Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <device/pci_ops.h> |
| 21 | #include "sb700.h" |
| 22 | |
| 23 | static void pci_init(struct device *dev) |
| 24 | { |
| 25 | u32 dword; |
| 26 | u16 word; |
| 27 | u8 byte; |
| 28 | |
| 29 | /* RPR 5.1 Enables the PCI-bridge subtractive decode */ |
| 30 | /* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */ |
| 31 | byte = pci_read_config8(dev, 0x4B); |
| 32 | byte |= 1 << 7; |
| 33 | pci_write_config8(dev, 0x4B, byte); |
| 34 | byte = pci_read_config8(dev, 0x40); |
| 35 | byte |= 1 << 5; |
| 36 | pci_write_config8(dev, 0x40, byte); |
| 37 | |
| 38 | /* RPR5.2 PCI-bridge upstream dual address window */ |
| 39 | /* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */ |
| 40 | byte = pci_read_config8(dev, 0x50); |
| 41 | byte |= 1 << 0; |
| 42 | pci_write_config8(dev, 0x50, byte); |
| 43 | |
| 44 | /* RPR 5.3 PCI bus 64-byte DMA read access */ |
| 45 | /* Enhance the PCI bus DMA performance */ |
| 46 | byte = pci_read_config8(dev, 0x4B); |
| 47 | byte |= 1 << 4; |
| 48 | pci_write_config8(dev, 0x4B, byte); |
| 49 | |
| 50 | /* RPR 5.4 Enables the PCIB writes to be cacheline aligned. */ |
| 51 | /* The size of the writes will be set in the Cacheline Register */ |
| 52 | byte = pci_read_config8(dev, 0x40); |
| 53 | byte |= 1 << 1; |
| 54 | pci_write_config8(dev, 0x40, byte); |
| 55 | |
| 56 | /* RPR 5.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */ |
| 57 | pci_write_config8(dev, 0x0D, 0x40); |
| 58 | pci_write_config8(dev, 0x1B, 0x40); |
| 59 | |
| 60 | /* RPR 5.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */ |
| 61 | byte = pci_read_config8(dev, 0x4B); |
| 62 | byte |= 1 << 6; |
| 63 | pci_write_config8(dev, 0x4B, byte); |
| 64 | |
| 65 | /* RPR 5.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */ |
| 66 | byte = pci_read_config8(dev, 0x4B); |
| 67 | byte |= 1 << 0; |
| 68 | pci_write_config8(dev, 0x4B, byte); |
| 69 | |
| 70 | /* RPR 5.8 Adjusts the GNT# de-assertion time */ |
| 71 | word = pci_read_config16(dev, 0x64); |
| 72 | word |= 1 << 12; |
| 73 | pci_write_config16(dev, 0x64, word); |
| 74 | |
| 75 | /* RPR 5.9 Fast Back to Back transactions support */ |
| 76 | byte = pci_read_config8(dev, 0x48); |
| 77 | byte |= 1 << 2; |
| 78 | /* pci_write_config8(dev, 0x48, byte); */ |
| 79 | |
| 80 | /* RPR 5.10 Enable Lock Operation */ |
| 81 | /* byte = pci_read_config8(dev, 0x48); */ |
| 82 | byte |= 1 << 3; |
| 83 | pci_write_config8(dev, 0x48, byte); |
| 84 | |
| 85 | /* RPR 5.11 Enable additional optional PCI clock */ |
| 86 | word = pci_read_config16(dev, 0x64); |
| 87 | word |= 1 << 8; |
| 88 | pci_write_config16(dev, 0x64, word); |
| 89 | |
| 90 | /* RPR 5.12 Enable One-Prefetch-Channel Mode */ |
| 91 | dword = pci_read_config32(dev, 0x64); |
| 92 | dword |= 1 << 20; |
| 93 | pci_write_config32(dev, 0x64, dword); |
| 94 | |
| 95 | /* RPR 5.13 Disable PCIB MSI Capability */ |
| 96 | byte = pci_read_config8(dev, 0x40); |
| 97 | byte &= ~(1 << 3); |
| 98 | pci_write_config8(dev, 0x40, byte); |
| 99 | |
| 100 | /* rpr5.14 Adjusting CLKRUN# */ |
| 101 | dword = pci_read_config32(dev, 0x64); |
| 102 | dword |= (1 << 15); |
| 103 | pci_write_config32(dev, 0x64, dword); |
| 104 | } |
| 105 | |
| 106 | static struct pci_operations lops_pci = { |
| 107 | .set_subsystem = 0, |
| 108 | }; |
| 109 | |
| 110 | static struct device_operations pci_ops = { |
| 111 | .read_resources = pci_bus_read_resources, |
| 112 | .set_resources = pci_dev_set_resources, |
| 113 | .enable_resources = pci_bus_enable_resources, |
| 114 | .init = pci_init, |
| 115 | .scan_bus = pci_scan_bridge, |
| 116 | .reset_bus = pci_bus_reset, |
| 117 | .ops_pci = &lops_pci, |
| 118 | }; |
| 119 | |
Stefan Reinauer | 8e96ba2 | 2010-03-16 23:33:29 +0000 | [diff] [blame] | 120 | static const struct pci_driver pci_driver __pci_driver = { |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 121 | .ops = &pci_ops, |
| 122 | .vendor = PCI_VENDOR_ID_ATI, |
| 123 | .device = PCI_DEVICE_ID_ATI_SB700_PCI, |
| 124 | }; |