Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef __RS780_H__ |
| 17 | #define __RS780_H__ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include "chip.h" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 22 | #include "rev.h" |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 23 | |
| 24 | #define NBMISC_INDEX 0x60 |
| 25 | #define NBHTIU_INDEX 0x94 |
| 26 | #define NBMC_INDEX 0xE8 |
| 27 | #define NBPCIE_INDEX 0xE0 |
| 28 | #define EXT_CONF_BASE_ADDRESS 0xE0000000 |
| 29 | #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 |
| 30 | |
| 31 | #define get_nb_rev(dev) pci_read_config8((dev), 0x89) |
| 32 | |
| 33 | typedef struct __PCIE_CFG__ { |
| 34 | u16 Config; |
| 35 | u8 ResetReleaseDelay; |
| 36 | u8 Gfx0Width; |
| 37 | u8 Gfx1Width; |
| 38 | u8 GfxPayload; |
| 39 | u8 GppPayload; |
| 40 | u16 PortDetect; |
| 41 | u8 PortHp; /* hot plug */ |
| 42 | u16 DbgConfig; |
| 43 | u32 DbgConfig2; |
| 44 | u8 GfxLx; |
| 45 | u8 GppLx; |
| 46 | u8 NBSBLx; |
| 47 | u8 PortSlotInit; |
| 48 | u8 Gfx0Pwr; |
| 49 | u8 Gfx1Pwr; |
| 50 | u8 GppPwr; |
| 51 | } PCIE_CFG; |
| 52 | |
| 53 | /* The Integrated Info Table */ |
| 54 | #define USHORT u16 |
| 55 | #define UCHAR u8 |
| 56 | #define ULONG u32 |
| 57 | |
| 58 | typedef struct _ATOM_COMMON_TABLE_HEADER |
| 59 | { |
| 60 | USHORT usStructureSize; |
| 61 | UCHAR ucTableFormatRevision; |
| 62 | UCHAR ucTableContentRevision; |
| 63 | }ATOM_COMMON_TABLE_HEADER; |
| 64 | |
| 65 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 |
| 66 | { |
| 67 | ATOM_COMMON_TABLE_HEADER sHeader; |
| 68 | ULONG ulBootUpEngineClock; //in 10kHz unit |
| 69 | ULONG ulReserved1[2]; //must be 0x0 for the reserved |
| 70 | ULONG ulBootUpUMAClock; //in 10kHz unit |
| 71 | ULONG ulBootUpSidePortClock; //in 10kHz unit |
| 72 | ULONG ulMinSidePortClock; //in 10kHz unit |
| 73 | ULONG ulReserved2[6]; //must be 0x0 for the reserved |
| 74 | ULONG ulSystemConfig; |
| 75 | //[0]=1: PowerExpress mode |
| 76 | // =0 Non-PowerExpress mode; |
Martin Roth | a9e3a75 | 2014-12-16 20:52:23 -0700 | [diff] [blame] | 77 | //[1]=1: system boots up at AMD overdriven state or user customized mode. In this case, driver will disable other power state in VBIOS table. |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 78 | // =0: system boots up at driver control state. Power state depends on VBIOS PP table. |
| 79 | //[2]=1: PWM method is used on NB voltage control. |
| 80 | // =0: GPIO method is used. |
| 81 | //[3]=1: Only one power state(Performance) will be supported. |
| 82 | // =0: Number of power states supported is from VBIOS PP table. |
| 83 | //[4]=1: CLMC is supported and enabled on current system. |
| 84 | // =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. |
| 85 | //[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. |
| 86 | // =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. |
| 87 | //[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and VBIOS PP table voltage drop/throttling request will be ignored. |
| 88 | // =0: Voltage settings is determined by VBIOS PP table. |
Martin Roth | a9e3a75 | 2014-12-16 20:52:23 -0700 | [diff] [blame] | 89 | //[7]=1: Enable CLMC Hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 90 | // =0: Enable regular CLMC mode, CDLD and CILR will be enabled. |
| 91 | //[8]=1: CDLF is supported and enabled by fuse //CHP 914 |
| 92 | // =0: CDLF is not supported and not enabled by fuses |
| 93 | ULONG ulBootUpReqDisplayVector; |
| 94 | ULONG ulOtherDisplayMisc; |
| 95 | ULONG ulDDISlot1Config; |
| 96 | ULONG ulDDISlot2Config; |
| 97 | UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved |
| 98 | UCHAR ucUMAChannelNumber; |
| 99 | UCHAR ucDockingPinBit; |
| 100 | UCHAR ucDockingPinPolarity; |
| 101 | ULONG ulDockingPinCFGInfo; |
| 102 | ULONG ulCPUCapInfo; |
| 103 | USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform |
| 104 | // 1 - non inverted waveform |
| 105 | USHORT usMaxNBVoltage; |
| 106 | USHORT usMinNBVoltage; |
| 107 | USHORT usBootUpNBVoltage; |
| 108 | ULONG ulHTLinkFreq; //in 10Khz |
| 109 | USHORT usMinHTLinkWidth; // if no CLMC, usMinHTLinkWidth should be equal to usMaxHTLinkWidth?? |
| 110 | USHORT usMaxHTLinkWidth; |
| 111 | USHORT usUMASyncStartDelay; // will be same as usK8SyncStartDelay on RS690 |
| 112 | USHORT usUMADataReturnTime; // will be same as usK8DataReturnTime on RS690 |
| 113 | USHORT usLinkStatusZeroTime; |
| 114 | USHORT usReserved; |
| 115 | ULONG ulHighVoltageHTLinkFreq; // in 10Khz |
| 116 | ULONG ulLowVoltageHTLinkFreq; // in 10Khz |
| 117 | USHORT usMaxUpStreamHTLinkWidth; |
| 118 | USHORT usMaxDownStreamHTLinkWidth; |
| 119 | USHORT usMinUpStreamHTLinkWidth; |
| 120 | USHORT usMinDownStreamHTLinkWidth; |
| 121 | ULONG ulReserved3[97]; //must be 0x0 |
| 122 | } ATOM_INTEGRATED_SYSTEM_INFO_V2; |
| 123 | |
| 124 | /* PCIE config flags */ |
| 125 | #define PCIE_DUALSLOT_CONFIG (1 << 0) |
| 126 | #define PCIE_OVERCLOCK_ENABLE (1 << 1) |
| 127 | #define PCIE_GPP_CLK_GATING (1 << 2) |
| 128 | #define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3) |
| 129 | #define PCIE_OFF_UNUSED_GFX_LANES (1 << 4) |
| 130 | #define PCIE_OFF_UNUSED_GPP_LANES (1 << 5) |
| 131 | #define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7) |
| 132 | #define PCIE_GFX_CLK_GATING (1 << 11) |
| 133 | #define PCIE_GFX_COMPLIANCE (1 << 14) |
| 134 | #define PCIE_GPP_COMPLIANCE (1 << 15) |
| 135 | |
| 136 | /* -------------------- ---------------------- |
| 137 | * NBMISCIND |
| 138 | ------------------- -----------------------*/ |
| 139 | #define PCIE_LINK_CFG 0x8 |
| 140 | #define PCIE_NBCFG_REG7 0x37 |
| 141 | #define STRAPS_OUTPUT_MUX_7 0x67 |
| 142 | #define STRAPS_OUTPUT_MUX_A 0x6a |
| 143 | |
| 144 | /* -------------------- ---------------------- |
| 145 | * PCIEIND |
| 146 | ------------------- -----------------------*/ |
| 147 | #define PCIE_CI_CNTL 0x20 |
| 148 | #define PCIE_LC_LINK_WIDTH 0xa2 |
| 149 | #define PCIE_LC_STATE0 0xa5 |
| 150 | #define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */ |
| 151 | |
| 152 | #define PCIE_CORE_INDEX_GFX (0x00 << 16) /* see 5.2.2 */ |
| 153 | #define PCIE_CORE_INDEX_GPPSB (0x01 << 16) |
| 154 | #define PCIE_CORE_INDEX_GPP (0x02 << 16) |
| 155 | #define PCIE_CORE_INDEX_BRDCST (0x03 << 16) |
| 156 | |
| 157 | /* contents of PCIE_NBCFG_REG7 */ |
| 158 | #define RECONFIG_GPPSB_EN (1 << 12) |
| 159 | #define RECONFIG_GPPSB_GPPSB (1 << 14) |
| 160 | #define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) |
| 161 | #define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17) |
| 162 | |
| 163 | /* contents of PCIE_VC0_RESOURCE_STATUS */ |
| 164 | #define VC_NEGOTIATION_PENDING (1 << 1) |
| 165 | |
| 166 | #define LC_STATE_RECONFIG_GPPSB 0x10 |
| 167 | |
| 168 | /* ------------------------------------------------ |
| 169 | * Global variable |
| 170 | * ------------------------------------------------- */ |
| 171 | extern PCIE_CFG AtiPcieCfg; |
| 172 | |
Martin Roth | a9e3a75 | 2014-12-16 20:52:23 -0700 | [diff] [blame] | 173 | /* ----------------- export functions ----------------- */ |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 174 | u32 nbmisc_read_index(device_t nb_dev, u32 index); |
| 175 | void nbmisc_write_index(device_t nb_dev, u32 index, u32 data); |
| 176 | u32 nbpcie_p_read_index(device_t dev, u32 index); |
| 177 | void nbpcie_p_write_index(device_t dev, u32 index, u32 data); |
| 178 | u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); |
| 179 | void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); |
| 180 | u32 htiu_read_index(device_t nb_dev, u32 index); |
| 181 | void htiu_write_index(device_t nb_dev, u32 index, u32 data); |
| 182 | u32 nbmc_read_index(device_t nb_dev, u32 index); |
| 183 | void nbmc_write_index(device_t nb_dev, u32 index, u32 data); |
| 184 | |
| 185 | u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); |
| 186 | void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); |
| 187 | |
| 188 | void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
| 189 | void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val); |
| 190 | void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
| 191 | void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
| 192 | void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val); |
| 193 | void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val); |
| 194 | void rs780_set_tom(device_t nb_dev); |
| 195 | |
| 196 | void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); |
| 197 | void enable_pcie_bar3(device_t nb_dev); |
| 198 | void disable_pcie_bar3(device_t nb_dev); |
| 199 | |
| 200 | void rs780_enable(device_t dev); |
| 201 | void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); |
| 202 | void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port); |
| 203 | void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); |
| 204 | void config_gpp_core(device_t nb_dev, device_t sb_dev); |
| 205 | void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); |
| 206 | u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 207 | u32 extractbit(u32 data, int bit_number); |
| 208 | u32 extractbits(u32 source, int lsb, int msb); |
| 209 | int cpuidFamily(void); |
| 210 | int is_family0Fh(void); |
| 211 | int is_family10h(void); |
Kerry Sheh | 8c69b1d | 2011-09-14 10:04:19 +0800 | [diff] [blame] | 212 | void pcie_hide_unused_ports(device_t nb_dev); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 213 | #endif /* RS780_H */ |