Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <arch/io.h> |
Timothy Pearson | 1eaaa0e | 2015-08-14 15:20:42 -0500 | [diff] [blame] | 18 | #include <arch/acpi.h> |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <device/pci_ops.h> |
| 23 | #include <cpu/x86/msr.h> |
| 24 | #include <cpu/amd/mtrr.h> |
| 25 | #include "rs780.h" |
| 26 | |
| 27 | /***************************************** |
| 28 | * rs780_config_misc_clk() |
| 29 | *****************************************/ |
| 30 | void static rs780_config_misc_clk(device_t nb_dev) |
| 31 | { |
| 32 | u32 reg; |
| 33 | u16 word; |
| 34 | u8 byte; |
| 35 | struct bus pbus; /* fake bus for dev0 fun1 */ |
| 36 | |
| 37 | reg = pci_read_config32(nb_dev, 0x4c); |
| 38 | reg |= 1 << 0; |
| 39 | pci_write_config32(nb_dev, 0x4c, reg); |
| 40 | |
| 41 | word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8); |
| 42 | word &= 0xf00; |
| 43 | pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word); |
| 44 | |
| 45 | word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8); |
| 46 | word &= ~((1 << 12) | (1 << 13) | (1 << 14)); |
| 47 | word |= 1 << 13; |
| 48 | pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word); |
| 49 | |
| 50 | reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); |
| 51 | reg &= ~((1 << 16) | (1 << 24) | (1 << 28)); |
| 52 | pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); |
| 53 | |
| 54 | reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); |
| 55 | reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25)); |
| 56 | reg |= 1 << 13; |
| 57 | pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); |
| 58 | |
| 59 | reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); |
| 60 | reg |= 1 << 24; |
| 61 | pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); |
| 62 | |
| 63 | reg = nbmc_read_index(nb_dev, 0x7a); |
| 64 | reg &= ~0x3f; |
| 65 | reg |= 1 << 2; |
| 66 | reg &= ~(1 << 6); |
| 67 | set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); |
| 68 | nbmc_write_index(nb_dev, 0x7a, reg); |
| 69 | /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */ |
| 70 | reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); |
| 71 | reg &= ~(1 << 23); |
| 72 | reg |= 1 << 24; |
| 73 | pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); |
| 74 | |
| 75 | /* Programming NB CLK table. */ |
| 76 | byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0); |
| 77 | byte |= 0x01; |
| 78 | pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte); |
| 79 | |
| 80 | #if 0 |
| 81 | /* Powerdown reference clock to graphics core PLL in northbridge only mode */ |
| 82 | reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); |
| 83 | reg |= 1 << 21; |
| 84 | pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); |
| 85 | |
| 86 | /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */ |
| 87 | reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); |
| 88 | reg |= (1 << 23) | (1 << 24); |
| 89 | pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); |
| 90 | |
| 91 | /* Powerdown clock to memory controller in northbridge only mode */ |
| 92 | byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4); |
| 93 | byte |= 1 << 0; |
| 94 | pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); |
| 95 | |
| 96 | /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ |
| 97 | /* TODO: */ |
| 98 | #endif |
| 99 | |
| 100 | reg = pci_read_config32(nb_dev, 0x4c); |
| 101 | reg &= ~(1 << 0); |
| 102 | pci_write_config32(nb_dev, 0x4c, reg); |
| 103 | |
| 104 | set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8); |
| 105 | } |
| 106 | |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 107 | static u32 get_vid_did(device_t dev) |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 108 | { |
| 109 | return pci_read_config32(dev, 0); |
| 110 | } |
| 111 | |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 112 | static void rs780_nb_pci_table(device_t nb_dev) |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 113 | { /* NBPOR_InitPOR function. */ |
| 114 | u8 temp8; |
| 115 | u16 temp16; |
| 116 | u32 temp32; |
| 117 | |
| 118 | /* Program NB PCI table. */ |
| 119 | temp16 = pci_read_config16(nb_dev, 0x04); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 120 | printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 121 | temp32 = pci_read_config32(nb_dev, 0x84); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 123 | |
| 124 | pci_write_config8(nb_dev, 0x4c, 0x42); |
| 125 | |
| 126 | temp8 = pci_read_config8(nb_dev, 0x4e); |
| 127 | temp8 |= 0x05; |
| 128 | pci_write_config8(nb_dev, 0x4e, temp8); |
| 129 | |
| 130 | temp32 = pci_read_config32(nb_dev, 0x4c); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 131 | printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 132 | |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 133 | /* set temporary NB TOM to 0x40000000. */ |
| 134 | rs780_set_tom(nb_dev); |
| 135 | |
| 136 | /* Program NB HTIU table. */ |
| 137 | #if 0 |
| 138 | set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); |
| 139 | set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); |
| 140 | set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); |
| 141 | set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); |
| 142 | set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); |
| 143 | set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11); |
| 144 | set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); |
| 145 | set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1); |
| 146 | set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30); |
| 147 | set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); |
| 148 | set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); |
| 149 | set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); |
| 150 | |
| 151 | /* Program NB MISC table. */ |
| 152 | set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180); |
| 153 | set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106); |
| 154 | set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100); |
| 155 | set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100); |
| 156 | set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100); |
| 157 | set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100); |
| 158 | set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100); |
| 159 | set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100); |
| 160 | set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100); |
| 161 | set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100); |
| 162 | set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0); |
| 163 | set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0); |
| 164 | set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5); |
| 165 | set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10); |
| 166 | set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10); |
| 167 | set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25); |
| 168 | set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24); |
| 169 | set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28); |
| 170 | set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13); |
| 171 | set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10); |
| 172 | set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30); |
| 173 | set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0); |
| 174 | set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0); |
| 175 | set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17); |
| 176 | set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23); |
| 177 | set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22); |
| 178 | set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48); |
| 179 | |
| 180 | /* the last two step. */ |
| 181 | set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8); |
| 182 | set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4); |
| 183 | #endif |
| 184 | } |
| 185 | |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 186 | static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 187 | { |
| 188 | /* NB_InitGFXStraps */ |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 189 | u32 MMIOBase, apc04, apc18, apc24, romstrap2; |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 190 | volatile u32 * strap; |
| 191 | |
Kyösti Mälkki | 1e60839 | 2015-03-18 10:55:06 +0200 | [diff] [blame] | 192 | /* Choose a base address that is unused and routed to the RS780. */ |
| 193 | MMIOBase = 0xFFB00000; |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 194 | |
Kyösti Mälkki | 1e60839 | 2015-03-18 10:55:06 +0200 | [diff] [blame] | 195 | /* 1E: NB_BIF_SPARE */ |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 196 | set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7); |
| 197 | /* Set a temporary Bus number. */ |
| 198 | apc18 = pci_read_config32(dev, 0x18); |
| 199 | pci_write_config32(dev, 0x18, 0x010100); |
Kyösti Mälkki | 1e60839 | 2015-03-18 10:55:06 +0200 | [diff] [blame] | 200 | /* Set MMIO window for AGP target(graphics controller). */ |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 201 | apc24 = pci_read_config32(dev, 0x24); |
| 202 | pci_write_config32(dev, 0x24, (MMIOBase>>16)+((MMIOBase+0x20000)&0xffff0000)); |
| 203 | /* Enable memory access. */ |
| 204 | apc04 = pci_read_config32(dev, 0x04); |
| 205 | pci_write_config8(dev, 0x04, 0x02); |
| 206 | |
| 207 | /* Program Straps. */ |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 208 | romstrap2 = 1 << 26; // enables audio function |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 209 | #if CONFIG_GFXUMA |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 210 | // bits 7-9: aperture size |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 211 | // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 212 | if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; |
| 213 | if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7; |
| 214 | if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7; |
| 215 | if (uma_memory_size == 0x10000000) romstrap2 |= 1 << 7; |
| 216 | if (uma_memory_size == 0x20000000) romstrap2 |= 4 << 7; |
| 217 | if (uma_memory_size == 0x40000000) romstrap2 |= 5 << 7; |
| 218 | if (uma_memory_size == 0x80000000) romstrap2 |= 6 << 7; |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 219 | #endif |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 220 | strap = (volatile u32 *)(MMIOBase + 0x15020); |
| 221 | *strap = romstrap2; |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 222 | strap = (volatile u32 *)(MMIOBase + 0x15000); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 223 | *strap = 0x2c006300; |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 224 | strap = (volatile u32 *)(MMIOBase + 0x15010); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 225 | *strap = 0x03015330; |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 226 | strap = (volatile u32 *)(MMIOBase + 0x15020); |
| 227 | *strap = romstrap2 | 0x00000040; |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 228 | strap = (volatile u32 *)(MMIOBase + 0x15030); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 229 | *strap = 0x00001002; |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 230 | strap = (volatile u32 *)(MMIOBase + 0x15040); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 231 | *strap = 0x00000000; |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 232 | strap = (volatile u32 *)(MMIOBase + 0x15050); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 233 | *strap = 0x00000000; |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 234 | strap = (volatile u32 *)(MMIOBase + 0x15220); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 235 | *strap = 0x03c03800; |
Zheng Bao | b63bdbe | 2010-03-23 06:46:01 +0000 | [diff] [blame] | 236 | strap = (volatile u32 *)(MMIOBase + 0x15060); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 237 | *strap = 0x00000000; |
| 238 | |
| 239 | /* BIF switches into normal functional mode. */ |
| 240 | set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5); |
| 241 | |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 242 | /* NB Revision is A12 or newer */ |
| 243 | if (get_nb_rev(nb_dev) >= REV_RS780_A12) |
| 244 | set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 245 | |
| 246 | /* Restore APC04, APC18, APC24. */ |
| 247 | pci_write_config32(dev, 0x04, apc04); |
| 248 | pci_write_config32(dev, 0x18, apc18); |
| 249 | pci_write_config32(dev, 0x24, apc24); |
| 250 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 251 | printk(BIOS_INFO, "GC is accessible from now on.\n"); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | /*********************************************** |
| 255 | * 0:00.0 NBCFG : |
| 256 | * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default |
| 257 | * 0:01.0 P2P Internal: |
| 258 | * 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 259 | * 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 260 | * 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 261 | * 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 262 | * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 263 | * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 264 | * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 |
| 265 | * case 0 will be called twice, one is by cpu in hypertransport.c line458, |
| 266 | * the other is by rs780. |
| 267 | ***********************************************/ |
| 268 | void rs780_enable(device_t dev) |
| 269 | { |
| 270 | device_t nb_dev = 0, sb_dev = 0; |
| 271 | int dev_ind; |
| 272 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 273 | printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 274 | |
| 275 | nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 276 | if (!nb_dev) { |
| 277 | die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n"); |
| 278 | /* NOT REACHED */ |
| 279 | } |
| 280 | |
| 281 | /* sb_dev (dev 8) is a bridge that links to southbridge. */ |
| 282 | sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); |
| 283 | if (!sb_dev) { |
| 284 | die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n"); |
| 285 | /* NOT REACHED */ |
| 286 | } |
| 287 | |
| 288 | dev_ind = dev->path.pci.devfn >> 3; |
| 289 | switch (dev_ind) { |
| 290 | case 0: /* bus0, dev0, fun0; */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 291 | printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 292 | enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
| 293 | config_gpp_core(nb_dev, sb_dev); |
| 294 | rs780_gpp_sb_init(nb_dev, sb_dev, 8); |
| 295 | /* 5.10.8.4. set SB payload size: 64byte */ |
| 296 | set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11); |
| 297 | |
| 298 | /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */ |
| 299 | rs780_config_misc_clk(nb_dev); |
| 300 | |
| 301 | rs780_nb_pci_table(nb_dev); |
| 302 | break; |
| 303 | |
| 304 | case 1: /* bus0, dev1, APC. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 305 | printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 306 | rs780_nb_gfx_dev_table(nb_dev, dev); |
| 307 | break; |
| 308 | case 2: /* bus0, dev2,3, two GFX */ |
| 309 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 310 | printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 311 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
| 312 | (dev->enabled ? 0 : 1) << dev_ind); |
| 313 | if (dev->enabled) |
| 314 | rs780_gfx_init(nb_dev, dev, dev_ind); |
| 315 | break; |
| 316 | case 4: /* bus0, dev4-7, four GPPSB */ |
| 317 | case 5: |
| 318 | case 6: |
| 319 | case 7: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 320 | printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 321 | dev->enabled); |
| 322 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
| 323 | (dev->enabled ? 0 : 1) << dev_ind); |
| 324 | if (dev->enabled) |
| 325 | rs780_gpp_sb_init(nb_dev, dev, dev_ind); |
| 326 | break; |
| 327 | case 8: /* bus0, dev8, SB */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 328 | printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 329 | set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, |
| 330 | (dev->enabled ? 1 : 0) << 6); |
| 331 | if (dev->enabled) |
| 332 | rs780_gpp_sb_init(nb_dev, dev, dev_ind); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 333 | break; |
| 334 | case 9: /* bus 0, dev 9,10, GPP */ |
| 335 | case 10: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 336 | printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 337 | dev->enabled); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 338 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
| 339 | (dev->enabled ? 0 : 1) << (7 + dev_ind)); |
| 340 | if (dev->enabled) |
| 341 | rs780_gpp_sb_init(nb_dev, dev, dev_ind); |
Scott Duplichan | 88dc531 | 2010-11-24 00:39:44 +0000 | [diff] [blame] | 342 | |
Kerry Sheh | 8c69b1d | 2011-09-14 10:04:19 +0800 | [diff] [blame] | 343 | if (dev_ind == 10) { |
| 344 | disable_pcie_bar3(nb_dev); |
| 345 | pcie_hide_unused_ports(nb_dev); |
| 346 | } |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 347 | break; |
| 348 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 349 | printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 350 | } |
| 351 | } |
| 352 | |
Timothy Pearson | 1eaaa0e | 2015-08-14 15:20:42 -0500 | [diff] [blame] | 353 | #if !IS_ENABLED(CONFIG_AMD_SB_CIMX) |
| 354 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 355 | { |
| 356 | /* FIXME |
| 357 | * Leave table blank until proper contents |
| 358 | * are determined. |
| 359 | */ |
| 360 | return current; |
| 361 | } |
| 362 | #endif |
| 363 | |
Zheng Bao | 1088bbf | 2010-03-16 01:41:14 +0000 | [diff] [blame] | 364 | struct chip_operations southbridge_amd_rs780_ops = { |
| 365 | CHIP_NAME("ATI RS780") |
| 366 | .enable_dev = rs780_enable, |
| 367 | }; |