Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Uwe Hermann | 344e457 | 2007-05-22 10:12:49 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Uwe Hermann | 344e457 | 2007-05-22 10:12:49 +0000 | [diff] [blame] | 14 | */ |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 15 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 16 | /* |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 17 | * cs5536_early_setup.c: Early chipset initialization for CS5536 companion device |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 18 | * This file implements the initialization sequence documented in section 4.2 of |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 19 | * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide. |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 20 | */ |
| 21 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 22 | /** |
| 23 | * @brief Setup PCI IDSEL for CS5536 |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 24 | */ |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 25 | static void cs5536_setup_extmsr(void) |
| 26 | { |
| 27 | msr_t msr; |
| 28 | |
| 29 | /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */ |
| 30 | msr.hi = msr.lo = 0x00000000; |
Stefan Reinauer | 78b4033 | 2010-03-17 22:09:26 +0000 | [diff] [blame] | 31 | #if CS5536_GLINK_PORT_NUM <= 4 |
| 32 | msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); |
| 33 | #else |
| 34 | msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); |
| 35 | #endif |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 36 | wrmsr(GLPCI_ExtMSR, msr); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 37 | } |
| 38 | |
| 39 | static void cs5536_setup_idsel(void) |
| 40 | { |
| 41 | /* write IDSEL to the write once register at address 0x0000 */ |
| 42 | outl(0x1 << (CS5536_DEV_NUM + 10), 0); |
| 43 | } |
| 44 | |
| 45 | static void cs5536_usb_swapsif(void) |
| 46 | { |
| 47 | msr_t msr; |
| 48 | |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 49 | msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 50 | //USB Serial short detect bit. |
| 51 | if (msr.hi & 0x10) { |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 52 | /* We need to preserve bits 32,33,35 and not clear any BIST |
| 53 | * error, but clear the SERSHRT error bit */ |
| 54 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 55 | msr.hi &= 0xFFFFFFFB; |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 56 | wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 57 | } |
| 58 | } |
| 59 | |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 60 | static void cs5536_setup_iobase(void) |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 61 | { |
| 62 | msr_t msr; |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 63 | /* setup LBAR for SMBus controller */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 64 | msr.hi = 0x0000f001; |
| 65 | msr.lo = SMBUS_IO_BASE; |
| 66 | wrmsr(MDD_LBAR_SMB, msr); |
| 67 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 68 | /* setup LBAR for GPIO */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 69 | msr.hi = 0x0000f001; |
| 70 | msr.lo = GPIO_IO_BASE; |
| 71 | wrmsr(MDD_LBAR_GPIO, msr); |
| 72 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 73 | /* setup LBAR for MFGPT */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 74 | msr.hi = 0x0000f001; |
| 75 | msr.lo = MFGPT_IO_BASE; |
| 76 | wrmsr(MDD_LBAR_MFGPT, msr); |
| 77 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 78 | /* setup LBAR for ACPI */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 79 | msr.hi = 0x0000f001; |
| 80 | msr.lo = ACPI_IO_BASE; |
| 81 | wrmsr(MDD_LBAR_ACPI, msr); |
| 82 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 83 | /* setup LBAR for PM Support */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 84 | msr.hi = 0x0000f001; |
| 85 | msr.lo = PMS_IO_BASE; |
| 86 | wrmsr(MDD_LBAR_PMS, msr); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 87 | } |
| 88 | |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 89 | static void cs5536_setup_power_button(void) |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 90 | { |
Peter Stuge | 51eafde | 2010-10-13 06:23:02 +0000 | [diff] [blame] | 91 | #if CONFIG_ENABLE_POWER_BUTTON |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 92 | outl(0x40020000, PMS_IO_BASE + 0x40); |
Peter Stuge | 51eafde | 2010-10-13 06:23:02 +0000 | [diff] [blame] | 93 | #endif |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 94 | |
Marc Jones | ddf845f | 2007-05-10 23:22:27 +0000 | [diff] [blame] | 95 | /* setup WORK_AUX/GPIO24, it is the external signal for 5536 |
| 96 | * vsb_work_aux controls all voltage rails except Vstandby & Vmem. |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 97 | * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. |
Marc Jones | ddf845f | 2007-05-10 23:22:27 +0000 | [diff] [blame] | 98 | * If WORK_AUX/GPIO24 is not enabled then soft-off will not work. |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 99 | */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 100 | outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); |
| 101 | outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 102 | |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | static void cs5536_setup_gpio(void) |
| 106 | { |
| 107 | uint32_t val; |
| 108 | |
| 109 | /* setup GPIO pins 14/15 for SDA/SCL */ |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 110 | val = GPIOL_15_SET | GPIOL_14_SET; |
| 111 | /* Output Enable */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 112 | outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 113 | /* Output AUX1 */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 114 | outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 115 | /* Input Enable */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 116 | outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 117 | /* Input AUX1 */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 118 | outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 119 | } |
| 120 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 121 | void cs5536_disable_internal_uart(void) |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 122 | { |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 123 | msr_t msr; |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 124 | /* The UARTs default to enabled. |
Marc Jones | ddf845f | 2007-05-10 23:22:27 +0000 | [diff] [blame] | 125 | * Disable and reset them and configure them later. (SIO init) |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 126 | */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 127 | msr = rdmsr(MDD_UART1_CONF); |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 128 | msr.lo = 1; // reset |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 129 | wrmsr(MDD_UART1_CONF, msr); |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 130 | msr.lo = 0; // disabled |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 131 | wrmsr(MDD_UART1_CONF, msr); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 132 | |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 133 | msr = rdmsr(MDD_UART2_CONF); |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 134 | msr.lo = 1; // reset |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 135 | wrmsr(MDD_UART2_CONF, msr); |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 136 | msr.lo = 0; // disabled |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 137 | wrmsr(MDD_UART2_CONF, msr); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | static void cs5536_setup_cis_mode(void) |
| 141 | { |
| 142 | msr_t msr; |
| 143 | |
Nils Jacobs | 8098e42 | 2010-12-30 19:23:29 +0000 | [diff] [blame] | 144 | /* Setup CPU serial SouthBridge interface to mode C. */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 145 | msr = rdmsr(GLPCI_SB_CTRL); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 146 | msr.lo &= ~0x18; |
| 147 | msr.lo |= 0x10; |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 148 | wrmsr(GLPCI_SB_CTRL, msr); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 149 | } |
| 150 | |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 151 | /** |
| 152 | * Enable the on-chip UART. |
| 153 | * |
| 154 | * See page 412 of the AMD Geode CS5536 Companion Device data book. |
| 155 | */ |
Stefan Reinauer | 720297c | 2010-04-02 22:11:20 +0000 | [diff] [blame] | 156 | static void cs5536_setup_onchipuart1(void) |
Li-Ta Lo | b7a09b4 | 2006-04-26 22:07:16 +0000 | [diff] [blame] | 157 | { |
Ronald G. Minnich | 2f19800 | 2006-04-23 19:21:12 +0000 | [diff] [blame] | 158 | msr_t msr; |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 159 | |
| 160 | /* Setup early for polling only mode. |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 161 | * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1. |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 162 | * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 163 | * 2. Enable UART I/O space in MDD. |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 164 | * MSR 0x51400014 bit 18:16 |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 165 | * 3. Enable UART controller. |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 166 | * MSR 0x5140003A bit 0, 1 |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 167 | */ |
| 168 | |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 169 | /* GPIO8 - UART1_TX */ |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 170 | /* Set: Output Enable (0x4) */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 171 | outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 172 | /* Set: OUTAUX1 Select (0x10) */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 173 | outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); |
Stefan Reinauer | 5a559d4 | 2010-02-03 13:49:24 +0000 | [diff] [blame] | 174 | |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 175 | /* GPIO9 - UART1_RX */ |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 176 | /* Set: Input Enable (0x20) */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 177 | outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 178 | /* Set: INAUX1 Select (0x34) */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 179 | outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 180 | |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 181 | /* Set address to 0x3F8. */ |
Ronald G. Minnich | 070a10f | 2006-05-04 23:05:49 +0000 | [diff] [blame] | 182 | msr = rdmsr(MDD_LEG_IO); |
| 183 | msr.lo |= 0x7 << 16; |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 184 | wrmsr(MDD_LEG_IO, msr); |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 185 | |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 186 | /* Bit 1 = DEVEN (device enable) |
| 187 | * Bit 4 = EN_BANKS (allow access to the upper banks) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 188 | */ |
| 189 | msr.lo = (1 << 4) | (1 << 1); |
| 190 | msr.hi = 0; |
| 191 | |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 192 | /* Enable COM1. */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 193 | wrmsr(MDD_UART1_CONF, msr); |
Ronald G. Minnich | 2f19800 | 2006-04-23 19:21:12 +0000 | [diff] [blame] | 194 | } |
| 195 | |
Stefan Reinauer | 720297c | 2010-04-02 22:11:20 +0000 | [diff] [blame] | 196 | static void cs5536_setup_onchipuart2(void) |
Edwin Beasant | e30db0e | 2010-02-09 10:22:33 +0000 | [diff] [blame] | 197 | { |
| 198 | msr_t msr; |
| 199 | |
| 200 | /* GPIO4 - UART2_TX */ |
| 201 | /* Set: Output Enable (0x4) */ |
| 202 | outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); |
| 203 | /* Set: OUTAUX1 Select (0x10) */ |
| 204 | outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); |
| 205 | /* GPIO4 - UART2_RX */ |
| 206 | /* Set: Input Enable (0x20) */ |
| 207 | outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); |
| 208 | /* Set: INAUX1 Select (0x34) */ |
| 209 | outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); |
| 210 | |
| 211 | /* Set: GPIO 3 + 3 Pull Up (0x18) */ |
| 212 | outl(GPIOL_3_SET | GPIOL_4_SET, |
| 213 | GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); |
| 214 | |
| 215 | /* set address to 2F8 */ |
| 216 | msr = rdmsr(MDD_LEG_IO); |
| 217 | msr.lo |= 0x5 << 20; |
| 218 | wrmsr(MDD_LEG_IO, msr); |
| 219 | |
| 220 | /* Bit 1 = DEVEN (device enable) |
| 221 | * Bit 4 = EN_BANKS (allow access to the upper banks |
| 222 | */ |
| 223 | msr.lo = (1 << 4) | (1 << 1); |
| 224 | msr.hi = 0; |
| 225 | |
| 226 | /* enable COM2 */ |
| 227 | wrmsr(MDD_UART2_CONF, msr); |
| 228 | } |
| 229 | |
| 230 | void cs5536_setup_onchipuart(int uart) |
| 231 | { |
| 232 | switch (uart) { |
| 233 | case 1: |
| 234 | cs5536_setup_onchipuart1(); |
| 235 | break; |
| 236 | case 2: |
| 237 | cs5536_setup_onchipuart2(); |
| 238 | break; |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 243 | /* note: you can't do prints in here in most cases, |
| 244 | * and we don't want to hang on serial, so they are |
| 245 | * commented out |
Ronald G. Minnich | 1656c18 | 2006-05-05 03:54:31 +0000 | [diff] [blame] | 246 | */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 247 | static void cs5536_early_setup(void) |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 248 | { |
| 249 | msr_t msr; |
| 250 | |
| 251 | cs5536_setup_extmsr(); |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 252 | cs5536_setup_cis_mode(); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 253 | |
| 254 | msr = rdmsr(GLCP_SYS_RSTPLL); |
| 255 | if (msr.lo & (0x3f << 26)) { |
| 256 | /* PLL is already set and we are reboot from PLL reset */ |
Stefan Reinauer | 5ab52dd | 2015-01-05 13:01:01 -0800 | [diff] [blame] | 257 | //printk(BIOS_DEBUG, "reboot from BIOS reset\n"); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 258 | return; |
| 259 | } |
Stefan Reinauer | 5ab52dd | 2015-01-05 13:01:01 -0800 | [diff] [blame] | 260 | //printk(BIOS_DEBUG, "Setup idsel\n"); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 261 | cs5536_setup_idsel(); |
Stefan Reinauer | 5ab52dd | 2015-01-05 13:01:01 -0800 | [diff] [blame] | 262 | //printk(BIOS_DEBUG, "Setup iobase\n"); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 263 | cs5536_usb_swapsif(); |
| 264 | cs5536_setup_iobase(); |
Stefan Reinauer | 5ab52dd | 2015-01-05 13:01:01 -0800 | [diff] [blame] | 265 | //printk(BIOS_DEBUG, "Setup gpio\n"); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 266 | cs5536_setup_gpio(); |
Stefan Reinauer | 5ab52dd | 2015-01-05 13:01:01 -0800 | [diff] [blame] | 267 | //printk(BIOS_DEBUG, "Setup smbus\n"); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 268 | cs5536_enable_smbus(); |
Stefan Reinauer | 5ab52dd | 2015-01-05 13:01:01 -0800 | [diff] [blame] | 269 | //printk(BIOS_DEBUG, "Setup power button\n"); |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 270 | cs5536_setup_power_button(); |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 271 | } |