Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Uwe Hermann | 344e457 | 2007-05-22 10:12:49 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Paul Menzel | a8ae1c6 | 2013-02-20 13:21:20 +0100 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
Uwe Hermann | 344e457 | 2007-05-22 10:12:49 +0000 | [diff] [blame] | 13 | * GNU General Public License for more details. |
Uwe Hermann | 344e457 | 2007-05-22 10:12:49 +0000 | [diff] [blame] | 14 | */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 15 | |
Li-Ta Lo | a910a3a | 2006-04-20 22:54:32 +0000 | [diff] [blame] | 16 | #ifndef _CS5536_H |
| 17 | #define _CS5536_H |
Li-Ta Lo | 5d69896 | 2006-04-20 21:31:47 +0000 | [diff] [blame] | 18 | |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 19 | #define Cx5536_ID ( 0x208F1022) |
| 20 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 21 | /* SouthBridge Equates */ |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 22 | #define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */ |
| 23 | #define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 24 | #define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */ |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 25 | #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 26 | |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 27 | #define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 28 | #define SMBUS_IO_BASE 0x6000 |
| 29 | #define GPIO_IO_BASE 0x6100 |
| 30 | #define MFGPT_IO_BASE 0x6200 |
| 31 | #define ACPI_IO_BASE 0x9C00 |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 32 | #define PMS_IO_BASE 0x9D00 |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 33 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 34 | #define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 35 | #define CHIPSET_DEV_NUM 15 |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 36 | #define IDSEL_BASE 11 /* bit 11 = device 1 */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 37 | |
| 38 | /* Cs5536 as follows. */ |
| 39 | /* SB_GLIU */ |
| 40 | /* port0 - GLIU */ |
| 41 | /* port1 - GLPCI */ |
| 42 | /* port2 - USB Controller #2 */ |
| 43 | /* port3 - ATA-5 Controller */ |
| 44 | /* port4 - MDD */ |
| 45 | /* port5 - AC97 */ |
| 46 | /* port6 - USB Controller #1 */ |
| 47 | /* port7 - GLCP */ |
| 48 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 49 | #define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ |
| 50 | #define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 51 | #define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ |
| 52 | #define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */ |
| 53 | #define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */ |
| 54 | #define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */ |
| 55 | #define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */ |
| 56 | #define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */ |
| 57 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 58 | /* GLIU */ |
| 59 | #define GLIU_SB_GLD_MSR_CAP (MSR_SB_GLIU + 0x00) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 60 | #define GLIU_SB_GLD_MSR_CONF (MSR_SB_GLIU + 0x01) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 61 | #define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 62 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 63 | /* USB1 */ |
| 64 | #define USB1_SB_GLD_MSR_CAP (MSR_SB_USB1 + 0x00) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 65 | #define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 66 | #define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 67 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 68 | /* USB2 */ |
| 69 | #define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 70 | #define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 71 | #define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */ |
| 72 | #define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 73 | #define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05) |
| 74 | #define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08) |
| 75 | #define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09) |
| 76 | #define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A) |
Jordan Crouse | 2a133f7 | 2007-05-10 18:43:57 +0000 | [diff] [blame] | 77 | #define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 78 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 79 | /* ATA */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 80 | #define ATA_SB_GLD_MSR_CAP (MSR_SB_ATA + 0x00) |
| 81 | #define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01) |
| 82 | #define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03) |
| 83 | #define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 84 | #define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 85 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 86 | /* AC97 */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 87 | #define AC97_SB_GLD_MSR_CAP (MSR_SB_AC97 + 0x00) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 88 | #define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 89 | #define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04) |
| 90 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 91 | /* GLPCI */ |
| 92 | #define GLPCI_SB_GLD_MSR_CAP (MSR_SB_GLPCI + 0x00) |
| 93 | #define GLPCI_SB_GLD_MSR_CONF (MSR_SB_GLPCI + 0x01) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 94 | #define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04) |
| 95 | #define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 96 | #define GLPCI_CRTL_PPIDE_SET (1 << 17) |
| 97 | |
| 98 | /* GLCP */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 99 | #define GLCP_SB_GLD_MSR_CAP (MSR_SB_GLCP + 0x00) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 100 | #define GLCP_SB_GLD_MSR_CONF (MSR_SB_GLCP + 0x01) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 101 | #define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04) |
| 102 | #define GLCP_SB_CLKOFF (MSR_SB_GLCP + 0x10) |
| 103 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 104 | /* MDD */ |
| 105 | #define MDD_SB_GLD_MSR_CAP (MSR_SB_MDD + 0x00) |
| 106 | #define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01) |
| 107 | #define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04) |
| 108 | #define LBAR_EN (0x01) |
| 109 | #define IO_MASK (0x1f) |
| 110 | #define MEM_MASK (0x0FFFFF) |
| 111 | #define MDD_LBAR_IRQ (MSR_SB_MDD + 0x08) |
| 112 | #define MDD_LBAR_KEL1 (MSR_SB_MDD + 0x09) |
| 113 | #define MDD_LBAR_KEL2 (MSR_SB_MDD + 0x0A) |
| 114 | #define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B) |
| 115 | #define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C) |
| 116 | #define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D) |
| 117 | #define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E) |
| 118 | #define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 119 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 120 | #define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10) |
| 121 | #define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11) |
| 122 | #define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12) |
| 123 | #define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13) |
| 124 | #define MDD_LEG_IO (MSR_SB_MDD + 0x14) |
| 125 | #define MDD_PIN_OPT (MSR_SB_MDD + 0x15) |
| 126 | #define MDD_SOFT_IRQ (MSR_SB_MDD + 0x16) |
| 127 | #define MDD_SOFT_RESET (MSR_SB_MDD + 0x17) |
| 128 | #define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18) |
| 129 | #define MDD_NORF_T01 (MSR_SB_MDD + 0x19) |
| 130 | #define MDD_NORF_T23 (MSR_SB_MDD + 0x1A) |
| 131 | #define MDD_NANDF_DATA (MSR_SB_MDD + 0x1B) |
| 132 | #define MDD_NADF_CNTL (MSR_SB_MDD + 0x1C) |
| 133 | #define MDD_AC_DMA (MSR_SB_MDD + 0x1E) |
| 134 | #define MDD_KEL_CNTRL (MSR_SB_MDD + 0x1F) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 135 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 136 | #define MDD_IRQM_YLOW (MSR_SB_MDD + 0x20) |
| 137 | #define MDD_IRQM_YHIGH (MSR_SB_MDD + 0x21) |
| 138 | #define MDD_IRQM_ZLOW (MSR_SB_MDD + 0x22) |
| 139 | #define MDD_IRQM_ZHIGH (MSR_SB_MDD + 0x23) |
| 140 | #define MDD_IRQM_PRIM (MSR_SB_MDD + 0x24) |
| 141 | #define MDD_IRQM_LPC (MSR_SB_MDD + 0x25) |
| 142 | #define MDD_IRQM_LXIRR (MSR_SB_MDD + 0x26) |
| 143 | #define MDD_IRQM_HXIRR (MSR_SB_MDD + 0x27) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 144 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 145 | #define MDD_MFGPT_IRQ (MSR_SB_MDD + 0x28) |
| 146 | #define MDD_MFGPT_NR (MSR_SB_MDD + 0x29) |
| 147 | #define MDD_MFGPT_RES0 (MSR_SB_MDD + 0x2A) |
| 148 | #define MDD_MFGPT_RES1 (MSR_SB_MDD + 0x2B) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 149 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 150 | #define MDD_FLOP_S3F2 (MSR_SB_MDD + 0x30) |
| 151 | #define MDD_FLOP_S3F7 (MSR_SB_MDD + 0x31) |
| 152 | #define MDD_FLOP_S372 (MSR_SB_MDD + 0x32) |
| 153 | #define MDD_FLOP_S377 (MSR_SB_MDD + 0x33) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 154 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 155 | #define MDD_PIC_S (MSR_SB_MDD + 0x34) |
| 156 | #define MDD_PIT_S (MSR_SB_MDD + 0x36) |
| 157 | #define MDD_PIT_CNTRL (MSR_SB_MDD + 0x37) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 158 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 159 | #define MDD_UART1_MOD (MSR_SB_MDD + 0x38) |
| 160 | #define MDD_UART1_DON (MSR_SB_MDD + 0x39) |
| 161 | #define MDD_UART1_CONF (MSR_SB_MDD + 0x3A) |
| 162 | #define MDD_UART2_MOD (MSR_SB_MDD + 0x3C) |
| 163 | #define MDD_UART2_DON (MSR_SB_MDD + 0x3D) |
| 164 | #define MDD_UART2_CONF (MSR_SB_MDD + 0x3E) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 165 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 166 | #define MDD_DMA_MAP (MSR_SB_MDD + 0x40) |
| 167 | #define MDD_DMA_SHAD1 (MSR_SB_MDD + 0x41) |
| 168 | #define MDD_DMA_SHAD2 (MSR_SB_MDD + 0x42) |
| 169 | #define MDD_DMA_SHAD3 (MSR_SB_MDD + 0x43) |
| 170 | #define MDD_DMA_SHAD4 (MSR_SB_MDD + 0x44) |
| 171 | #define MDD_DMA_SHAD5 (MSR_SB_MDD + 0x45) |
| 172 | #define MDD_DMA_SHAD6 (MSR_SB_MDD + 0x46) |
| 173 | #define MDD_DMA_SHAD7 (MSR_SB_MDD + 0x47) |
| 174 | #define MDD_DMA_SHAD8 (MSR_SB_MDD + 0x48) |
| 175 | #define MDD_DMA_SHAD9 (MSR_SB_MDD + 0x49) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 176 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 177 | #define MDD_LPC_EADDR (MSR_SB_MDD + 0x4C) |
| 178 | #define MDD_LPC_ESTAT (MSR_SB_MDD + 0x4D) |
| 179 | #define MDD_LPC_SIRQ (MSR_SB_MDD + 0x4E) |
| 180 | #define MDD_LPC_RES (MSR_SB_MDD + 0x4F) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 181 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 182 | #define MDD_PML_TMR (MSR_SB_MDD + 0x50) |
| 183 | #define MDD_RTC_RAM_LO_CK (MSR_SB_MDD + 0x54) |
| 184 | #define MDD_RTC_DOMA_IND (MSR_SB_MDD + 0x55) |
| 185 | #define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x56) |
| 186 | #define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x57) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 187 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 188 | /* LBUS Device Equates - */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 189 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 190 | /* SMBus */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 191 | #define SMB_SDA 0x00 |
| 192 | #define SMB_STS 0x01 |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 193 | #define SMB_STS_SLVSTP (0x01 << 7) |
| 194 | #define SMB_STS_SDAST (0x01 << 6) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 195 | #define SMB_STS_BER (0x01 << 5) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 196 | #define SMB_STS_NEGACK (0x01 << 4) |
| 197 | #define SMB_STS_STASTR (0x01 << 3) |
| 198 | #define SMB_STS_NMATCH (0x01 << 2) |
| 199 | #define SMB_STS_MASTER (0x01 << 1) |
| 200 | #define SMB_STS_XMIT (0x01 << 0) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 201 | |
| 202 | #define SMB_CTRL_STS 0x02 |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 203 | #define SMB_CSTS_TGSCL (0x01 << 5) |
| 204 | #define SMB_CSTS_TSDA (0x01 << 4) |
| 205 | #define SMB_CSTS_GCMTCH (0x01 << 3) |
| 206 | #define SMB_CSTS_MATCH (0x01 << 2) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 207 | #define SMB_CSTS_BB (0x01 << 1) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 208 | #define SMB_CSTS_BUSY (0x01 << 0) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 209 | |
| 210 | #define SMB_CTRL1 0x03 |
| 211 | #define SMB_CTRL1_STASTRE (0x01 << 7) |
| 212 | #define SMB_CTRL1_NMINTE (0x01 << 6) |
| 213 | #define SMB_CTRL1_GCMEN (0x01 << 5) |
| 214 | #define SMB_CTRL1_ACK (0x01 << 4) |
| 215 | #define SMB_CTRL1_RSVD (0x01 << 3) |
| 216 | #define SMB_CTRL1_INTEN (0x01 << 2) |
| 217 | #define SMB_CTRL1_STOP (0x01 << 1) |
| 218 | #define SMB_CTRL1_START (0x01 << 0) |
| 219 | |
| 220 | #define SMB_ADD 0x04 |
| 221 | #define SMB_ADD_SAEN (0x01 << 7) |
| 222 | |
| 223 | #define SMB_CTRL2 0x05 |
| 224 | #define SMB_CTRL2_ENABLE (0x01 << 0) |
| 225 | |
| 226 | #define SMB_CTRL3 0x06 |
| 227 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 228 | /* GPIO */ |
| 229 | #define GPIOL_0_SET (1 << 0) |
| 230 | #define GPIOL_1_SET (1 << 1) |
| 231 | #define GPIOL_2_SET (1 << 2) |
| 232 | #define GPIOL_3_SET (1 << 3) |
| 233 | #define GPIOL_4_SET (1 << 4) |
| 234 | #define GPIOL_5_SET (1 << 5) |
| 235 | #define GPIOL_6_SET (1 << 6) |
| 236 | #define GPIOL_7_SET (1 << 7) |
| 237 | #define GPIOL_8_SET (1 << 8) |
| 238 | #define GPIOL_9_SET (1 << 9) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 239 | #define GPIOL_10_SET (1 << 10) |
| 240 | #define GPIOL_11_SET (1 << 11) |
| 241 | #define GPIOL_12_SET (1 << 12) |
| 242 | #define GPIOL_13_SET (1 << 13) |
| 243 | #define GPIOL_14_SET (1 << 14) |
| 244 | #define GPIOL_15_SET (1 << 15) |
| 245 | |
| 246 | #define GPIOL_0_CLEAR (1 << 16) |
| 247 | #define GPIOL_1_CLEAR (1 << 17) |
| 248 | #define GPIOL_2_CLEAR (1 << 18) |
| 249 | #define GPIOL_3_CLEAR (1 << 19) |
| 250 | #define GPIOL_4_CLEAR (1 << 20) |
| 251 | #define GPIOL_5_CLEAR (1 << 21) |
| 252 | #define GPIOL_6_CLEAR (1 << 22) |
| 253 | #define GPIOL_7_CLEAR (1 << 23) |
| 254 | #define GPIOL_8_CLEAR (1 << 24) |
| 255 | #define GPIOL_9_CLEAR (1 << 25) |
| 256 | #define GPIOL_10_CLEAR (1 << 26) |
| 257 | #define GPIOL_11_CLEAR (1 << 27) |
| 258 | #define GPIOL_12_CLEAR (1 << 28) |
| 259 | #define GPIOL_13_CLEAR (1 << 29) |
| 260 | #define GPIOL_14_CLEAR (1 << 30) |
| 261 | #define GPIOL_15_CLEAR (1 << 31) |
| 262 | |
| 263 | #define GPIOH_16_SET (1 << 0) |
| 264 | #define GPIOH_17_SET (1 << 1) |
| 265 | #define GPIOH_18_SET (1 << 2) |
| 266 | #define GPIOH_19_SET (1 << 3) |
| 267 | #define GPIOH_20_SET (1 << 4) |
| 268 | #define GPIOH_21_SET (1 << 5) |
| 269 | #define GPIOH_22_SET (1 << 6) |
| 270 | #define GPIOH_23_SET (1 << 7) |
| 271 | #define GPIOH_24_SET (1 << 8) |
| 272 | #define GPIOH_25_SET (1 << 9) |
| 273 | #define GPIOH_26_SET (1 << 10) |
| 274 | #define GPIOH_27_SET (1 << 11) |
| 275 | #define GPIOH_28_SET (1 << 12) |
| 276 | #define GPIOH_29_SET (1 << 13) |
| 277 | #define GPIOH_30_SET (1 << 14) |
| 278 | #define GPIOH_31_SET (1 << 15) |
| 279 | |
| 280 | #define GPIOH_16_CLEAR (1 << 16) |
| 281 | #define GPIOH_17_CLEAR (1 << 17) |
| 282 | #define GPIOH_18_CLEAR (1 << 18) |
| 283 | #define GPIOH_19_CLEAR (1 << 19) |
| 284 | #define GPIOH_20_CLEAR (1 << 20) |
| 285 | #define GPIOH_21_CLEAR (1 << 21) |
| 286 | #define GPIOH_22_CLEAR (1 << 22) |
| 287 | #define GPIOH_23_CLEAR (1 << 23) |
| 288 | #define GPIOH_24_CLEAR (1 << 24) |
| 289 | #define GPIOH_25_CLEAR (1 << 25) |
| 290 | #define GPIOH_26_CLEAR (1 << 26) |
| 291 | #define GPIOH_27_CLEAR (1 << 27) |
| 292 | #define GPIOH_28_CLEAR (1 << 28) |
| 293 | #define GPIOH_29_CLEAR (1 << 29) |
| 294 | #define GPIOH_30_CLEAR (1 << 30) |
| 295 | #define GPIOH_31_CLEAR (1 << 31) |
| 296 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 297 | /* GPIO LOW Bank Bit Registers */ |
| 298 | #define GPIOL_OUTPUT_VALUE (0x00) |
| 299 | #define GPIOL_OUTPUT_ENABLE (0x04) |
| 300 | #define GPIOL_OUT_OPENDRAIN (0x08) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 301 | #define GPIOL_OUTPUT_INVERT_ENABLE (0x0C) |
| 302 | #define GPIOL_OUT_AUX1_SELECT (0x10) |
| 303 | #define GPIOL_OUT_AUX2_SELECT (0x14) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 304 | #define GPIOL_PULLUP_ENABLE (0x18) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 305 | #define GPIOL_PULLDOWN_ENABLE (0x1C) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 306 | #define GPIOL_INPUT_ENABLE (0x20) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 307 | #define GPIOL_INPUT_INVERT_ENABLE (0x24) |
| 308 | #define GPIOL_IN_FILTER_ENABLE (0x28) |
| 309 | #define GPIOL_IN_EVENTCOUNT_ENABLE (0x2C) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 310 | #define GPIOL_READ_BACK (0x30) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 311 | #define GPIOL_IN_AUX1_SELECT (0x34) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 312 | #define GPIOL_EVENTS_ENABLE (0x38) |
| 313 | #define GPIOL_LOCK_ENABLE (0x3C) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 314 | #define GPIOL_IN_POSEDGE_ENABLE (0x40) |
| 315 | #define GPIOL_IN_NEGEDGE_ENABLE (0x44) |
| 316 | #define GPIOL_IN_POSEDGE_STATUS (0x48) |
| 317 | #define GPIOL_IN_NEGEDGE_STATUS (0x4C) |
| 318 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 319 | /* GPIO High Bank Bit Registers */ |
| 320 | #define GPIOH_OUTPUT_VALUE (0x80) |
| 321 | #define GPIOH_OUTPUT_ENABLE (0x84) |
| 322 | #define GPIOH_OUT_OPENDRAIN (0x88) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 323 | #define GPIOH_OUTPUT_INVERT_ENABLE (0x8C) |
| 324 | #define GPIOH_OUT_AUX1_SELECT (0x90) |
| 325 | #define GPIOH_OUT_AUX2_SELECT (0x94) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 326 | #define GPIOH_PULLUP_ENABLE (0x98) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 327 | #define GPIOH_PULLDOWN_ENABLE (0x9C) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 328 | #define GPIOH_INPUT_ENABLE (0xA0) |
| 329 | #define GPIOH_INPUT_INVERT_ENABLE (0xA4) |
| 330 | #define GPIOH_IN_FILTER_ENABLE (0xA8) |
| 331 | #define GPIOH_IN_EVENTCOUNT_ENABLE (0xAC) |
| 332 | #define GPIOH_READ_BACK (0xB0) |
| 333 | #define GPIOH_IN_AUX1_SELECT (0xB4) |
| 334 | #define GPIOH_EVENTS_ENABLE (0xB8) |
| 335 | #define GPIOH_LOCK_ENABLE (0xBC) |
| 336 | #define GPIOH_IN_POSEDGE_ENABLE (0xC0) |
| 337 | #define GPIOH_IN_NEGEDGE_ENABLE (0xC4) |
| 338 | #define GPIOH_IN_POSEDGE_STATUS (0xC8) |
| 339 | #define GPIOH_IN_NEGEDGE_STATUS (0xCC) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 340 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 341 | /* Input Conditioning Function Registers */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 342 | #define GPIO_00_FILTER_AMOUNT (0x50) |
| 343 | #define GPIO_00_FILTER_COUNT (0x52) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 344 | #define GPIO_00_EVENT_COUNT (0x54) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 345 | #define GPIO_00_EVENTCOMPARE_VALUE (0x56) |
| 346 | #define GPIO_01_FILTER_AMOUNT (0x58) |
| 347 | #define GPIO_01_FILTER_COUNT (0x5A) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 348 | #define GPIO_01_EVENT_COUNT (0x5C) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 349 | #define GPIO_01_EVENTCOMPARE_VALUE (0x5E) |
| 350 | #define GPIO_02_FILTER_AMOUNT (0x60) |
| 351 | #define GPIO_02_FILTER_COUNT (0x62) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 352 | #define GPIO_02_EVENT_COUNT (0x64) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 353 | #define GPIO_02_EVENTCOMPARE_VALUE (0x66) |
| 354 | #define GPIO_03_FILTER_AMOUNT (0x68) |
| 355 | #define GPIO_03_FILTER_COUNT (0x6A) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 356 | #define GPIO_03_EVENT_COUNT (0x6C) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 357 | #define GPIO_03_EVENTCOMPARE_VALUE (0x6E) |
| 358 | #define GPIO_04_FILTER_AMOUNT (0x70) |
| 359 | #define GPIO_04_FILTER_COUNT (0x72) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 360 | #define GPIO_04_EVENT_COUNT (0x74) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 361 | #define GPIO_04_EVENTCOMPARE_VALUE (0x76) |
| 362 | #define GPIO_05_FILTER_AMOUNT (0x78) |
| 363 | #define GPIO_05_FILTER_COUNT (0x7A) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 364 | #define GPIO_05_EVENT_COUNT (0x7C) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 365 | #define GPIO_05_EVENTCOMPARE_VALUE (0x7E) |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 366 | #define GPIO_06_FILTER_AMOUNT (0xD0) |
| 367 | #define GPIO_06_FILTER_COUNT (0xD2) |
| 368 | #define GPIO_06_EVENT_COUNT (0xD4) |
| 369 | #define GPIO_06_EVENTCOMPARE_VALUE (0xD6) |
| 370 | #define GPIO_07_FILTER_AMOUNT (0xD8) |
| 371 | #define GPIO_07_FILTER_COUNT (0xDA) |
| 372 | #define GPIO_07_EVENT_COUNT (0xDC) |
| 373 | #define GPIO_07_EVENTCOMPARE_VALUE (0xDE) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 374 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 375 | /* R/W GPIO Interrupt &PME Mapper Registers */ |
| 376 | #define GPIO_MAPPER_X (0xE0) |
| 377 | #define GPIO_MAPPER_Y (0xE4) |
| 378 | #define GPIO_MAPPER_Z (0xE8) |
| 379 | #define GPIO_MAPPER_W (0xEC) |
| 380 | #define GPIO_FE_SELECT_0 (0xF0) |
| 381 | #define GPIO_FE_SELECT_1 (0xF1) |
| 382 | #define GPIO_FE_SELECT_2 (0xF2) |
| 383 | #define GPIO_FE_SELECT_3 (0xF3) |
| 384 | #define GPIO_FE_SELECT_4 (0xF4) |
| 385 | #define GPIO_FE_SELECT_5 (0xF5) |
| 386 | #define GPIO_FE_SELECT_6 (0xF6) |
| 387 | #define GPIO_FE_SELECT_7 (0xF7) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 388 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 389 | /* Event Counter Decrement Registers */ |
| 390 | #define GPIOL_IN_EVENT_DECREMENT (0xF8) |
| 391 | #define GPIOH_IN_EVENT_DECREMENT (0xFC) |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 392 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 393 | /* PMC register */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 394 | #define PM_SSD (0x00) |
| 395 | #define PM_SCXA (0x04) |
| 396 | #define PM_SCYA (0x08) |
| 397 | #define PM_SODA (0x0C) |
| 398 | #define PM_SCLK (0x10) |
| 399 | #define PM_SED (0x14) |
| 400 | #define PM_SCXD (0x18) |
| 401 | #define PM_SCYD (0x1C) |
| 402 | #define PM_SIDD (0x20) |
| 403 | #define PM_WKD (0x30) |
| 404 | #define PM_WKXD (0x34) |
| 405 | #define PM_RD (0x38) |
| 406 | #define PM_WKXA (0x3C) |
| 407 | #define PM_FSD (0x40) |
| 408 | #define PM_TSD (0x44) |
| 409 | #define PM_PSD (0x48) |
| 410 | #define PM_NWKD (0x4C) |
| 411 | #define PM_AWKD (0x50) |
| 412 | #define PM_SSC (0x54) |
| 413 | |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 414 | /* FLASH device macros */ |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 415 | #define FLASH_TYPE_NONE 0 /* No flash device installed */ |
| 416 | #define FLASH_TYPE_NAND 1 /* NAND device */ |
| 417 | #define FLASH_TYPE_NOR 2 /* NOR device */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 418 | |
Nils Jacobs | ef15ff4 | 2010-12-29 20:31:31 +0000 | [diff] [blame] | 419 | #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ |
| 420 | #define FLASH_IF_IO 2 /* I/O interface for Flash device */ |
Marc Jones | a67d4fd | 2007-05-04 19:05:36 +0000 | [diff] [blame] | 421 | |
| 422 | /* Flash Memory Mask values */ |
| 423 | #define FLASH_MEM_DEFAULT 0x00000000 |
| 424 | #define FLASH_MEM_4K 0xFFFFF000 |
| 425 | #define FLASH_MEM_8K 0xFFFFE000 |
| 426 | #define FLASH_MEM_16K 0xFFFFC000 |
| 427 | #define FLASH_MEM_128K 0xFFFE0000 |
| 428 | #define FLASH_MEM_512K 0xFFFC0000 |
| 429 | #define FLASH_MEM_4M 0xFFC00000 |
| 430 | #define FLASH_MEM_8M 0xFF800000 |
| 431 | #define FLASH_MEM_16M 0xFF000000 |
| 432 | |
| 433 | /* Flash IO Mask values */ |
| 434 | #define FLASH_IO_DEFAULT 0x00000000 |
| 435 | #define FLASH_IO_16B 0x0000FFF0 |
| 436 | #define FLASH_IO_32B 0x0000FFE0 |
| 437 | #define FLASH_IO_64B 0x0000FFC0 |
| 438 | #define FLASH_IO_128B 0x0000FF80 |
| 439 | #define FLASH_IO_256B 0x0000FF00 |
| 440 | |
Stefan Reinauer | 3f5f6d8 | 2013-05-07 20:35:29 +0200 | [diff] [blame] | 441 | #if !defined(__ASSEMBLER__) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 442 | #if defined(__PRE_RAM__) |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 443 | void cs5536_setup_onchipuart(int uart); |
| 444 | void cs5536_disable_internal_uart(void); |
| 445 | #else |
| 446 | void chipsetinit(void); |
| 447 | #endif |
| 448 | #endif |
| 449 | |
Edward O'Callaghan | 309a7ff | 2014-08-09 21:38:56 +1000 | [diff] [blame] | 450 | #endif /* _CS5536_H */ |