Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Early initialization code for riscv |
| 3 | * |
| 4 | * Copyright 2015 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 14 | * GNU General Public License for more details. |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/exception.h> |
| 19 | #include <spike_util.h> |
| 20 | #include <string.h> |
| 21 | |
| 22 | #define HART_ID 0 |
| 23 | #define CONSOLE_PUT 1 |
| 24 | #define SEND_DEVICE_REQUEST 2 |
| 25 | #define RECEIVE_DEVICE_RESPONSE 3 |
| 26 | #define SEND_IPI 4 |
| 27 | #define CLEAR_IPI 5 |
| 28 | #define SHUTDOWN 6 |
| 29 | #define SET_TIMER 7 |
| 30 | #define QUERY_MEMORY 8 |
| 31 | |
| 32 | int loopBreak2 = 1; |
| 33 | |
| 34 | void handle_supervisor_call(trapframe *tf) { |
| 35 | uintptr_t call = tf->gpr[17]; |
| 36 | uintptr_t arg0 = tf->gpr[10]; |
| 37 | uintptr_t arg1 = tf->gpr[11]; |
| 38 | uintptr_t returnValue; |
| 39 | switch(call) { |
| 40 | case HART_ID: |
| 41 | printk(BIOS_DEBUG, "Getting hart id...\n"); |
| 42 | returnValue = mcall_hart_id(); |
| 43 | break; |
| 44 | case CONSOLE_PUT: |
| 45 | returnValue = mcall_console_putchar(arg0); |
| 46 | break; |
| 47 | case SEND_DEVICE_REQUEST: |
| 48 | printk(BIOS_DEBUG, "Sending device request...\n"); |
| 49 | returnValue = mcall_dev_req((sbi_device_message*) arg0); |
| 50 | break; |
| 51 | case RECEIVE_DEVICE_RESPONSE: |
| 52 | printk(BIOS_DEBUG, "Getting device response...\n"); |
| 53 | returnValue = mcall_dev_resp(); |
| 54 | break; |
| 55 | case SEND_IPI: |
| 56 | printk(BIOS_DEBUG, "Sending IPI...\n"); |
| 57 | returnValue = mcall_send_ipi(arg0); |
| 58 | break; |
| 59 | case CLEAR_IPI: |
| 60 | printk(BIOS_DEBUG, "Clearing IPI...\n"); |
| 61 | returnValue = mcall_clear_ipi(); |
| 62 | break; |
| 63 | case SHUTDOWN: |
| 64 | printk(BIOS_DEBUG, "Shutting down...\n"); |
| 65 | returnValue = mcall_shutdown(); |
| 66 | break; |
| 67 | case SET_TIMER: |
| 68 | printk(BIOS_DEBUG, "Setting timer...\n"); |
| 69 | returnValue = mcall_set_timer(arg0); |
| 70 | break; |
| 71 | case QUERY_MEMORY: |
| 72 | printk(BIOS_DEBUG, "Querying memory, CPU #%lld...\n", arg0); |
| 73 | returnValue = mcall_query_memory(arg0, (memory_block_info*) arg1); |
| 74 | break; |
| 75 | default: |
| 76 | printk(BIOS_DEBUG, "ERROR! Unrecognized system call\n"); |
| 77 | returnValue = 0; |
| 78 | break; // note: system call we do not know how to handle |
| 79 | } |
| 80 | tf->gpr[10] = returnValue; |
| 81 | write_csr(mepc, read_csr(mepc) + 4); |
| 82 | asm volatile("j supervisor_call_return"); |
| 83 | } |
| 84 | |
| 85 | void trap_handler(trapframe *tf) { |
| 86 | write_csr(mscratch, tf); |
| 87 | int cause = 0; |
| 88 | void* epc = 0; |
| 89 | void* badAddr = 0; |
| 90 | |
| 91 | // extract cause |
| 92 | asm("csrr t0, mcause"); |
| 93 | asm("move %0, t0" : "=r"(cause)); |
| 94 | |
| 95 | // extract faulting Instruction pc |
| 96 | epc = (void*) tf->epc; |
| 97 | |
| 98 | // extract bad address |
| 99 | asm("csrr t0, mbadaddr"); |
| 100 | asm("move %0, t0" : "=r"(badAddr)); |
| 101 | |
| 102 | switch(cause) { |
| 103 | case 0: |
| 104 | printk(BIOS_DEBUG, "Trap: Instruction address misaligned\n"); |
| 105 | break; |
| 106 | case 1: |
| 107 | printk(BIOS_DEBUG, "Trap: Instruction access fault\n"); |
| 108 | printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); |
| 109 | printk(BIOS_DEBUG, "Address: %p\n", badAddr); |
| 110 | break; |
| 111 | case 2: |
| 112 | printk(BIOS_DEBUG, "Trap: Illegal instruction\n"); |
| 113 | printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); |
| 114 | printk(BIOS_DEBUG, "Address: %p\n", badAddr); |
| 115 | break; |
| 116 | case 3: |
| 117 | printk(BIOS_DEBUG, "Trap: Breakpoint\n"); |
| 118 | break; |
| 119 | case 4: |
| 120 | printk(BIOS_DEBUG, "Trap: Load address misaligned\n"); |
| 121 | //handleMisalignedLoad(tf); |
| 122 | break; |
| 123 | case 5: |
| 124 | printk(BIOS_DEBUG, "Trap: Load access fault\n"); |
| 125 | break; |
| 126 | case 6: |
| 127 | printk(BIOS_DEBUG, "Trap: Store address misaligned\n"); |
| 128 | printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); |
| 129 | printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); |
| 130 | handle_misaligned_store(tf); |
| 131 | break; |
| 132 | case 7: |
| 133 | printk(BIOS_DEBUG, "Trap: Store access fault\n"); |
| 134 | printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); |
| 135 | printk(BIOS_DEBUG, "Store Address: %p\n", badAddr); |
| 136 | break; |
| 137 | case 8: |
| 138 | printk(BIOS_DEBUG, "Trap: Environment call from U-mode\n"); |
| 139 | break; |
| 140 | case 9: |
| 141 | // Don't print so we make console putchar calls look the way they should |
| 142 | // printk(BIOS_DEBUG, "Trap: Environment call from S-mode\n"); |
| 143 | handle_supervisor_call(tf); |
| 144 | break; |
| 145 | case 10: |
| 146 | printk(BIOS_DEBUG, "Trap: Environment call from H-mode\n"); |
| 147 | break; |
| 148 | case 11: |
| 149 | printk(BIOS_DEBUG, "Trap: Environment call from M-mode\n"); |
| 150 | break; |
| 151 | default: |
| 152 | printk(BIOS_DEBUG, "Trap: Unknown cause\n"); |
| 153 | break; |
| 154 | } |
| 155 | printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); |
| 156 | printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); |
| 157 | printk(BIOS_DEBUG, "looping...\n"); |
| 158 | while(1); |
| 159 | } |
| 160 | |
Thaminda Edirisooriya | d9653e1 | 2015-09-10 10:55:17 -0700 | [diff] [blame] | 161 | void handleMisalignedLoad(trapframe *tf) { |
| 162 | printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); |
| 163 | printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); |
| 164 | insn_t faultingInstruction = 0; |
| 165 | uintptr_t faultingInstructionAddr = tf->epc; |
| 166 | asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr)); |
| 167 | asm("lw t0, 0(t0)"); |
| 168 | asm("move %0, t0" : "=r"(faultingInstruction)); |
| 169 | printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); |
| 170 | insn_t widthMask = 0x7000; |
| 171 | insn_t memWidth = (faultingInstruction & widthMask) >> 12; |
| 172 | insn_t destMask = 0xF80; |
| 173 | insn_t destRegister = (faultingInstruction & destMask) >> 7; |
| 174 | printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth); |
| 175 | if (memWidth == 3) { |
| 176 | // load double, handle the issue |
| 177 | void* badAddress = (void*) tf->badvaddr; |
| 178 | memcpy(&(tf->gpr[destRegister]), badAddress, 8); |
| 179 | } else { |
| 180 | // panic, this should not have happened |
| 181 | printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n"); |
| 182 | while(1); |
| 183 | } |
| 184 | |
| 185 | // return to where we came from |
| 186 | write_csr(mepc, read_csr(mepc) + 4); |
| 187 | asm volatile("j machine_call_return"); |
| 188 | } |
| 189 | |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 190 | void handle_misaligned_store(trapframe *tf) { |
| 191 | printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); |
| 192 | printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); |
| 193 | insn_t faultingInstruction = 0; |
| 194 | uintptr_t faultingInstructionAddr = tf->epc; |
| 195 | asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr)); |
| 196 | asm("lw t0, 0(t0)"); |
| 197 | asm("move %0, t0" : "=r"(faultingInstruction)); |
| 198 | printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); |
| 199 | insn_t widthMask = 0x7000; |
| 200 | insn_t memWidth = (faultingInstruction & widthMask) >> 12; |
| 201 | insn_t srcMask = 0x1F00000; |
| 202 | insn_t srcRegister = (faultingInstruction & srcMask) >> 20; |
| 203 | printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth); |
| 204 | if (memWidth == 3) { |
| 205 | // store double, handle the issue |
| 206 | void* badAddress = (void*) tf->badvaddr; |
| 207 | long valueToStore = tf->gpr[srcRegister]; |
| 208 | memcpy(badAddress, &valueToStore, 8); |
| 209 | } else { |
| 210 | // panic, this should not have happened |
| 211 | printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n"); |
| 212 | while(1); |
| 213 | } |
| 214 | |
| 215 | // return to where we came from |
| 216 | write_csr(mepc, read_csr(mepc) + 4); |
| 217 | asm volatile("j machine_call_return"); |
| 218 | } |