Angel Pons | d28443e | 2020-04-05 13:22:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 3 | |
| 4 | #include <arch/acpi.h> |
| 5 | #include <arch/io.h> |
| 6 | #include <console/console.h> |
| 7 | #include <cpu/x86/smm.h> |
| 8 | #include <southbridge/intel/lynxpoint/nvs.h> |
| 9 | #include <southbridge/intel/lynxpoint/pch.h> |
| 10 | #include <southbridge/intel/common/gpio.h> |
| 11 | #include <southbridge/intel/lynxpoint/me.h> |
| 12 | #include <northbridge/intel/haswell/haswell.h> |
| 13 | #include <cpu/intel/haswell/haswell.h> |
| 14 | #include <elog.h> |
| 15 | |
| 16 | /* Include EC functions */ |
| 17 | #include <ec/google/chromeec/ec.h> |
| 18 | #include "ec.h" |
| 19 | |
| 20 | /* Codec enable: GPIO45 */ |
| 21 | #define GPIO_PP3300_CODEC_EN 45 |
| 22 | /* GPIO46 controls the WLAN_DISABLE_L signal. */ |
| 23 | #define GPIO_WLAN_DISABLE_L 46 |
| 24 | #define GPIO_LTE_DISABLE_L 59 |
| 25 | |
| 26 | static u8 mainboard_smi_ec(void) |
| 27 | { |
| 28 | u8 cmd = google_chromeec_get_event(); |
| 29 | u32 pm1_cnt; |
| 30 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 31 | /* Log this event */ |
| 32 | if (cmd) |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 33 | elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 34 | |
| 35 | switch (cmd) { |
| 36 | case EC_HOST_EVENT_LID_CLOSED: |
| 37 | printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); |
| 38 | |
| 39 | /* Go to S5 */ |
| 40 | pm1_cnt = inl(get_pmbase() + PM1_CNT); |
| 41 | pm1_cnt |= (0xf << 10); |
| 42 | outl(pm1_cnt, get_pmbase() + PM1_CNT); |
| 43 | break; |
| 44 | } |
| 45 | |
| 46 | return cmd; |
| 47 | } |
| 48 | |
| 49 | /* gpi_sts is GPIO 47:32 */ |
| 50 | void mainboard_smi_gpi(u32 gpi_sts) |
| 51 | { |
| 52 | if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { |
| 53 | /* Process all pending events */ |
| 54 | while (mainboard_smi_ec() != 0); |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | void mainboard_smi_sleep(u8 slp_typ) |
| 59 | { |
| 60 | /* Disable USB charging if required */ |
| 61 | switch (slp_typ) { |
| 62 | case ACPI_S3: |
| 63 | if (smm_get_gnvs()->s3u0 == 0) |
| 64 | google_chromeec_set_usb_charge_mode( |
| 65 | 0, USB_CHARGE_MODE_DISABLED); |
| 66 | if (smm_get_gnvs()->s3u1 == 0) |
| 67 | google_chromeec_set_usb_charge_mode( |
| 68 | 1, USB_CHARGE_MODE_DISABLED); |
| 69 | |
| 70 | /* Prevent leak from standby rail to WLAN rail in S3. */ |
| 71 | set_gpio(GPIO_WLAN_DISABLE_L, 0); |
| 72 | set_gpio(GPIO_PP3300_CODEC_EN, 0); |
| 73 | /* Disable LTE */ |
| 74 | set_gpio(GPIO_LTE_DISABLE_L, 0); |
| 75 | |
| 76 | /* Enable wake events */ |
| 77 | google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); |
| 78 | break; |
| 79 | case ACPI_S4: |
| 80 | case ACPI_S5: |
| 81 | if (smm_get_gnvs()->s5u0 == 0) |
| 82 | google_chromeec_set_usb_charge_mode( |
| 83 | 0, USB_CHARGE_MODE_DISABLED); |
| 84 | if (smm_get_gnvs()->s5u1 == 0) |
| 85 | google_chromeec_set_usb_charge_mode( |
| 86 | 1, USB_CHARGE_MODE_DISABLED); |
| 87 | |
| 88 | /* Prevent leak from standby rail to WLAN rail in S5. */ |
| 89 | set_gpio(GPIO_WLAN_DISABLE_L, 0); |
| 90 | set_gpio(GPIO_PP3300_CODEC_EN, 0); |
| 91 | /* Disable LTE */ |
| 92 | set_gpio(GPIO_LTE_DISABLE_L, 0); |
| 93 | |
| 94 | /* Enable wake events */ |
| 95 | google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); |
| 96 | break; |
| 97 | } |
| 98 | |
| 99 | /* Disable SCI and SMI events */ |
| 100 | google_chromeec_set_smi_mask(0); |
| 101 | google_chromeec_set_sci_mask(0); |
| 102 | |
| 103 | /* Clear pending events that may trigger immediate wake */ |
| 104 | while (google_chromeec_get_event() != 0); |
| 105 | } |
| 106 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 107 | int mainboard_smi_apmc(u8 apmc) |
| 108 | { |
| 109 | switch (apmc) { |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 110 | case APM_CNT_ACPI_ENABLE: |
| 111 | google_chromeec_set_smi_mask(0); |
| 112 | /* Clear all pending events */ |
| 113 | while (google_chromeec_get_event() != 0); |
| 114 | google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); |
| 115 | break; |
| 116 | case APM_CNT_ACPI_DISABLE: |
| 117 | google_chromeec_set_sci_mask(0); |
| 118 | /* Clear all pending events */ |
| 119 | while (google_chromeec_get_event() != 0); |
| 120 | google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); |
| 121 | break; |
| 122 | } |
| 123 | return 0; |
| 124 | } |