Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <arch/hlt.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/romcc_io.h> |
| 25 | #include <console/console.h> |
| 26 | #include <delay.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <string.h> |
| 29 | #include "me.h" |
| 30 | #include "pch.h" |
| 31 | |
| 32 | static const char *me_ack_values[] = { |
| 33 | [ME_HFS_ACK_NO_DID] = "No DID Ack received", |
| 34 | [ME_HFS_ACK_RESET] = "Non-power cycle reset", |
| 35 | [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", |
| 36 | [ME_HFS_ACK_S3] = "Go to S3", |
| 37 | [ME_HFS_ACK_S4] = "Go to S4", |
| 38 | [ME_HFS_ACK_S5] = "Go to S5", |
| 39 | [ME_HFS_ACK_GBL_RESET] = "Global Reset", |
| 40 | [ME_HFS_ACK_CONTINUE] = "Continue to boot" |
| 41 | }; |
| 42 | |
| 43 | static inline void pci_read_dword_ptr(void *ptr, int offset) |
| 44 | { |
| 45 | u32 dword = pci_read_config32(PCH_ME_DEV, offset); |
| 46 | memcpy(ptr, &dword, sizeof(dword)); |
| 47 | } |
| 48 | |
| 49 | static inline void pci_write_dword_ptr(void *ptr, int offset) |
| 50 | { |
| 51 | u32 dword = 0; |
| 52 | memcpy(&dword, ptr, sizeof(dword)); |
| 53 | pci_write_config32(PCH_ME_DEV, offset, dword); |
| 54 | } |
| 55 | |
| 56 | void intel_early_me_status(void) |
| 57 | { |
| 58 | struct me_hfs hfs; |
| 59 | struct me_gmes gmes; |
| 60 | |
| 61 | pci_read_dword_ptr(&hfs, PCI_ME_HFS); |
| 62 | pci_read_dword_ptr(&gmes, PCI_ME_GMES); |
| 63 | |
| 64 | intel_me_status(&hfs, &gmes); |
| 65 | } |
| 66 | |
| 67 | int intel_early_me_init(void) |
| 68 | { |
| 69 | int count; |
| 70 | struct me_uma uma; |
| 71 | struct me_hfs hfs; |
| 72 | |
| 73 | printk(BIOS_INFO, "Intel ME early init\n"); |
| 74 | |
| 75 | /* Wait for ME UMA SIZE VALID bit to be set */ |
| 76 | for (count = ME_RETRY; count > 0; --count) { |
| 77 | pci_read_dword_ptr(&uma, PCI_ME_UMA); |
| 78 | if (uma.valid) |
| 79 | break; |
| 80 | udelay(ME_DELAY); |
| 81 | } |
| 82 | if (!count) { |
| 83 | printk(BIOS_ERR, "ERROR: ME is not ready!\n"); |
| 84 | return -1; |
| 85 | } |
| 86 | |
| 87 | /* Check for valid firmware */ |
| 88 | pci_read_dword_ptr(&hfs, PCI_ME_HFS); |
| 89 | if (hfs.fpt_bad) { |
| 90 | printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); |
| 91 | return -1; |
| 92 | } |
| 93 | |
| 94 | printk(BIOS_INFO, "Intel ME firmware is ready\n"); |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | int intel_early_me_uma_size(void) |
| 99 | { |
| 100 | struct me_uma uma; |
| 101 | |
| 102 | pci_read_dword_ptr(&uma, PCI_ME_UMA); |
| 103 | if (uma.valid) { |
| 104 | printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); |
| 105 | return uma.size; |
| 106 | } |
| 107 | |
| 108 | printk(BIOS_DEBUG, "ME: Invalid UMA size\n"); |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | static inline void set_global_reset(int enable) |
| 113 | { |
| 114 | u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); |
| 115 | |
| 116 | /* Clear CF9 Without Resume Well Reset Enable */ |
| 117 | etr3 &= ~ETR3_CWORWRE; |
| 118 | |
| 119 | /* CF9GR indicates a Global Reset */ |
| 120 | if (enable) |
| 121 | etr3 |= ETR3_CF9GR; |
| 122 | else |
| 123 | etr3 &= ~ETR3_CF9GR; |
| 124 | |
| 125 | pci_write_config32(PCH_LPC_DEV, ETR3, etr3); |
| 126 | } |
| 127 | |
| 128 | int intel_early_me_init_done(u8 status) |
| 129 | { |
| 130 | u8 reset; |
| 131 | int count; |
| 132 | u32 mebase_l, mebase_h; |
| 133 | struct me_hfs hfs; |
| 134 | struct me_did did = { |
| 135 | .init_done = ME_INIT_DONE, |
| 136 | .status = status |
| 137 | }; |
| 138 | |
| 139 | /* MEBASE from MESEG_BASE[35:20] */ |
| 140 | mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L); |
| 141 | mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf; |
| 142 | did.uma_base = (mebase_l >> 20) | (mebase_h << 12); |
| 143 | |
| 144 | /* Send message to ME */ |
| 145 | printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " |
| 146 | "UMA base: 0x%04x\n", status, did.uma_base); |
| 147 | |
| 148 | pci_write_dword_ptr(&did, PCI_ME_H_GS); |
| 149 | |
| 150 | /* Must wait for ME acknowledgement */ |
| 151 | for (count = ME_RETRY; count > 0; --count) { |
| 152 | pci_read_dword_ptr(&hfs, PCI_ME_HFS); |
| 153 | if (hfs.bios_msg_ack) |
| 154 | break; |
| 155 | udelay(ME_DELAY); |
| 156 | } |
| 157 | if (!count) { |
| 158 | printk(BIOS_ERR, "ERROR: ME failed to respond\n"); |
| 159 | return -1; |
| 160 | } |
| 161 | |
| 162 | /* Return the requested BIOS action */ |
| 163 | printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", |
| 164 | me_ack_values[hfs.ack_data]); |
| 165 | |
| 166 | /* Check status after acknowledgement */ |
| 167 | intel_early_me_status(); |
| 168 | |
| 169 | reset = 0; |
| 170 | switch (hfs.ack_data) { |
| 171 | case ME_HFS_ACK_CONTINUE: |
| 172 | /* Continue to boot */ |
| 173 | return 0; |
| 174 | case ME_HFS_ACK_RESET: |
| 175 | /* Non-power cycle reset */ |
| 176 | set_global_reset(0); |
| 177 | reset = 0x06; |
| 178 | break; |
| 179 | case ME_HFS_ACK_PWR_CYCLE: |
| 180 | /* Power cycle reset */ |
| 181 | set_global_reset(0); |
| 182 | reset = 0x0e; |
| 183 | break; |
| 184 | case ME_HFS_ACK_GBL_RESET: |
| 185 | /* Global reset */ |
| 186 | set_global_reset(1); |
| 187 | reset = 0x0e; |
| 188 | break; |
| 189 | case ME_HFS_ACK_S3: |
| 190 | case ME_HFS_ACK_S4: |
| 191 | case ME_HFS_ACK_S5: |
| 192 | break; |
| 193 | } |
| 194 | |
| 195 | /* Perform the requested reset */ |
| 196 | if (reset) { |
| 197 | outb(reset, 0xcf9); |
| 198 | hlt(); |
| 199 | } |
| 200 | return -1; |
| 201 | } |