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review.coreboot.org / coreboot / 7687e7767f2d2321b57fa8eab68b7e954e57ad42 / . / src / vendorcode / amd / pi / 00730F01 / Include / PlatformMemoryConfiguration.h
blob: c79c0a52552810b52bd4b45d4ea69c64668f2383 [file] [log] [blame]
Martin Roth7687e772023-08-22 16:32:20 -0600[diff] [blame^]1/* SPDX-License-Identifier: BSD-3-Clause */
2
Marc Jones0b11bd02015-07-19 15:20:17 -0600[diff] [blame]3/* $NoKeywords:$ */
4/**
5 * @file
6 *
7 * AMD Platform Specific Memory Configuration
8 *
9 * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: OPTION
14 * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
15 *
16 */
17/*****************************************************************************
18 *
19 * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *
44 ***************************************************************************/
45
46#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
47#define _PLATFORM_MEMORY_CONFIGURATION_H_
48
49/*----------------------------------------------------------------------------------------
50 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
51 *----------------------------------------------------------------------------------------
52 */
53#ifndef PSO_ENTRY
54 #define PSO_ENTRY UINT8
55#endif
56
57/*----------------------------------------------------------------------------------------
58 * D E F I N I T I O N S A N D M A C R O S
59 *----------------------------------------------------------------------------------------
60 */
61/*----------------------------------------------------------------------------------------
62 * T Y P E D E F S, S T R U C T U R E S, E N U M S
63 *----------------------------------------------------------------------------------------
64 */
65/*----------------------------------------------------------------------------------------
66 * PLATFORM SPECIFIC MEMORY DEFINITIONS
67 *----------------------------------------------------------------------------------------
68 */
69///
70/// Memory Speed and DIMM Population Masks
71///
72///< DDR Speed Masks
73///< Specifies the DDR Speed on a memory channel
74///
75#define ANY_SPEED 0xFFFFFFFFul
76#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
77#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
78#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
79#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
80#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
81#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
82#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
83#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
84#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
85#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
86///
87///< DIMM POPULATION MASKS
88///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
89///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
90///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
91///
92#define ANY_ 0xFF ///< Any dimm configuration the current channel
93#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
94#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
95#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
96#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
97#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
98#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
99#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
100#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
101#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
102#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
103#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
104#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
105#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
106#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
107#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
108#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
109#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
110#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
111#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
112#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
113///
114///< CS POPULATION MASKS
115///< Specifies the CS Population on a channel (can be added together to specify configuration).
116///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
117///
118#define CS_ANY_ 0xFF ///< Any CS configuration
119#define CS0_ 0x01 ///< CS0 bit map mask
120#define CS1_ 0x02 ///< CS1 bit map mask
121#define CS2_ 0x04 ///< CS2 bit map mask
122#define CS3_ 0x08 ///< CS3 bit map mask
123#define CS4_ 0x10 ///< CS4 bit map mask
124#define CS5_ 0x20 ///< CS5 bit map mask
125#define CS6_ 0x40 ///< CS6 bit map mask
126#define CS7_ 0x80 ///< CS7 bit map mask
127///
128///< Number of Dimms on the current channel
129///< This is a mask used to indicate the number of dimms in a channel
130///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
131///
132#define ANY_NUM 0xFF ///< Any number of Dimms
133#define NO_DIMM 0x00 ///< No Dimms present
134#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
135#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
136#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
137#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
138
139///
140///< DIMM VOLTAGE MASKS
141///
142#define VOLT_ANY_ 0xFF ///< Any voltage configuration
143#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
144#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
145#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
146
147//
148// < Not applicable
149//
150#define NA_ 0 ///< Not applicable
151
152/*----------------------------------------------------------------------------------------
153 *
154 * Platform Specific Override Definitions for Socket, Channel and Dimm
155 * This indicates where a platform override will be applied.
156 *
157 *----------------------------------------------------------------------------------------
158 */
159///
160///< SOCKET MASKS
161///< Indicates associated processor sockets to apply override settings
162///
163#define ANY_SOCKET 0xFF ///< Apply to all sockets
164#define SOCKET0 0x01 ///< Apply to socket 0
165#define SOCKET1 0x02 ///< Apply to socket 1
166#define SOCKET2 0x04 ///< Apply to socket 2
167#define SOCKET3 0x08 ///< Apply to socket 3
168#define SOCKET4 0x10 ///< Apply to socket 4
169#define SOCKET5 0x20 ///< Apply to socket 5
170#define SOCKET6 0x40 ///< Apply to socket 6
171#define SOCKET7 0x80 ///< Apply to socket 7
172///
173///< CHANNEL MASKS
174///< Indicates Memory channels where override should be applied
175///
176#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
177#define CHANNEL_A 0x01 ///< Apply to Channel A
178#define CHANNEL_B 0x02 ///< Apply to Channel B
179#define CHANNEL_C 0x04 ///< Apply to Channel C
180#define CHANNEL_D 0x08 ///< Apply to Channel D
181///
182/// DIMM MASKS
183/// Indicates Dimm Slots where override should be applied
184///
185#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
186#define DIMM0 0x01 ///< Apply to Dimm Slot 0
187#define DIMM1 0x02 ///< Apply to Dimm Slot 1
188#define DIMM2 0x04 ///< Apply to Dimm Slot 2
189#define DIMM3 0x08 ///< Apply to Dimm Slot 3
190///
191/// REGISTER ACCESS MASKS
192/// Not supported as an at this time
193///
194#define ACCESS_NB0 0x0
195#define ACCESS_NB1 0x1
196#define ACCESS_NB2 0x2
197#define ACCESS_NB3 0x3
198#define ACCESS_NB4 0x4
199#define ACCESS_PHY 0x5
200#define ACCESS_DCT_XT 0x6
201///
202/// MOTHER BOARD DESIGN LAYERS MASKS
203/// Indicates the layer design of mother board
204///
205#define LAYERS_4 0x0
206#define LAYERS_6 0x1
207/*----------------------------------------------------------------------------------------
208 *
209 * Platform Specific Overriding Table Definitions
210 *
211 *----------------------------------------------------------------------------------------
212 */
213
214#define PSO_END 0 ///< Table End
215#define PSO_CKE_TRI 1 ///< CKE Tristate Map
216#define PSO_ODT_TRI 2 ///< ODT Tristate Map
217#define PSO_CS_TRI 3 ///< CS Tristate Map
218#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
219#define PSO_CLK_SPEED 5 ///< Clock Speed
220#define PSO_DIMM_TYPE 6 ///< Dimm Type
221#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
222#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
223#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
224#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
225#define PSO_MEM_TECH 11 ///< Channel Memory Type
226#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
227#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
228#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
229#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
230#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
231#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
232#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
233#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
234#define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override
235#define PSO_MOTHER_BOARD_LAYERS 21 ///< Mother board layer design
236
237/*----------------------------------
238 * CONDITIONAL PSO SPECIFIC ENTRIES
239 *---------------------------------*/
240// Condition Types
241#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
242#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
243#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
244#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
245#define PSO_CONDITION_REG 103 // Reserved
246#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
247// Action Types
248#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
249#define PSO_ACTION_ODT 120 ///< ODT values to override
250#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
251#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
252#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
253#define PSO_ACTION_REG 124 // Reserved
254#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
255#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
256#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
257
258/*----------------------------------
259 * TABLE DRIVEN PSO SPECIFIC ENTRIES
260 *---------------------------------*/
261// Condition descriptor
262#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
263
264// Overriding entry types
265#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
266#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
267#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
268#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
269#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
270#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
271#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
272#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
273#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
274#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
275#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
276#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
277#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
278#define PSO_TBLDRV_2D_TRAINING 222 ///< 2D training
279#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
280#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
281
282/*----------------------------------------------------------------------------------------
283 * CONDITIONAL OVERRIDE TABLE MACROS
284 *----------------------------------------------------------------------------------------
285 */
286#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
287 PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
288 ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
289
290#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
291 PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
292 , Bit7Map
293
294#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
295 PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
296
297#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
298 PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
299
300#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
301 PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
302
303#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
304 PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
305
306#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
307 PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
308
309#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
310 PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
311
312#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
313 PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
314
315#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
316 PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
317 BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
318
319#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
320 PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
321
322#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
323 Byte6Seed, Byte7Seed, ByteEccSeed) \
324 PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
325 Byte6Seed, Byte7Seed, ByteEccSeed
326
327#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
328 Byte6Seed, Byte7Seed, ByteEccSeed) \
329 PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
330 Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
331 Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
332
333#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
334 PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
335
336#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
337 PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
338
339#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
340 PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
341
342#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
343 PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
344
345#define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \
346 PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy
347
348#define MOTHER_BOARD_LAYERS(Layers) \
349 PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers
350
351/*----------------------------------------------------------------------------------------
352 * CONDITIONAL OVERRIDE TABLE MACROS
353 *----------------------------------------------------------------------------------------
354 */
355#define CONDITION_AND \
356 PSO_CONDITION_AND, 0
357
358#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
359 PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
360
361#define COND_SPD(Byte, Mask, Value) \
362 PSO_CONDITION_SPD, 3, Byte, Mask, Value
363
364#define COND_REG(Access, Offset, Mask, Value) \
365 PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
366 ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
367 ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
368
369#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
370 PSO_ACTION_ODT, 9, \
371 ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
372 Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
373
374#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
375 PSO_ACTION_ADDRTMG, 10, \
376 ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
377 ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
378 (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
379
380#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
381 PSO_ACTION_ODCCONTROL, 10, \
382 ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
383 ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
384 (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
385
386#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
387 PSO_ACTION_SLEWRATE, 10, \
388 ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
389 ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
390 (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
391
392#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
393 PSO_ACTION_SPEEDLIMIT, 9, \
394 ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
395 (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
396 (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
397 (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
398
399/*----------------------------------------------------------------------------------------
400 * END OF CONDITIONAL OVERRIDE TABLE MACROS
401 *----------------------------------------------------------------------------------------
402 */
403/*----------------------------------------------------------------------------------------
404 * TABLE DRIVEN OVERRIDE MACROS
405 *----------------------------------------------------------------------------------------
406 */
407/// Configuration sub-descriptors
408typedef enum {
409 CONFIG_GENERAL, ///< CONFIG_GENERAL
410 CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
411 CONFIG_RC2IBT, ///< CONFIG_RC2IBT
412 CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
413} Config_Type;
414
415// ====================
416// Configuration Macros
417// ====================
418#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
419 PSO_TBLDRV_CONFIG, 9, \
420 CONFIG_GENERAL, \
421 DimmPerCH, DimmVolt, \
422 ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
423 ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
424
425#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
426 PSO_TBLDRV_CONFIG, 7, \
427 CONFIG_SPEEDLIMIT, \
428 DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
429
430#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
431 PSO_TBLDRV_CONFIG, 10, \
432 CONFIG_RC2IBT, \
433 DimmPerCH, DimmVolt, \
434 ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
435 ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
436 NumOfReg
437
438//==================
439// Overriding Macros
440//==================
441#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
442 PSO_TBLDRV_SPEEDLIMIT, 6, \
443 (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
444 (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
445 (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
446
447#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
448 PSO_TBLDRV_ODT_RTTNOM, 2, \
449 TgtCS, RttNom
450
451#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
452 PSO_TBLDRV_ODT_RTTWR, 2, \
453 TgtCS, RttWr
454
455#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
456 PSO_TBLDRV_ODTPATTERN, 16, \
457 ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
458 ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
459 ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
460 ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
461
462#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
463 PSO_TBLDRV_ADDRTMG, 4, \
464 ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
465
466#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
467 PSO_TBLDRV_ODCCTRL, 4, \
468 ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
469
470#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
471 PSO_TBLDRV_SLOWACCMODE, 1, \
472 SlowAccMode
473
474#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
475 PSO_TBLDRV_RC2_IBT, 2, \
476 TgtDimm, IBT
477
478#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
479 PSO_TBLDRV_CONFIG, 1, \
480 CONFIG_DONT_CARE, \
481 PSO_TBLDRV_MR0_CL, 3, \
482 RegValOfTcl, MR0CL13, MR0CL0
483
484#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
485 PSO_TBLDRV_CONFIG, 1, \
486 CONFIG_DONT_CARE, \
487 PSO_TBLDRV_MR0_WR, 2, \
488 RegValOfTwr, MR0WR
489
490#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
491 PSO_TBLDRV_CONFIG, 1, \
492 CONFIG_DONT_CARE, \
493 PSO_TBLDRV_RC10_OPSPEED, 5, \
494 ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
495 MR10OPSPEED
496
497#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
498 PSO_TBLDRV_LRDIMM_IBT, 4, \
499 F0RC8, F1RC0, F1RC1, F1RC2
500
501#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \
502 PSO_TBLDRV_2D_TRAINING, 1, \
503 Training2dMode
504
505//============================
506// Macros for removing entries
507//============================
508#define INVALID_CONFIG_FLAG 0x8000
509
510#define TBLDRV_INVALID_CONFIG \
511 PSO_TBLDRV_INVALID_TYPE, 0
512
513/*----------------------------------------------------------------------------------------
514 * END OF TABLE DRIVEN OVERRIDE MACROS
515 *----------------------------------------------------------------------------------------
516 */
517
518#endif // _PLATFORM_MEMORY_CONFIGURATION_H_