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review.coreboot.org / coreboot / 7687e7767f2d2321b57fa8eab68b7e954e57ad42 / . / src / vendorcode / amd / pi / 00730F01 / Include / Ids.h
blob: 28128ab37f9c4a0d4fad557470fd470b1b0d5472 [file] [log] [blame]
Martin Roth7687e772023-08-22 16:32:20 -0600[diff] [blame^]1/* SPDX-License-Identifier: BSD-3-Clause */
2
Marc Jones0b11bd02015-07-19 15:20:17 -0600[diff] [blame]3/* $NoKeywords:$ */
4/**
5 * @file
6 *
7 * AMD IDS Routines
8 *
9 * Contains AMD AGESA Integrated Debug Macros
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: IDS
14 * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
15 */
16/*****************************************************************************
17 *
18 * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ***************************************************************************/
44
45 /* Macros to aid debugging */
46 /* These definitions expand to zero (0) bytes of code when disabled */
47
48#ifndef _IDS_H_
49#define _IDS_H_
50
51#undef FALSE
52#undef TRUE
53#define FALSE 0
54#define TRUE 1
55// Proto type for optionsids.h
56typedef UINT32 IDS_STATUS; ///< Status of IDS function.
57#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful.
58#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed.
59
60#define IDS_STRINGIZE(a) #a ///< for define stringize macro
61#ifndef IDS_DEADLOOP
62 #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
63#endif
64/**
65 * IDS Option Hook Points
66 *
67 * These are the values to indicate hook point in AGESA for IDS Options.
68 *
69 */
70typedef enum { //vv- for debug reference only
71 IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
72 ///< IDS Object is initialized.
73 ///< Override CPU Core Leveling Mode.
74 ///< Set P-State in Post
75 IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
76 IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
77 ///< It will be used to control the following tables.
78 ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
79 ///< ACPI SRAT Table
80 ///< ACPI SLIT Table
81 ///< ACPI WHEA Table
82 ///< DMI Table
83 IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
84 IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
85 IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
86 IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
87 ///< Control Interleaving and DRAM memory hole
88 ///< Override the setting of ECC Control
89 ///< Override the setting of Online Spare Rank
90 IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
91 IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
92 IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
93 IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
94 IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
95 IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
96 IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
97 IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
98 IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
99 IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
100 IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
101 IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
102 IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init
103 IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt
104 IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume
105 IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume
106 IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init
107
108 IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime
109
110 IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
111 IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
112 IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
113 IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
114 IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
115 IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
116 IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
117 IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
118
119 // All the above timing point is used by BVM, their value should never be changed
120 IDS_INIT_DRAM_TABLE, ///< 40 Generate override table for Dram Timing
121 ///< Dram Controller, Drive Strength and DQS Timing
122 IDS_GET_DRAM_TABLE, ///< 41 Generate override table for Dram Timing
123 IDS_GANGING_MODE, ///< 42 override Memory Mode Unganged
124 IDS_POWERDOWN_MODE, ///< 43 override Power Down Mode
125 IDS_BURST_LENGTH32, ///< 44 override Burst Length32
126 IDS_ALL_MEMORY_CLOCK, ///< 45 override All Memory Clks Enable
127 IDS_ECC, ///< 46 override ECC parameter
128 IDS_ECCSYMBOLSIZE, ///< 47 override ECC symbol size
129 IDS_CPU_Early_Override, ///< 48 override CPU early parameter
130 IDS_CACHE_FLUSH_HLT, ///< 49 override Cache Flush Hlt
131 IDS_CHANNEL_INTERLEAVE, ///< 4a override Channel Interleave
132 IDS_MEM_ERROR_RECOVERY, ///< 4b override memory error recovery
133 IDS_MEM_RETRAIN_TIMES, ///< 4c override memory retrain times
134 IDS_MEM_SIZE_OVERLAY, ///< 4d Override the syslimit
135 IDS_CHECK_NEGATIVE_WL, ///< 4e Check for negative write leveling result
136 IDS_DLL_SHUT_DOWN, ///< 4f Check for Dll Shut Down
137 IDS_POR_MEM_FREQ, ///< 50 Entry to enable/disable MemClk frequency enforcement
138 IDS_PHY_DLL_STANDBY_CTRL, ///< 51 Enable/Disable Phy DLL standby feature
139 IDS_PLATFORMCFG_OVERRIDE, ///< 52 Hook for Override PlatformConfig structure
140 IDS_LOADCARD_ERROR_RECOVERY, ///< 53 Special error handling for load card support
141 IDS_MEM_IGNORE_ERROR, ///< 54 Ignore error and do not do fatal exit in memory
142 IDS_GNB_SMU_SERVICE_CONFIG, ///< 55 Config GNB SMU service
143 IDS_GNB_ORBDYNAMIC_WAKE, ///< 56 config GNB dynamic wake
144 IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 57 override ids gnb platform config
145 IDS_GNB_LCLK_DPM_EN, ///< 58 override GNB LCLK DPM configuration
146 IDS_GNB_LCLK_DEEP_SLEEP, ///< 59 override GNB LCLK DPM deep sleep
147 IDS_GNB_CLOCK_GATING, ///< 5a Override GNB Clock gating config
148 IDS_NB_PSTATE_DIDVID, ///< 5b Override NB P-state settings
149 IDS_CPB_CTRL, ///< 5c Config the Core peformance boost feature
150 IDS_HTC_CTRL, ///< 5d Hook for Hardware Thermal Control
151 IDS_CC6_WORKAROUND, ///< 5e Hook for skip CC6 work around
152 IDS_MEM_MR0, ///< 5f Hook for override Memory Mr0 register
153 IDS_TRAP_TABLE, ///< 60 Hook for add IDS register table to the loop
154 IDS_NBBUFFERALLOCATIONATEARLY, ///< 61 Hook for override North bridge bufer allocation
155 IDS_BEFORE_S3_SPECIAL, ///< 62 Hook to bypass S3 special functions
156 IDS_SET_PCI_REGISTER_ENTRY, ///< 63 Hook to SetRegisterForPciEntry
157 IDS_ERRATUM463_WORKAROUND, ///< 64 Hook to Erratum 463 workaround
158 IDS_BEFORE_MEMCLR, ///< 65 Hook before set Memclr bit
159 IDS_OVERRIDE_IO_CSTATE, ///< 66 Hook for override io C-state setting
160 IDS_NBPSDIS_OVERRIDE, ///< 67 Hook for override NB pstate disable setting
161 IDS_NBPS_REG_OVERRIDE, ///< 68 Hook for override Memory NBps reg
162 IDS_LOW_POWER_PSTATE, ///< 69 Hook for disable Low power_Pstates feature
163 IDS_CST_CREATE, ///< 6a Hook for create _CST
164 IDS_CST_SIZE, ///< 6b Hook for get _CST size
165 IDS_ENFORCE_VDDIO, ///< 6c Hook to override VDDIO
166 IDS_STRETCH_FREQUENCY_LIMIT, ///< 6d Hook for enforcing memory stretch frequency limit
167 IDS_INIT_MEM_REG_TABLE, ///< 6e Hook for init memory register table
168 IDS_SKIP_FUSED_MAX_RATE, ///< 6f Hook to skip fused max rate cap
169 IDS_FCH_INIT_AT_RESET, ///< 70 Hook for FCH reset parameter
170 IDS_FCH_INIT_AT_ENV, ///< 71 Hook for FCH ENV parameter
171 IDS_ENFORCE_PLAT_TABLES, ///< 72 Hook to enforce platform specific tables
172 IDS_NBPS_MIN_FREQ, ///< 73 Hook for override MIN nb ps freq
173 IDS_GNB_FORCE_CABLESAFE, ///< 74 Hook for override Force Cable Safe
174 IDS_SKIP_PM_TRANSITION_STEP, ///< 75 Hook for provide IDS ability to skip this PM step
175 IDS_GNB_PROPERTY, ///< 76 Hook for GNB Property
176 IDS_GNB_PCIE_POWER_GATING, ///< 77 Hook for GNB PCIe Power Gating
177 IDS_MEM_DYN_DRAM_TERM, ///< 78 Hook for Override Dynamic Dram Term
178 IDS_MEM_DRAM_TERM, ///< 79 Hook for Override Dram Term
179 IDS_GNB_ALTVDDNB, ///< 7a Hook for Override AltVddNB
180 IDS_UCODE, ///< 7b Enable or Disable microcode patching
181 IDS_FAM_REG_GMMX, ///< 7c GMMX register access
182 IDS_MEMORY_POWER_POLICY, ///< 7d Memory power policy
183 IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 7e Hook for enforcing memory stretch frequency limit
184 IDS_CPU_FEAT, ///< 7f Hook for runtime force cpu feature disable
185 IDS_AFTER_DCT_PHY_ACCESS, ///< 80 Hook for DctAccessDone check
186 IDS_FORCE_PHY_TO_M0, ///< 81 Hook to bypass M0 enforcement
187 IDS_GNB_PMM_SWTJOFFSET, ///< 82 Hook to GNBSWTJOFFSET
188 IDS_LOCK_DRAM_CFG, ///< 83 Hook to BFLockDramCfg
189 IDS_BEFORE_GEN2_INIT, ///< 84 Hook to Before Gen2 Init
190 IDS_BEFORE_GPP_TRAINING, ///< 85 Hook to Before Gpp training
191 IDS_BEFORE_RECONFIGURATION, ///< 86 Hook to Before Reconfiguration
192 IDS_BEFORE_GEN3_INIT, ///< 87 Hook to Before Gen3 Init
193 IDS_BEFORE_POWER_GATING, ///< 88 Hook to Before Power Gating
194 IDS_AFTER_EARLY_INIT_ONCORE, ///< 89 Hook to after EarlyInit On Core
195 IDS_GNB_PCIE_PORT_REMAP, ///< 8a Hook to change mapping of PCIe devices
196 IDS_ECC_CONTROL, ///< 8b Enable/Disable ECC feature
197 IDS_GNB_PCIE_PHY_ISOLATION, ///< 8c Enable/Disable PCIE PHY ISOLATION
198 IDS_AFTER_RESTORING_PCI_REG, ///< 8d Hook after restoring PCI register during S3 resume
199 IDS_MSR_ACCESS_OVERRIDE, ///< 8e Hook to disable MSR access
200 IDS_REPORT_SMU_FW_VERSION, ///< 8f Hook to report SMU firmware version
201 IDS_GNB_LOAD_SAMU_PATCH, ///< 90 Hook to Load SAMU patch
202 IDS_DLLSTAGGERDLY_OVERRIDE, ///< 91 Hook to skip Dll Stagger Delay
203 IDS_CSAMPLE_TIMER, ///< 92 Hook to override CSampleTimer
204 IDS_PIPE_THROTTLE, ///< 93 Hook to override PipeThrottle
205 IDS_GNB_PMM_NATIVEGEN1PLL, ///< 94 Enable/Disable Native Gen1 PLL
206 IDS_BEFORE_PLAT_TABLES, ///< 95 Hook before processing platform specific tables
207 IDS_GNB_PCIE_MASTERPLL_SELECTION, ///< 96 Hook to override PCIe Master PLL selection
208 IDS_GNB_PCIE_PHYLANE_CONFIG, ///< 97 Hook to override PCIe PhyLane configuration
209 IDS_DSM_LP_SELECTION, ///< 98 Set Dsm low power mode
210 IDS_GNB_EQUAL_PRESET, ///< 99 Set equalization preset
211 IDS_GNB_GEN1_LOOPBACK, ///< 9a Override Gen 1 loopback mode
212 IDS_GNB_SMU_SERVICE_MASK, ///< 9b Override SMU service enablement mask
213 IDS_BEFORE_HT_MEM_MAP, ///< 9c Hook before mapping memory address space among DCTs
214 IDS_GNB_GEN3_SETTINGS_OVERRIDE, ///< 9d Hook to override Gen3 Adapt PI Offset Bypass Enable
215 IDS_GNB_TARGET_TDP, ///< 9e Hook to override Target TDP
216 IDS_GNB_LOAD_BUILD_OPTIONS, ///< 9f Hook to override gnb build options
217 IDS_GNB_SMU_BIOS_TABLE, ///< A0 Hook to override gnb smu bios table
218 IDS_LOW_POWER_RCVR_EN_CTRL, ///< A1 Hook to override LowPowerRcvrEn mode
219 IDS_OPTION_END ///< A2 End of IDS option
220} AGESA_IDS_OPTION;
221
222#include "OptionsIds.h"
223#include "Filecode.h"
224#include "IdsPerf.h"
225
226/* Initialize IDS controls */
227#ifndef IDSOPT_IDS_ENABLED
228 #define IDSOPT_IDS_ENABLED FALSE
229#endif
230
231#ifndef IDSOPT_CONTROL_ENABLED
232 #define IDSOPT_CONTROL_ENABLED FALSE
233#endif
234
235#ifndef IDSOPT_CONTROL_NV_TO_CMOS
236 #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
237#endif
238
239#ifndef IDSOPT_TRACING_ENABLED
240 #define IDSOPT_TRACING_ENABLED FALSE
241#endif
242
243#ifndef IDSOPT_TRACE_USER_OPTIONS
244 #define IDSOPT_TRACE_USER_OPTIONS TRUE
245#endif
246
247#ifndef IDSOPT_PERF_ANALYSIS
248 #define IDSOPT_PERF_ANALYSIS FALSE
249#endif
250
251#ifndef IDSOPT_HEAP_CHECKING
252 #define IDSOPT_HEAP_CHECKING FALSE
253#endif
254
255#ifndef IDSOPT_ASSERT_ENABLED
256 #define IDSOPT_ASSERT_ENABLED FALSE
257#endif
258
259#ifndef IDSOPT_ERROR_TRAP_ENABLED
260 #define IDSOPT_ERROR_TRAP_ENABLED FALSE
261#endif
262
263#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
264 #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
265#endif
266
267#ifndef IDSOPT_DEBUG_CODE_ENABLED
268 #define IDSOPT_DEBUG_CODE_ENABLED FALSE
269#endif
270
271#ifndef IDSOPT_IDT_EXCEPTION_TRAP
272 #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
273#endif
274
275#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
276 #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
277#endif
278
279#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT
280 #define IDSOPT_TRACING_CONSOLE_HDTOUT TRUE
281#endif
282
283#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT
284 #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
285#endif
286
287#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
288 #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
289#endif
290
291#ifndef IDSOPT_TRACING_CONSOLE_RAM
292 #define IDSOPT_TRACING_CONSOLE_RAM FALSE
293#endif
294
295#if IDSOPT_IDS_ENABLED == FALSE
296 #undef IDSOPT_CONTROL_ENABLED
297 #undef IDSOPT_TRACING_ENABLED
298 #undef IDSOPT_PERF_ANALYSIS
299 #undef IDSOPT_HEAP_CHECKING
300 #undef IDSOPT_ASSERT_ENABLED
301 #undef IDSOPT_ERROR_TRAP_ENABLED
302 #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
303 #undef IDSOPT_DEBUG_CODE_ENABLED
304 #undef IDSOPT_TRACE_USER_OPTIONS
305 #undef IDSOPT_TRACING_CONSOLE_HDTOUT
306 #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
307 #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
308 #undef IDSOPT_TRACING_CONSOLE_RAM
309
310 #define IDSOPT_CONTROL_ENABLED FALSE
311 #define IDSOPT_TRACING_ENABLED FALSE
312 #define IDSOPT_PERF_ANALYSIS FALSE
313 #define IDSOPT_HEAP_CHECKING FALSE
314 #define IDSOPT_ASSERT_ENABLED FALSE
315 #define IDSOPT_ERROR_TRAP_ENABLED FALSE
316 #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
317 #define IDSOPT_DEBUG_CODE_ENABLED FALSE
318 #define IDSOPT_TRACE_USER_OPTIONS FALSE
319 #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
320 #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
321 #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
322 #define IDSOPT_TRACING_CONSOLE_RAM FALSE
323#endif
324
325//Disable when master token Tracing is set to FALSE
326#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE))
327 #undef IDSOPT_TRACING_CONSOLE_HDTOUT
328 #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
329
330 #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
331 #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
332
333 #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
334 #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
335
336 #undef IDSOPT_TRACING_CONSOLE_RAM
337 #define IDSOPT_TRACING_CONSOLE_RAM FALSE
338#endif
339
340//Disable Tracing if all support HW layer set to FALSE
341#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE) && (IDSOPT_TRACING_CONSOLE_RAM == FALSE))
342 #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE
343 #undef IDSOPT_TRACING_ENABLED
344 #define IDSOPT_TRACING_ENABLED FALSE
345 #endif
346#endif
347/**
348 * Make a Progress Report to the User.
349 *
350 * This Macro is always enabled. The default action is to write the TestPoint value
351 * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
352 * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
353 * in OptionsIds.h in their build tip.
354 *
355 * @param[in] TestPoint The value for display indicating progress
356 * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
357 *
358 **/
359
360#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))
361
362#ifndef IDS_DEBUG_PORT
363 #define IDS_DEBUG_PORT 0x80
364#endif
365
366/**
367 * @def STOP_HERE
368 * (macro) - Causes program to halt. This is @b only for use during active debugging .
369 *
370 * Causes the program to halt and display the file number of the source of the
371 * halt (displayed in decimal).
372 *
373 **/
374#if IDSOPT_IDS_ENABLED == TRUE
375 #ifdef STOP_CODE
376 #undef STOP_CODE
377 #endif
378 #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
379 ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
380 (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
381 #define STOP_HERE IdsErrorStop (STOP_CODE);
382#else
383 #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
384#endif
385
386/**
387 * @def ASSERT
388 * Test an assertion that the given statement is True.
389 *
390 * The statement is evaluated to a boolean value. If the statement is True,
391 * then no action is taken (no error). If the statement is False, a error stop
392 * is generated to halt the program. Used for testing for fatal errors that
393 * must be resolved before production. This is used to do parameter checks,
394 * bounds checking, range checks and 'sanity' checks.
395 *
396 * @param[in] conditional Assert that evaluating this conditional results in TRUE.
397 *
398 **/
399#ifndef ASSERT
400 #if IDSOPT_ASSERT_ENABLED == TRUE
401 #ifdef STOP_CODE
402 #undef STOP_CODE
403 #endif
404 #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
405 ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
406 (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
407
408 #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
409 #else
410 #define ASSERT(conditional)
411 #endif
412#endif
413
414#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
415 #undef IDSOPT_ERROR_TRAP_ENABLED
416 #define IDSOPT_ERROR_TRAP_ENABLED TRUE
417 #define IDS_CAR_CORRUPTION_CHECK(StdHeader) IdsCarCorruptionCheck(StdHeader)
418#else
419 #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
420#endif
421/**
422 * @def DEBUG_CODE
423 * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
424 *
425 */
426#ifndef DEBUG_CODE
427 #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
428 #define DEBUG_CODE(Code) Code
429 #else
430 #define DEBUG_CODE(Code)
431 #endif
432#endif
433
434/**
435 * @def IDS_ERROR_TRAP
436 * Trap AGESA Error events with stop code display.
437 *
438 * Works similarly to use of "ASSERT (FALSE);"
439 *
440 */
441#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
442 #ifdef STOP_CODE
443 #undef STOP_CODE
444 #endif
445 #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
446 ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
447 (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
448
449 #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE)
450#else
451 #define IDS_ERROR_TRAP
452#endif
453
454///give the extended Macro default value
455#ifndef __IDS_EXTENDED__
456 #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
457 #define IDS_TRACE_DEFAULT (0)
458 #define IDS_INITIAL_F15_TN_PM_STEP
459 #define IDS_INITIAL_F15_KV_PM_STEP
460 #define IDS_INITIAL_F15_CZ_PM_STEP
461 #define IDS_INITIAL_F16_KB_PM_STEP
462 #define IDS_INITIAL_F16_ML_PM_STEP
463 #define IDS_F15_TN_PM_CUSTOM_STEP
464 #define IDS_F15_KV_PM_CUSTOM_STEP
465 #define IDS_F15_CZ_PM_CUSTOM_STEP
466 #define IDS_F16_KB_PM_CUSTOM_STEP
467 #define IDS_F16_ML_PM_CUSTOM_STEP
468 #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
469 #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
470 #define IDS_EXTENDED_HEAP_SIZE 0
471 #define IDS_EXT_INCLUDE_F15(file)
472 #define IDS_EXT_INCLUDE(file)
473 #define IDS_PAD_4K
474 #define IDS_EXTENDED_CODE(code)
475 #define SMU_FIRMWARE_PADS_1K
476#endif
477
478#ifndef IDS_NUM_NV_ITEM
479 #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
480#endif
481
482#define IDS_CMOS_INDEX_PORT 0x70
483#define IDS_CMOS_DATA_PORT 0x71
484#define IDS_CMOS_REGION_START 0x20
485#define IDS_CMOS_REGION_END 0x7F
486#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
487
488#if IDSOPT_CONTROL_ENABLED == TRUE
489 #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \
490 AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))
491
492 #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \
493 IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader))
494 #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
495 #undef IDS_AP_GET_NV_FROM_CMOS
496 #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x)
497 #ifdef IDS_OPT_CMOS_INDEX_PORT
498 #undef IDS_CMOS_INDEX_PORT
499 #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
500 #endif
501
502 #ifdef IDS_OPT_CMOS_DATA_PORT
503 #undef IDS_CMOS_DATA_PORT
504 #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
505 #endif
506
507 #ifdef IDS_OPT_CMOS_REGION_START
508 #undef IDS_CMOS_REGION_START
509 #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
510 #endif
511
512 #ifdef IDS_OPT_CMOS_REGION_END
513 #undef IDS_CMOS_REGION_END
514 #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
515 #endif
516 #endif
517#else
518 #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
519
520 #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS
521#endif
522
523/**
524 * Macro to add a *skip* hook for IDS options
525 *
526 * The default minimal action is to do nothing and there is no any code to increase.
527 * For debug environments, IDS dispatcher function will be called to perform
528 * the detailed action and to skip AGESA code if necessary.
529 *
530 * @param[in] IdsOption IDS Option ID for this hook point
531 * @param[in, out] DataPtr Data Pointer to override
532 * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
533 *
534 *
535 **/
536
537#if IDSOPT_CONTROL_ENABLED == TRUE
538 #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \
539 if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)
540#else
541 #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
542#endif
543
544/**
545 * Macro to add a heap manager routine
546 *
547 * when memory is allocated the heap manager actually allocates two extra dwords of data,
548 * one dword buffer before the actual memory, and one dword afterwards.
549 * a complete heap walk and check to be performed at any time.
550 * it would ASSERT if the heap is corrupt
551 *
552 * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
553 *
554 *
555 **/
556
557// Heap debug feature
558#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head"
559#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail"
560#if IDSOPT_IDS_ENABLED == TRUE
561 #if IDSOPT_HEAP_CHECKING == TRUE
562 #define SIZE_OF_SENTINEL 4
563 #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail")
564 #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
565 #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
566 #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)
567 #else
568 #define SIZE_OF_SENTINEL 0
569 #define NUM_OF_SENTINEL 0
570 #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
571 #define SET_SENTINEL_AFTER(NodePtr)
572 #define Heap_Check(stdheader)
573 #endif
574#else
575 #define SIZE_OF_SENTINEL 0
576 #define NUM_OF_SENTINEL 0
577 #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
578 #define SET_SENTINEL_AFTER(NodePtr)
579 #define Heap_Check(stdheader)
580#endif
581
582/**
583 * Macro to add IDT for debugging exception.
584 *
585 * A debug feature. Adding a 'jmp $' into every exception handler.
586 * So debugger could use HDT to skip 'jmp $' and execute the iret,
587 * then they could find which instruction cause the exception.
588 *
589 * @param[in] FunctionId IDS Function ID for this hook point
590 * @param[in, out] DataPtr Data Pointer to override
591 * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
592 *
593 *
594 **/
595#if IDSOPT_IDS_ENABLED == TRUE
596 #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
597 #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader)
598 #else
599 #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
600 #endif
601#else
602 #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
603#endif
604
605
606 //Note a is from 0 to 63
607#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
608//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
609//Memory Masks
610#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
611#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
612#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
613#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
614#define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4)
615#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
616#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
617#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
618#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
619#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
620
621//CPU Masks
622#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
623#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
624#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
625#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
626#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
627#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
628#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
629#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
630#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
631#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
632
633//GNB Masks
634#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
635#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
636#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
637#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
638#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
639#define NB_MISC DEBUG_PRINT_SHIFT (25)
640#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
641#define GFX_MISC DEBUG_PRINT_SHIFT (27)
642#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
643#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
644
645//Topology Masks
646#define TOPO_TRACE DEBUG_PRINT_SHIFT (30)
647#define TOPO_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
648#define TOPO_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
649#define TOPO_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
650#define TOPO_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
651#define TOPO_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
652#define TOPO_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
653#define TOPO_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
654#define TOPO_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
655#define TOPO_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
656
657//FCH Masks
658#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
659#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
660#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
661#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
662#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
663#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
664#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
665#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
666#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
667#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
668
669//Other Masks
670#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
671#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
672#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
673
674//Ids Masks
675#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
676#define BVM_TRACE DEBUG_PRINT_SHIFT (54)
677#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
678#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
679
680//S3
681#define S3_TRACE DEBUG_PRINT_SHIFT (57)
682
683//Library function to read/write PCI/MSR registers
684#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)
685#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)
686
687//AGESA test points
688#define TEST_POINT DEBUG_PRINT_SHIFT (60)
689
690//Reserved for platform log
691#define PLAT_RSV1 DEBUG_PRINT_SHIFT (61)
692#define PLAT_RSV2 DEBUG_PRINT_SHIFT (62)
693#define PLAT_RSV3 DEBUG_PRINT_SHIFT (63)
694
695#define GNB_TRACE_DEFAULT\
696 (\
697 GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \
698 )
699
700#define GNB_TRACE_REG\
701 (\
702 PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \
703 NB_SMUREG_TRACE | GNB_TRACE_RSV1 \
704 )
705
706#define GNB_TRACE_ALL\
707 (\
708 GNB_TRACE_DEFAULT | GNB_TRACE_REG \
709 )
710
711#define CPU_TRACE_ALL\
712 (\
713 CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \
714 CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \
715 CPU_TRACE_RSV8 | CPU_TRACE_RSV9\
716 )
717
718#define MEMORY_TRACE_ALL\
719 (\
720 MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \
721 MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \
722 MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\
723 )
724
725#define TOPO_TRACE_ALL\
726 (\
727 TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \
728 TOPO_TRACE_RSV4 | TOPO_TRACE_RSV5 | TOPO_TRACE_RSV6 | TOPO_TRACE_RSV7 | \
729 TOPO_TRACE_RSV8 | TOPO_TRACE_RSV9\
730 )
731
732#define FCH_TRACE_ALL\
733 (\
734 FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \
735 FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \
736 FCH_TRACE_RSV8 | FCH_TRACE_RSV9\
737 )
738
739#define IDS_TRACE_ALL\
740 (\
741 IDS_TRACE | BVM_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\
742 )
743
744#define OTHER_TRACE_ALL\
745 (\
746 MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\
747 )
748
749
750#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull)
751#ifndef IDS_DEBUG_PRINT_MASK
752 #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
753#endif
754
755/// if no specific define INIT & EXIT will be NULL
756#define IDS_HDT_CONSOLE_INIT(x)
757#define IDS_HDT_CONSOLE_EXIT(x)
758
759/// AGESA tracing service
760#if IDSOPT_TRACING_ENABLED == TRUE
761 #ifdef VA_ARGS_SUPPORTED
762 #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
763 #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__)
764 #else
765 #pragma warning(disable: 4127)
766 #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \
767 else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \
768 else if (f == TOPO_TRACE) AmdIdsDebugPrintTopology (s, __VA_ARGS__); \
769 else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \
770 else AmdIdsDebugPrint (f, s, __VA_ARGS__)
771 #endif
772 #else
773 #define IDS_HDT_CONSOLE AmdIdsDebugPrint
774 #endif
775 #define CONSOLE AmdIdsDebugPrintAll
776 #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code
777 #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t)
778#else
779 #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsDebugPrint
780 #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
781 #define CONSOLE CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
782 #define IDS_TIMEOUT_CTL(t)
783#endif
784
785/// Macros for serial port tracing
786#ifdef IDSOPT_SERIAL_PORT
787 #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT
788#endif
789
790#ifndef IDS_SERIAL_PORT
791 #define IDS_SERIAL_PORT 0x3F8
792#endif
793
794// Macros for redirect IO tracing
795#ifdef IDSOPT_DEBUG_PRINT_IO_PORT
796 #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT
797#endif
798
799#ifndef IDS_DEBUG_PRINT_IO_PORT
800 #define IDS_DEBUG_PRINT_IO_PORT 0x80
801#endif
802
803#define IDS_DPRAM_BASE 0
804#define IDS_DPRAM_SIZE 0
805///Default policy, shift the old data when buffer full
806#define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL FALSE
807#if IDSOPT_TRACING_CONSOLE_RAM == TRUE
808 #ifdef IDSOPT_DPRAM_BASE
809 #undef IDS_DPRAM_BASE
810 #define IDS_DPRAM_BASE IDSOPT_DPRAM_BASE
811 #else
812 #error "Debug Print Ram Base not specified, please define IDSOPT_DPRAM_BASE in optionsids.h"
813 #endif
814
815 #ifdef IDSOPT_DPRAM_SIZE
816 #undef IDS_DPRAM_SIZE
817 #define IDS_DPRAM_SIZE IDSOPT_DPRAM_SIZE
818 #else
819 #error "Debug Print Ram size not specified, please define IDSOPT_DPRAM_SIZE in optionsids.h"
820 #endif
821
822 #ifdef IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
823 #define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
824 #endif
825#endif
826/**
827 * Macros to add HDT OUT
828 *
829 * The default minimal action is to do nothing and there is no any code to increase.
830 * For debug environments, the debug information can be displayed in HDT or other
831 * devices.
832 *
833 **/
834#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
835 #undef IDS_HDT_CONSOLE_INIT
836 #undef IDS_HDT_CONSOLE_EXIT
837 #define IDS_HDT_CONSOLE_INIT(x) AmdIdsHdtOutInit (x)
838 #define IDS_HDT_CONSOLE_EXIT(x) AmdIdsHdtOutExit (x)
839 #define IDS_HDT_CONSOLE_S3_EXIT(x) AmdIdsHdtOutS3Exit (x)
840 #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) AmdIdsHdtOutS3ApExit (x)
841
842 #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) AmdIdsHdtOutBufferFlush (x)
843 #define IDS_HDT_CONSOLE_ASSERT(x) AmdIdsDebugPrintAssert (x)
844 #define IDS_FUNCLIST_ADDR ScriptFuncList
845 #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[]
846#else
847 #define IDS_HDT_CONSOLE_S3_EXIT(x)
848 #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
849 #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
850 #define IDS_HDT_CONSOLE_ASSERT(x)
851 #define IDS_FUNCLIST_ADDR NULL
852 #define IDS_FUNCLIST_EXTERN()
853#endif
854
855#if IDSOPT_TRACING_ENABLED == TRUE
856 #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE
857 #undef IDS_HDT_CONSOLE
858 #define IDS_HDT_CONSOLE IDSOPT_CUSTOMIZE_TRACING_SERVICE
859 #endif
860 #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
861 #undef IDS_HDT_CONSOLE_INIT
862 #define IDS_HDT_CONSOLE_INIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x)
863 #endif
864 #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
865 #undef IDS_HDT_CONSOLE_EXIT
866 #define IDS_HDT_CONSOLE_EXIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x)
867 #endif
868#endif
869
870#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
871
872#if IDSOPT_PERF_ANALYSIS == TRUE
873 #include "IdsPerf.h"
874 #ifdef STOP_CODE
875 #undef STOP_CODE
876 #endif
877 #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
878 ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
879 (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
880
881 #define IDS_PERF_TIMESTAMP(ID, StdHeader) IdsPerfTimestamp (STOP_CODE, ID, (StdHeader))
882 #define IDS_PERF_ANALYSE(StdHeader) IdsPerfAnalyseTimestamp (StdHeader)
883#else
884 #define IDS_PERF_TIMESTAMP(ID, StdHeader)
885 #define IDS_PERF_ANALYSE(StdHeader)
886#endif
887
888///For IDS feat use
889#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
890#define IDS_BSP_ONLY TRUE
891#define IDS_ALL_CORES FALSE
892
893#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE
894
895#define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization.
896
897#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x83 ///< The function data of IDS callout function of GNB pp fuse table.
898#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x84 ///< The function data of IDS callout function of GNB integrated table.
899#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x85 ///< The function data of IDS callout function of GNB NB power gate config.
900#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x86 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
901#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x87 ///< The function data of IDS callout function of GNB pcie platform config.
902#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x88 ///< The function data of IDS callout function of GNB pcie PHY config.
903#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x89 ///< The function data of IDS callout function of GNB GMM register override
904#define IDS_CALLOUT_FCH_INIT_RESET 0x8A ///< The function data of IDS callout function of FchInitReset
905#define IDS_CALLOUT_FCH_INIT_ENV 0x8B ///< The function data of IDS callout function of FchInitEnv.
906#define IDS_CALLOUT_POWER_PLAN_INIT 0x8C ///< The function data of IDS callout function of Override Power Plan Init
907#define IDS_CALLOUT_GET_PERF_BUFFER 0x8D ///< The function data of IDS callout function of get platform performance buffer.
908#define IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG 0x8E ///< The function data of IDS callout function of Bapm Package Power.
909#define IDS_CALLOUT_SMU_PORT80_LOGGING_BUFFER 0x8F ///< The function data of IDS callout function of SMU port80 logging buffer.
910#define IDS_CALLOUT_GNB_BEFORE_EARLY_INIT 0x90 ///< The function data of IDS callout function of GNB before early init.
911#define IDS_CALLOUT_GNB_SMUBIOSTABLE_OVERRIDE 0x91 ///< The function data of IDS callout function of GNB smu bios table.
912
913/// Function entry for HDT script to call
914typedef struct _SCRIPT_FUNCTION {
915 UINT32 FuncAddr; ///< Function address in ROM
916 CHAR8 FuncName[40]; ///< Function name
917} SCRIPT_FUNCTION;
918
919/// Data Structure for Mem ECC parameter override
920typedef struct {
921 IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
922 IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
923 IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
924 IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
925 IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
926 IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
927 IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
928} ECC_OVERRIDE_STRUCT;
929
930
931
932
933/**
934 * AGESA Test Points
935 *
936 * These are the values displayed to the user to indicate progress through boot.
937 * These can be used in a debug environment to stop the debugger at a specific
938 * test point:
939 * For SimNow!, this command
940 * bi 81 w vb 49
941 * will stop the debugger on one of the TracePoints (49 is the TP value in this example).
942 *
943 */
944typedef enum {
945 StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
946
947 // Memory test points
948 TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
949 TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
950 TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
951 TpProcMemDramInit, ///< 04 .. DRAM initialization
952 TpProcMemSPDChecking, ///< 05 ..
953 TpProcMemModeChecking, ///< 06 ..
954 TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
955 TpProcMemSpdTiming, ///< 08 ..
956 TpProcMemDramMapping, ///< 09 ..
957 TpProcMemPlatformSpecificConfig, ///< 0A ..
958 TPProcMemPhyCompensation, ///< 0B ..
959 TpProcMemStartDcts, ///< 0C ..
960 TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
961 TpProcMemPhyFenceTraining, ///< 0E ..
962 TpProcMemSynchronizeDcts, ///< 0F ..
963 TpProcMemSystemMemoryMapping, ///< 10 ..
964 TpProcMemMtrrConfiguration, ///< 11 ..
965 TpProcMemDramTraining, ///< 12 ..
966 TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
967 TpProcMemWriteLevelizationTraining, ///< 14 ..
968 TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
969 TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
970 TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured
971 TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
972 TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
973 TpProcMemReceiverEnableTraining, ///< 1A ..
974 TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
975 TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
976 TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
977 TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
978 TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
979 TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
980 TpProcMemReceiveDqsTraining, ///< 21 ..
981 TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
982 TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
983 TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
984 TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
985 TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
986 TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
987 TpProcMemRcvDqsResults, ///< 28 .. Update results
988 TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
989 TpProcMemTransmitDqsTraining, ///< 2A ..
990 TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
991 TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
992 TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
993 TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
994 TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
995 TpProcMemTxDqResults, ///< 30 .. Update results
996 TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
997 TpProcMemMaxRdLatencyTraining, ///< 32 ..
998 TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
999 TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
1000 TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
1001 TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
1002 TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
1003 TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
1004 TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
1005 TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
1006 TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
1007 TpProcMemEccInitialization, ///< 3C .. ECC initialization
1008 TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
1009 TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
1010 TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
1011 TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
1012 TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
1013 TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
1014 TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
1015 TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
1016 TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
1017 TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
1018 TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
1019 TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
1020 TpProcMemInitMCT, ///< 49 .. Before InitMCT
1021 TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
1022 TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
1023 TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
1024 TpProcMemMemClr, ///< 4D .. Before MemClr
1025 TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
1026 TpProcMemDmi, ///< 4F .. Before DMI
1027 TpProcMemEnd, ///< 50 .. End of memory code
1028
1029 // CPU test points
1030 TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
1031 TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
1032 TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
1033 TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
1034 TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
1035 TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
1036 TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
1037 TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
1038 TpProcCpuSetBrandID, ///< 59 .. Set brand ID
1039 TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
1040 TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
1041 TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
1042 TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
1043 TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
1044 TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
1045 TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
1046 TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
1047 TpProcCpuBeforeRelinquishAPsFeatureInit = 0x63, ///< 63 .. Before Relinquishing control of APs feature dispatch point
1048 TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer
1049 TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer
1050 TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer
1051 TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer
1052 TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer
1053 TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer
1054 TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer
1055 TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer
1056 TpProcCpuEntryCrat, ///< 6C .. Entry point CreateAcpiCrat
1057 TpProcCpuEntryCdit, ///< 6D .. Entry point CreateAcpiCdit
1058 TpProcCpuEntryScs, ///< 6E .. Entry point InitializeScsFeature
1059
1060 // Topology test points
1061 TpProcTopologyEntry = 0x71, ///< 71 .. Topology Init begin
1062 TpProcTopologyDone = 0x7C, ///< 7C .. Topology Init complete
1063
1064 // Extended memory test point
1065 TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2
1066 TpProcMemSendMRS3, ///< 81 .. Sedding MRS3
1067 TpProcMemSendMRS1, ///< 82 .. Sending MRS1
1068 TpProcMemSendMRS0, ///< 83 .. Sending MRS0
1069 TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read
1070 TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write
1071 TpProcMem2dRdDqsTraining, ///< 86 .. Mem: 2d RdDqs Training begin
1072 TpProcMemBefore2dTrainExtVrefChange,///< 87 .. Mem: Before optional callout to platform BIOS to change External Vref during 2d Training
1073 TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platform BIOS to change External Vref during 2d Training
1074 TpProcMemConfigureDCTForGeneral, ///< 89 .. Configure DCT For General use begin
1075 TpProcMemProcConfigureDCTForTraining, ///< 8A .. Configure DCT For training begin
1076 TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit
1077 TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels
1078 TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage
1079
1080 // Gnb Earlier init
1081 TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init
1082 TpGnbEarlierInterface = 0x91, ///< 91 .. GNB earlier interface
1083 // Gnb Early init
1084 TpGnbEarlyInterface = 0x92, ///< 92 .. GNB early interface
1085 TpGnbPcieConfigurationMap, ///< 93 .. GNB early PCIE configuration map
1086 TpGnbPcieEarlyInterface, ///< 94 .. GNB early PCIE interface
1087 //Gnb post init
1088 TpGnbPciePostEarlyInterface = 0x95, ///< 95 .. GNB post early interface
1089 TpGnbGfxConfigPostInterface, ///< 96 .. GNB post GFX config interface
1090 TpGnbGfxPostInterface, ///< 97 .. GNB post GFX interface
1091 // Gnb post after DRAM init
1092 TpGnbPostInterface = 0x98, ///< 98 .. GNB post after DRAM interface
1093 TpGnbPciePostInterface, ///< 99 .. GNB post after DRAM PCIE interface
1094 // Gnb Env init
1095 TpGnbEnvInterface, ///< 9A .. GNB Env Nb interface
1096 TpGnbPcieEnvInterface, ///< 9B .. GNB Env PCIE interface
1097 TpGnbGfxConfigEnvInterface, ///< 9C .. GNB Env GFX Config interface
1098 TpGnbGfxEnvInterface, ///< 9D .. GNB Env GFX interface
1099 // Gnb Mid init
1100 TpGnbGfxConfigMidInterface = 0xA1, ///< A1 .. GNB Mid GFX config interface
1101 TpGnbGfxMidInterface, ///< A2 .. GNB Mid GFX interface
1102 TpPcieMidInterface, ///< A3 .. GNB Mid PCIE interface
1103 TpGnbMidInterface, ///< A4 .. GNB Mid interface
1104 TpNbLclkFeature, ///< A5 .. GNB Mid Nclk feature
1105 TpPciePowerGateFeature, ///< A6 .. GNB Mid pcie power gate feature
1106 TpGnbPcieMaxPayloadInterface, ///< A7 .. GNB Mid pcie max payload interface
1107 TpGnbPcieClkPmInterface, ///< A8 .. GNB Mid pcie clk pm port interface
1108 TpGnbPcieAspmInterface, ///< A9 .. GNB Mid pcie ASPM interface
1109 TpGnbNbIoapicInterface, ///< AA .. GNB Mid IOAPIC interface
1110 // Gnb Late init
1111 TpGnbPcieAlibFeature = 0xAB, ///< AB .. GNB Late pcie ALIB feature
1112 TpGnbIommuIvrsTable, ///< AC .. GNB Late pcie IOMMU
1113 // Gnb S3 Save
1114 TpGnbGfxInitSview = 0xAD, ///< AD .. GNB S3SAVE GFX sview init
1115 TpGnbAlibDispatchFeature = 0xAE, ///< AE .. GNB ALIB dispatch feature
1116 EndGnbTestPoints = 0xAF, ///< AF End of TP range for GNB
1117
1118 StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs
1119 TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point
1120 TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training
1121 TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed
1122 TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed
1123 TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training
1124 TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point
1125 TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point
1126 TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point
1127 TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event
1128 TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event
1129 TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point
1130 TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point
1131 EndFchTestPoints, ///< BF End of TP range for FCH
1132
1133 // Interface test points
1134 TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
1135 TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
1136 TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
1137 TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
1138 TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
1139 TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
1140 TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
1141 TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
1142 TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
1143 TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
1144 TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
1145 TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
1146 TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
1147 TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
1148 TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
1149 TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
1150 TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
1151 TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
1152 TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
1153 TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
1154 TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
1155 TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
1156 TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
1157 TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
1158 TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
1159 TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
1160 TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
1161 TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
1162 TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
1163 TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
1164 TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
1165 TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
1166 TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
1167 TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
1168 TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
1169 TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
1170 TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
1171 TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
1172 TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
1173 TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
1174 TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
1175 TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
1176 TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
1177 TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
1178 TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
1179 TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
1180 TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
1181 TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
1182 TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
1183 TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
1184 TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
1185 TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
1186 TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
1187 TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
1188 TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
1189 TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
1190 TpReadyToBoot, ///< F8 .. Ready to boot event
1191 // PMU test points
1192 TpProcMemPmuFailed, ///< F9 .. Failed PMU training.
1193
1194 EndAgesaTps = 0xFF, ///< Last defined AGESA TP
1195} AGESA_TP;
1196
1197///Ids Feat description
1198typedef enum {
1199 IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
1200 IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
1201 IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
1202 IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
1203 IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
1204 IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
1205 IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
1206 IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
1207 IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
1208 IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
1209 IDS_FEAT_HDTOUT, ///< Feat for hdt out
1210 IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
1211 IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
1212 IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
1213 IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
1214 IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
1215 IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS
1216 IDS_FEAT_COMMON, ///< Common Feat
1217 IDS_FEAT_END = 0xFF ///< End of Common feat
1218} IDS_FEAT;
1219
1220///Ids IDT table function ID
1221typedef enum {
1222 IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC
1223 IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC
1224 IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector
1225} IDS_IDT_FUNC_ID;
1226
1227typedef IDS_STATUS IDS_COMMON_FUNC (
1228 IN OUT VOID *DataPtr,
1229 IN OUT AMD_CONFIG_PARAMS *StdHeader,
1230 IN IDS_NV_ITEM *IdsNvPtr
1231 );
1232
1233typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
1234
1235/// Data Structure of IDS Feature block
1236typedef struct _IDS_FAMILY_FEAT_STRUCT {
1237 IDS_FEAT IdsFeat; ///< Ids Feat ID
1238 BOOLEAN IsBsp; ///< swith for Bsp check
1239 AGESA_IDS_OPTION IdsOption; ///< IDS option
1240 UINT64 CpuFamily; ///<
1241 PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
1242} IDS_FAMILY_FEAT_STRUCT;
1243
1244
1245/// Data Structure of IDS option
1246typedef struct _IDS_OPTION_STRUCT {
1247 AGESA_IDS_OPTION idsoption; ///< IDS option
1248 PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
1249} IDS_OPTION_STRUCT;
1250
1251/// Data Structure of IDS option table
1252typedef struct _IDS_OPTION_STRUCT_TBL {
1253 UINT8 version; ///<Version of IDS option table
1254 UINT16 size; ///<Size of IDS option table
1255 CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
1256} IDS_OPTION_STRUCT_TBL;
1257
1258#define IDS_NV_TO_CMOS_LEN_BYTE 1
1259#define IDS_NV_TO_CMOS_LEN_WORD 2
1260#define IDS_NV_TO_CMOS_LEN_END 0xFF
1261#define IDS_NV_TO_CMOS_ID_END 0xFFFF
1262
1263/// Data struct of set/get NV to/from CMOS
1264typedef struct _IDS_NV_TO_CMOS {
1265 UINT8 Length; ///< Length of NV
1266 UINT16 IDS_NV_ID; ///< IDS id
1267} IDS_NV_TO_CMOS;
1268
1269IDS_STATUS
1270AmdIdsCtrlDispatcher (
1271 IN AGESA_IDS_OPTION IdsOption,
1272 IN OUT VOID *DataPtr,
1273 IN OUT AMD_CONFIG_PARAMS *StdHeader
1274 );
1275
1276AGESA_STATUS
1277IdsOptionCallout (
1278 IN UINTN CallOutId,
1279 IN OUT VOID *DataPtr,
1280 IN OUT AMD_CONFIG_PARAMS *StdHeader
1281 );
1282
1283VOID
1284AmdIdsHdtOutInit (
1285 IN OUT AMD_CONFIG_PARAMS *StdHeader
1286 );
1287
1288VOID
1289AmdIdsHdtOutExit (
1290 IN OUT AMD_CONFIG_PARAMS *StdHeader
1291 );
1292
1293VOID
1294AmdIdsHdtOutS3Exit (
1295 IN OUT AMD_CONFIG_PARAMS *StdHeader
1296 );
1297
1298VOID
1299AmdIdsHdtOutS3ApExit (
1300 IN OUT AMD_CONFIG_PARAMS *StdHeader
1301 );
1302
1303VOID
1304AmdIdsDebugPrint (
1305 IN UINT64 Flag,
1306 IN const CHAR8 *Format,
1307 IN ...
1308 );
1309
1310VOID
1311AmdIdsDebugPrintTopology (
1312 IN CHAR8 *Format,
1313 IN ...
1314 );
1315
1316VOID
1317AmdIdsDebugPrintCpu (
1318 IN CHAR8 *Format,
1319 IN ...
1320 );
1321
1322VOID
1323AmdIdsDebugPrintMem (
1324 IN CHAR8 *Format,
1325 IN ...
1326 );
1327
1328VOID
1329AmdIdsDebugPrintGnb (
1330 IN CHAR8 *Format,
1331 IN ...
1332 );
1333
1334VOID
1335AmdIdsDebugPrintAll (
1336 IN CHAR8 *Format,
1337 IN ...
1338 );
1339
1340VOID
1341AmdIdsHdtOutBufferFlush (
1342 IN OUT AMD_CONFIG_PARAMS *StdHeader
1343 );
1344
1345VOID
1346IdsMemTimeOut (
1347 IN OUT VOID *DataPtr
1348 );
1349
1350VOID
1351IdsAgesaTestPoint (
1352 IN AGESA_TP TestPoint,
1353 IN OUT AMD_CONFIG_PARAMS *StdHeader
1354 );
1355
1356/**
1357 * IDS Backend Function for ASSERT
1358 *
1359 * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
1360 * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
1361 * to help distinguish the stop code from a post code loop.
1362 * Additional features may be available if using simulation.
1363 *
1364 * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
1365 *
1366 * @retval TRUE No error
1367**/
1368BOOLEAN
1369IdsAssert (
1370 IN UINT32 FileCode
1371 );
1372
1373/**
1374 * The engine code for ASSERT MACRO
1375 *
1376 * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
1377 * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
1378 * to help distinguish the stop code from a post code loop.
1379 * Additional features may be available if using simulation.
1380 *
1381 * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
1382 *
1383 */
1384BOOLEAN
1385IdsErrorStop (
1386 IN UINT32 FileCode
1387 );
1388
1389VOID
1390IdsDelay (
1391 IN VOID
1392 );
1393
1394BOOLEAN
1395AmdHeapIntactCheck (
1396 IN AMD_CONFIG_PARAMS *StdHeader
1397 );
1398
1399VOID
1400IdsCarCorruptionCheck (
1401 IN OUT AMD_CONFIG_PARAMS *StdHeader
1402 );
1403
1404IDS_STATUS
1405IdsExceptionTrap (
1406 IN IDS_IDT_FUNC_ID IdsIdtFuncId,
1407 IN VOID *DataPtr,
1408 IN OUT AMD_CONFIG_PARAMS *StdHeader
1409 );
1410
1411AGESA_STATUS
1412IdsPerfTimestamp (
1413 IN UINT32 LineInFile,
1414 IN UINT32 Description,
1415 IN OUT AMD_CONFIG_PARAMS *StdHeader
1416 );
1417
1418AGESA_STATUS
1419IdsPerfAnalyseTimestamp (
1420 IN OUT AMD_CONFIG_PARAMS *StdHeader
1421 );
1422
1423
1424#if IDSOPT_IDS_ENABLED == FALSE
1425 #undef IEM_SKIP_CODE
1426 #undef IEM_INSERT_CODE
1427#endif
1428#ifndef IEM_SKIP_CODE
1429 #define IEM_SKIP_CODE(L)
1430#endif
1431#ifndef IEM_INSERT_CODE
1432 #define IEM_INSERT_CODE(L, Fn, Parm)
1433#endif
1434
1435#endif // _IDS_H_