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review.coreboot.org / coreboot / 7687e7767f2d2321b57fa8eab68b7e954e57ad42 / . / src / vendorcode / amd / pi / 00670F00 / Proc / Fch / Fch.h
blob: 604f4d8adcf2e5d5e89338c808e94eb28a1c24fe [file] [log] [blame]
Martin Roth7687e772023-08-22 16:32:20 -0600[diff] [blame^]1/* SPDX-License-Identifier: BSD-3-Clause */
2
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]3/* $NoKeywords:$ */
4/**
5 * @file
6 *
7 * FCH registers definition
8 *
9 *
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: FCH
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]14 * @e \$Revision$ @e \$Date$
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]15 *
16 */
17 /*****************************************************************************
18 *
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]19 * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *
44 ***************************************************************************/
Martin Rothae016342017-11-16 22:46:56 -0700[diff] [blame]45
46#include <check_for_wrapper.h>
47
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]48#define FCH_REVISION "0.0.5.0"
49#define FCH_ID "FCH_A05"
50#define FCH_VERSION 0x0000
51
52/**
53 * @page fchinitguide FCH implement phase in AGESA
54 *
55 * FCH provides below access to supported FCH service functions
56 * and data.
57 * - @subpage fchreset "FCH_INIT_RESET"
58 * - @subpage fchenv "FCH_INIT_ENV"
59 * - @subpage fchmid "FCH_INIT_MID"
60 * - @subpage fchlate "FCH_INIT_LATE"
61 * - @subpage fchs3early "FCH_INIT_S3_EARLY_RESTORE"
62 * - @subpage fchs3late "FCH_INIT_S3_LATE_RESTORE"
63 * - @subpage fchsmm "FCH_SMM_SERVICE"
64 * - @subpage fchsmmacpion "FCH_SMM_ACPION"
65 */
66
67/*--------------------------- Documentation Pages ---------------------------*/
68/**
69 * @page fchreset FCH_INIT_RESET
70 * @section FCH_INIT_RESET Interface Call
71 * @par
72 * Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value.
73 * @subsection FCH_INIT_RESET_CallIn Call Prototype
74 * @par
75 * AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams);
76 * @subsection FCH_INIT_RESET_CallOut Prepare for Callout
77 * @par
78 * Not Applicable (Not necessary for the current implementation)
79 * @subsection FCH_INIT_RESET_Config Prepare for Configuration Data.
80 * @par
81 * <TABLE border="0">
82 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
83 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
84 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
85 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
86 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
87 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
88 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
89 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
90 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
91 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
92 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
93 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
94 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
95 * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
96 * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
97 * </TABLE>
98 *
99 */
100
101/*--------------------------- Documentation Pages ---------------------------*/
102/**
103 * @page fchenv FCH_INIT_ENV
104 * @section FCH_INIT_ENV Interface Call
105 * @par
106 * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
107 * @subsection FCH_INIT_ENV_CallIn Call Prototype
108 * @par
109 * AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams);
110 * @subsection FCH_INIT_ENV_CallOut Prepare for Callout
111 * @par
112 * Not Applicable (Not necessary for the current implementation)
113 * @subsection FCH_INIT_ENV_Config Prepare for Configuration Data.
114 * @par
115 * <TABLE border="0">
116 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
117 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
118 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
119 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
120 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
121 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
122 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
123 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
124 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
125 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
126 * </TABLE>
127 *
128 */
129
130/*--------------------------- Documentation Pages ---------------------------*/
131/**
132 * @page fchmid FCH_INIT_MID
133 * @section FCH_INIT_MID Interface Call
134 * @par
135 * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
136 * @subsection FCH_INIT_MID_CallIn Call Prototype
137 * @par
138 * AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams);
139 * @subsection FCH_INIT_MID_CallOut Prepare for Callout
140 * @par
141 * Not Applicable (Not necessary for the current implementation)
142 * @subsection FCH_INIT_MID_Config Prepare for Configuration Data.
143 * @par
144 * <TABLE border="0">
145 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
146 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
147 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
148 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
149 * </TABLE>
150 *
151 */
152
153/*--------------------------- Documentation Pages ---------------------------*/
154/**
155 * @page fchlate FCH_INIT_LATE
156 * @section FCH_INIT_LATE Interface Call
157 * @par
158 * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
159 * @subsection FCH_INIT_LATE_CallIn Call Prototype
160 * @par
161 * AGESA_STATUS FchInitLate (IN FCH_DATA_BLOCK *LateParams);
162 * @subsection FCH_INIT_LATE_CallOut Prepare for Callout
163 * @par
164 * Not Applicable (Not necessary for the current implementation)
165 * @subsection FCH_INIT_LATE_Config Prepare for Configuration Data.
166 * @par
167 * <TABLE border="0">
168 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
169 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
170 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
171 * </TABLE>
172 *
173 */
174
175/*--------------------------- Documentation Pages ---------------------------*/
176/**
177 * @page fchs3early FCH_INIT_S3_EARLY_RESTORE
178 * @section FCH_INIT_S3_EARLY_RESTORE Interface Call
179 * @par
180 * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
181 * @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype
182 * @par
183 * VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
184 * @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout
185 * @par
186 * Not Applicable (Not necessary for the current implementation)
187 * @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data.
188 * @par
189 * <TABLE border="0">
190 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
191 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
192 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
193 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
194 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
195 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
196 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
197 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
198 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
199 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
200 * </TABLE>
201 *
202 */
203
204/*--------------------------- Documentation Pages ---------------------------*/
205/**
206 * @page fchs3late FCH_INIT_S3_LATE_RESTORE
207 * @section FCH_INIT_S3_LATE_RESTORE Interface Call
208 * @par
209 * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
210 * @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype
211 * @par
212 * VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
213 * @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout
214 * @par
215 * Not Applicable (Not necessary for the current implementation)
216 * @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data.
217 * @par
218 * <TABLE border="0">
219 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
220 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
221 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
222 * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
223 * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
224 * </TABLE>
225 *
226 */
227
228/*--------------------------- Documentation Pages ---------------------------*/
229/**
230 * @page fchsmm FCH_SMM_SERVICE
231 * @section FCH_SMM_SERVICE Interface Call
232 * Initialize structure referenced by FCHCFG to default recommended value.
233 * @subsection FCH_SMM_SERVICE_CallIn Call Prototype
234 * @par
235 * FchSmmService ((FCHCFG*)pConfig) (Followed PH Interface)
236 * @subsection FCH_SMM_SERVICE_CallID Service ID
237 * @par
238 * <TABLE border="0">
239 * <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE --> 0x00010060 </TD></TR>
240 * </TABLE>
241 * @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout
242 * @par
243 * Not Applicable (Not necessary for the current implementation)
244 * @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data.
245 * @par
246 * Not necessary on current implementation
247 *
248 */
249#define FCH_SMM_SERVICE 0x00010060ul
250/*--------------------------- Documentation Pages ---------------------------*/
251/**
252 * @page fchsmmacpion FCH_SMM_ACPION
253 * @section FCH_SMM_ACPION Interface Call
254 * Initialize structure referenced by FCHCFG to default recommended value.
255 * @subsection FCH_SMM_ACPION_CallIn Call Prototype
256 * @par
257 * FchSmmAcpiOn ((FCHCFG*)pConfig) (Followed PH Interface)
258 * @subsection FCH_SMM_ACPION_CallID Service ID
259 * @par
260 * <TABLE border="0">
261 * <TR><TD class="indexkey" width=380> FCH_SMM_ACPION --> 0x00010061 </TD></TR>
262 * </TABLE>
263 * @subsection FCH_SMM_ACPION_CallOut Prepare for Callout
264 * @par
265 * Not Applicable (Not necessary for the current implementation)
266 * @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data.
267 * @par
268 * Not necessary on current implementation
269 *
270 */
271#define FCH_SMM_ACPION 0x00010061ul
272
273#ifndef OEM_CALLBACK_BASE
274 #define OEM_CALLBACK_BASE 0x00010100ul
275#endif
276
277//0x00 - 0x0F callback functions are reserved for bootblock
278#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10
279#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20
280/*--------------------------- Documentation Pages ---------------------------*/
281/**
282 * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
283 * @section CB_SBGPP_RESET_ASSERT Interface Call
284 * Initialize structure referenced by FCHCFG to default recommended value.
285 * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
286 * @par
287 * <TABLE border="0">
288 * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR>
289 * </TABLE>
290 * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
291 * @par
292 * Not necessary on current implementation
293 *
294 */
295#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30
296/*--------------------------- Documentation Pages ---------------------------*/
297/**
298 * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
299 * @section CB_SBGPP_RESET_DEASSERT Interface Call
300 * Initialize structure referenced by FCHCFG to default recommended value.
301 * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
302 * @par
303 * <TABLE border="0">
304 * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR>
305 * </TABLE>
306 * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
307 * @par
308 * Not necessary on current implementation
309 *
310 */
311#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31
312
313#define CFG_ADDR_PORT 0xCF8
314#define CFG_DATA_PORT 0xCFC
315
316#define ALINK_ACCESS_INDEX 0x0CD8
317#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4
318
319/*------------------------------------------------------------------
320; I/O Base Address - Should be set by host BIOS
321;------------------------------------------------------------------ */
322#define DELAY_PORT 0x0E0
323
324#define FCH_8259_CONTROL_REG_MASTER 0x20
325#define FCH_8259_MASK_REG_MASTER 0x21
326
327/*------------------------------------------------------------------
328; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
329;------------------------------------------------------------------ */
330// ASIC VendorID and DeviceIDs
331#define ATI_VID 0x1002
332#define AMD_FCH_VID 0x1022
333#define FCH_DEVICE_ID 0x780B
334#define FCH_SATA_VID AMD_FCH_VID // Dev 17 Func 0
335#define FCH_SATA_DID 0x7800
336#define FCH_SATA_AHCI_DID 0x7801
337#define FCH_SATA_RAID_DID 0x7802
338#define FCH_SATA_RAID5_DID 0x7803
339#define FCH_SATA_AMDAHCI_DID 0x7804
340#define FCH_SATA_RAID_DOTHILL_DID 0x7805
341#define FCH_SATA_RAID5_DOTHILL_DID 0x780A
342#define FCH_USB_OHCI_VID AMD_FCH_VID // Dev 18 Func 0, Dev 19 Func 0
343#define FCH_USB_OHCI_DID 0x7807
344#define FCH_USB_EHCI_VID AMD_FCH_VID // Dev 18 Func 2, Dev 19 Func 2
345#define FCH_USB_EHCI_DID 0x7808
346#define FCH_USB_XHCI_VID AMD_FCH_VID // Dev 10 Func 0, Dev 10 Func 1
347#define FCH_USB_XHCI_DID 0x7812
348#define FCH_USB_XHCI_DID_BOLTON 0x7814
349#define FCH_USB_XHCI_DID_KABINI 0x7814
350#define FCH_SMBUS_VID AMD_FCH_VID // Dev 20 Func 0
351#define FCH_SMBUS_DID 0x780B
352#define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1
353#define FCH_IDE_DID 0x780C
354#define FCH_AZALIA_VID AMD_FCH_VID // Dev 20 Func 2
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]355#define FCH_AZALIA_DID 0x780D
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]356#define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3
357#define FCH_LPC_DID 0x780E
358#define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4
359#define FCH_PCIB_DID 0x780F
360#define FCH_USB_OHCIF_VID AMD_FCH_VID // dev 20 Func 5
361#define FCH_USB_OHCIF_DID 0x7809
362#define FCH_NIC_VID 0x14E4 // Dev 20 Func 6
363#define FCH_NIC_DID 0x1699
364#define FCH_SD_VID AMD_FCH_VID // Dev 20 Func 7
365#define FCH_SD_DID 0x7806
366
367//FCH Variant
368#define FCH_Variant_EFUSE_LOCATION 0x1E // EFUSE bit 240-247
369
370#define FCH_M2 0x01
371#define FCH_M3 0x03
372#define FCH_M3T 0x07
373#define FCH_D2 0x0F
374#define FCH_D3 0x1F
375#define FCH_D4 0x3F
376#define FCH_BOLTON 0x15
377#define FCH_YANGTZE 0x39
378#define FCH_YANGTZEA1 0x3A
379#define FCH_AVALONA0 0x41
380#define FCH_AVALONA1 0x42
381//Misc
382#define R_FCH_ACPI_PM1_STATUS 0x00
383#define R_FCH_ACPI_PM1_ENABLE 0x02
384#define R_FCH_ACPI_PM_CONTROL 0x04
385#define R_FCH_ACPI_EVENT_STATUS 0x20
386#define R_FCH_ACPI_EVENT_ENABLE 0x24
387#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO 0x2C
388
389// ACPI Sleep Type
390#define ACPI_SLPTYP_S0 0
391#define ACPI_SLPTYP_S1 1
392#define ACPI_SLPTYP_S3 3
393#define ACPI_SLPTYP_S4 4
394#define ACPI_SLPTYP_S5 5
395
396//#define SATA_BUS_DEV_FUN_FPGA 0x228
397#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)
398#define FCH_SATA1_BUS 0
399#define FCH_SATA1_DEV 17
400#define FCH_SATA1_FUNC 0
401
402#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)
403#define FCH_XHCI_BUS 0
404#define FCH_XHCI_DEV 16
405#define FCH_XHCI_FUNC 0
406#define USB_XHCI_BUS_DEV_FUN ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC)
407#define FCH_XHCI1_BUS 0
408#define FCH_XHCI1_DEV 16
409#define FCH_XHCI1_FUNC 1
410#define USB_XHCI1_BUS_DEV_FUN ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC)
411#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4
412#define FCH_OHCI1_BUS 0
413#define FCH_OHCI1_DEV 18
414#define FCH_OHCI1_FUNC 0
415#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9
416#define FCH_OHCI2_BUS 0
417#define FCH_OHCI2_DEV 19
418#define FCH_OHCI2_FUNC 0
419#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13
420#define FCH_OHCI3_BUS 0
421#define FCH_OHCI3_DEV 22
422#define FCH_OHCI3_FUNC 0
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]423#define EHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-3
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]424#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4
425#define FCH_EHCI1_BUS 0
426#define FCH_EHCI1_DEV 18
427#define FCH_EHCI1_FUNC 2
428#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9
429#define FCH_EHCI2_BUS 0
430#define FCH_EHCI2_DEV 19
431#define FCH_EHCI2_FUNC 2
432#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13
433#define FCH_EHCI3_BUS 0
434#define FCH_EHCI3_DEV 22
435#define FCH_EHCI3_FUNC 2
436#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)
437#define FCH_ISA_BUS 0
438#define FCH_ISA_DEV 20
439#define FCH_ISA_FUNC 0
440#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)
441#define FCH_IDE_BUS 0
442#define FCH_IDE_DEV 20
443#define FCH_IDE_FUNC 1
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]444#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2)
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]445#define FCH_AZALIA_BUS 0
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]446#define FCH_AZALIA_DEV 20
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]447#define FCH_AZALIA_FUNC 2
448#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)
449#define FCH_LPC_BUS 0
450#define FCH_LPC_DEV 20
451#define FCH_LPC_FUNC 3
452#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700
453#define FCH_PCI_BUS 0
454#define FCH_PCI_DEV 20
455#define FCH_PCI_FUNC 4
456#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1
457#define FCH_OHCI4_BUS 0
458#define FCH_OHCI4_DEV 20
459#define FCH_OHCI4_FUNC 5
460//Gigabyte Ethernet Controller
461#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6)
462#define FCH_GBEC_BUS 0
463#define FCH_GBEC_DEV 20
464#define FCH_GBEC_FUNC 6
465
466#define SD_BUS_DEV_FUN ((0x14 << 3) + 7) // SD Controller
467#define SD_PCI_BUS 0
468#define SD_PCI_DEV 20
469#define SD_PCI_FUNC 7
470
471
472#define FCH_GPP_BUS 0
473#define FCH_GPP_DEV 21
474#define FCH_GPP_FUNC 0
475#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0
476#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1
477#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2
478#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3
479
480#define ACPI_MMIO_BASE 0xFED80000ul
481#define FCH_CFG_BASE 0x000 // DWORD
482#define GPIO_BASE 0x100 // BYTE
483#define SMI_BASE 0x200 // DWORD
484#define PMIO_BASE 0x300 // DWORD
485#define PMIO2_BASE 0x400 // BYTE
486#define BIOS_RAM_BASE 0x500 // BYTE
487#define CMOS_RAM_BASE 0x600 // BYTE
488#define CMOS_BASE 0x700 // BYTE
489#define ASF_BASE 0x900 // DWORD
490#define SMBUS_BASE 0xA00 // DWORD
491#define WATCHDOG_BASE 0xB00 //
492#define HPET_BASE 0xC00 // DWORD
493#define IOMUX_BASE 0xD00 // BYTE
494#define MISC_BASE 0xE00
495#define SERIAL_DEBUG_BASE 0x1000
496#define GFX_DAC_BASE 0x1400
497#define GPIO_BANK0_BASE 0x1500 // DWORD
498//#define GPIO_BANK1_BASE 0x1600 // DWORD
499//#define GPIO_BANK2_BASE 0x1700 // DWORD
500#define CEC_BASE 0x1800
501#define XHCI_BASE 0x1C00
502#define ACDC_BASE 0x1D00
503#define AOAC_BASE 0x1E00
504
505
506// Chip type definition
507#define CHIPTYPE_HUDSON2 (1 << 0)
508#define CHIPTYPE_YUBA (1 << 1)
509
510//
511// ROM SIG type definition
512//
513#define NUM_OF_ROMSIG_FILED 0x04
514#define XHCI_FILED_NUM 0x03
515#define ROMSIG_CFG_MASK 0x07
516#define XHCI_BOOT_RAM_OFFSET 0x8000
517#define INSTRUCTION_RAM_SIG 0x55AA
518#define ROMSIG_SIG 0x55AA55AAul
519
520// RegSpace field (AB_INDEX[31:29]
521#define AXINDC 0 // AXINDC
522#define AXINDP 2 // AXINDP
523#define ABCFG 6 // ABCFG
524#define AXCFG 4 // AXCFG
525#define RCINDXC 1 // PCIEIND
526#define RCINDXP 3 // PCIEIND_P
527
528#define GPP_DEV_NUM 21 //
529#define MAX_GPP_PORTS 4
530
531#define PCIE_FORCE_GEN1_EFUSE_LOCATION 0x14 // EFUSE bit 160
532//
533// ABCFG Registers
534//
535#define FCH_ABCFG_REG00 0x00 // VENDOR ID
536#define FCH_ABCFG_REG08 0x08 // REVISION ID
537#define FCH_ABCFG_REG40 0x40 // BL_EVENTCNT0LO
538#define FCH_ABCFG_REG44 0x44 // BL_EVENTCNT1LO
539#define FCH_ABCFG_REG48 0x48 // BL_EVENTCNTSEL
540#define FCH_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI
541#define FCH_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI
542#define FCH_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL
543#define FCH_ABCFG_REG50 0x50 // MISCCTL_50
544#define FCH_ABCFG_REG54 0x54 // MISCCTL_54
545#define FCH_ABCFG_REG58 0x58 // BL RAB CONTROL
546
547#define FCH_ABCFG_REG60 0x60 // LINKWIDTH_CTL
548#define FCH_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL
549#define FCH_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL
550#define FCH_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS
551#define FCH_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS
552#define FCH_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE
553#define FCH_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE
554
555#define FCH_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL
556#define FCH_ABCFG_REG88 0x88 //
557#define FCH_ABCFG_REG8C 0x8C //
558#define FCH_ABCFG_REG90 0x90 // BIF CONTROL 0
559#define FCH_ABCFG_REG94 0x94 // MSI CONTROL
560#define FCH_ABCFG_REG98 0x98 // BIF CONTROL 1
561#define FCH_ABCFG_REG9C 0x9C // MISCCTL_9C
562#define FCH_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE
563#define FCH_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4
564#define FCH_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8
565#define FCH_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING
566#define FCH_ABCFG_REGB8 0xB8 //
567#define FCH_ABCFG_REGB4 0xB4 //
568#define FCH_ABCFG_REGBC 0xBC //
569#define FCH_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE
570#define FCH_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP
571#define FCH_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA
572#define FCH_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL
573#define FCH_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA
574#define FCH_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS
575#define FCH_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL
576#define FCH_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL
577#define FCH_ABCFG_REGF4 0xF4 // GPP_SYSTEM_ERROR_CONTROL
578#define FCH_ABCFG_REGFC 0xFC // FCH_TRAP_CONTROL
579#define FCH_ABCFG_REG100 0x100 // FCH_TRAP0_ADDRL
580#define FCH_ABCFG_REG104 0x104 // FCH_TRAP0_ADDRH
581#define FCH_ABCFG_REG108 0x108 // FCH_TRAP0_CMD
582#define FCH_ABCFG_REG10C 0x10C // FCH_TRAP1_DATA
583#define FCH_ABCFG_REG110 0x110 // FCH_TRAP1_ADDRL
584#define FCH_ABCFG_REG114 0x114 // FCH_TRAP1_ADDRH
585#define FCH_ABCFG_REG118 0x118 // FCH_TRAP1_CMD
586#define FCH_ABCFG_REG11C 0x11C // FCH_TRAP1_DATA
587#define FCH_ABCFG_REG120 0x120 // FCH_TRAP2_ADDRL
588#define FCH_ABCFG_REG124 0x124 // FCH_TRAP2_ADDRH
589#define FCH_ABCFG_REG128 0x128 // FCH_TRAP2_CMD
590#define FCH_ABCFG_REG12C 0x12C // FCH_TRAP2_DATA
591#define FCH_ABCFG_REG130 0x130 // FCH_TRAP3_ADDRL
592#define FCH_ABCFG_REG134 0x134 // FCH_TRAP3_ADDRH
593#define FCH_ABCFG_REG138 0x138 // FCH_TRAP3_CMD
594#define FCH_ABCFG_REG13C 0x13C // FCH_TRAP3_DATA
595#define FCH_ABCFG_REG180 0x180 // FCH_DMA_TRAFFIC_CONTROL
596#define FCH_ABCFG_REG184 0x184 // FCH_AXI_DMA_MEMORY_POWER_SAVING
597#define FCH_ABCFG_REG208 0x208 // SBG_MISC
598#define FCH_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL
599#define FCH_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0
600#define FCH_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1
601#define FCH_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
602#define FCH_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
603#define FCH_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
604#define FCH_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
605#define FCH_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
606#define FCH_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0
607#define FCH_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1
608#define FCH_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2
609#define FCH_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A
610#define FCH_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B
611#define FCH_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C
612#define FCH_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D
613#define FCH_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
614#define FCH_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
615#define FCH_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND
616#define FCH_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER
617#define FCH_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE
618#define FCH_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
619#define FCH_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
620#define FCH_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
621#define FCH_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
622#define FCH_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
623#define FCH_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL
624#define FCH_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND
625#define FCH_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER
626#define FCH_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE
627#define FCH_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
628#define FCH_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
629#define FCH_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
630#define FCH_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
631#define FCH_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
632#define FCH_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL
633#define FCH_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND
634#define FCH_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER
635#define FCH_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE
636#define FCH_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
637#define FCH_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
638#define FCH_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
639#define FCH_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
640#define FCH_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
641#define FCH_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
642#define FCH_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND
643#define FCH_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER
644#define FCH_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
645#define FCH_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
646#define FCH_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
647#define FCH_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
648#define FCH_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
649#define FCH_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
650#define FCH_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
651#define FCH_ABCFG_REG10040 0x10040ul // AL_EVENTCNT0LO
652#define FCH_ABCFG_REG10044 0x10044ul // AL_EVENTCNT1LO
653#define FCH_ABCFG_REG10048 0x10048ul // AL_EVENTCNTSEL
654#define FCH_ABCFG_REG1004A 0x1004Aul // AL_EVENTCNT0HI
655#define FCH_ABCFG_REG1004B 0x1004Bul // AL_EVENTCNT1HI
656#define FCH_ABCFG_REG1004C 0x1004Cul // AL_EVENTCNTCTL
657#define FCH_ABCFG_REG10050 0x10050ul // MISCCTL_10050
658#define FCH_ABCFG_REG10054 0x10054ul // AL_ARB_CTL
659#define FCH_ABCFG_REG10056 0x10056ul // AL_CLK_CTL
660#define FCH_ABCFG_REG10058 0x10058ul // AL RAB CONTROL
661#define FCH_ABCFG_REG1005C 0x1005Cul // AL MLT CONTROL
662#define FCH_ABCFG_REG10060 0x10060ul // AL DMA PREFETCH ENABLE
663#define FCH_ABCFG_REG10064 0x10064ul // AL DMA PREFETCH FLUSH CONTROL
664#define FCH_ABCFG_REG10068 0x10068ul // AL PREFETCH LIMIT
665#define FCH_ABCFG_REG1006C 0x1006Cul // AL DMA PREFETCH CONTROL
666#define FCH_ABCFG_REG10070 0x10070ul // MISCCTL_10070
667#define FCH_ABCFG_REG10080 0x10080ul // CLKMUXSTATUS
668#define FCH_ABCFG_REG10090 0x10090ul // BIF CONTROL 0
669#define FCH_ABCFG_REG1009C 0x1009Cul // MISCCTL_1009C
670
671//
672// RCINDX_P Registers
673//
674#define FCH_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH
675#define FCH_RCINDXP_REG02 0x02 | RCINDXP << 29 //
676#define FCH_RCINDXP_REG10 0x10 | RCINDXP << 29 //
677#define FCH_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL
678#define FCH_RCINDXP_REG21 0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
679#define FCH_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
680#define FCH_RCINDXP_REG6A 0x6A | RCINDXP << 29 //
681#define FCH_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL
682#define FCH_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
683#define FCH_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
684#define FCH_RCINDXP_REGA2 0xA2 | RCINDXP << 29 //
685#define FCH_RCINDXP_REGA4 0xA4 | RCINDXP << 29 //
686#define FCH_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
687#define FCH_RCINDXP_REGC0 0xC0 | RCINDXP << 29 //
688
689//
690// RCINDX_C Registers
691//
692#define FCH_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG
693#define FCH_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL
694#define FCH_RCINDXC_REG40 0x40 | RCINDXC << 29 // PCIE_P_CNTL
695#define FCH_RCINDXC_REG65 0x65 | RCINDXC << 29 // PCIE_P_PAD_FORCE_DIS
696#define FCH_RCINDXC_REGC0 0xC0 | RCINDXC << 29 // PCIE_STRAP_MISC
697#define FCH_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // PCIE_STRAP_MISC2
698
699
700//
701// AXINDC Registers
702//
703#define FCH_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG
704#define FCH_AX_INDXC_REG10 0x10
705#define FCH_AX_INDXC_REG30 0x30
706#define FCH_AX_DATAC_REG34 0x34
707#define FCH_AX_INDXP_REG38 0x38
708#define FCH_AX_DATAP_REG3C 0x3C
709#define FCH_AX_INDXC_REG40 0x40 | AXINDC << 29
710#define FCH_AX_INDXC_REGA4 0xA4 | AXINDC << 29
711
712#define FCH_AX_INDXP_REG02 0x02 | AXINDP << 29
713#define FCH_AX_INDXP_REGA0 0xA0 | AXINDP << 29
714#define FCH_AX_INDXP_REGA4 0xA4 | AXINDP << 29
715#define FCH_AX_INDXP_REGB1 0xB1 | AXINDP << 29
716
717#define FCH_AX_CFG_REG68 0x68 | AXCFG << 29
718#define FCH_AX_CFG_REG88 0x88 | AXCFG << 29
719
720#define FCH_AB_REG04 0x04
721#define FCH_AB_REG40 0x40
722
723//Sata Port Configuration
724#define SIX_PORTS 0
725#define FOUR_PORTS 1
726
727#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133
728#define SATA_DH_EFUSE_LOCATION 0x11 // EFUSE bit 138
729#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169
730#define SATA_EFUSE_BIT 0x20 //
731#define SATA_DH_EFUSE_BIT 0x04 //
732#define FCH_SATA_REG00 0x000 // Vendor ID - R- 16 bits
733#define FCH_SATA_REG02 0x002 // Device ID - RW -16 bits
734#define FCH_SATA_REG04 0x004 // PCI Command - RW - 16 bits
735#define FCH_SATA_REG06 0x006 // PCI Status - RW - 16 bits
736#define FCH_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
737#define FCH_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits
738#define FCH_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits
739#define FCH_SATA_REG0E 0x00E // Header Type - R - 8 bits
740#define FCH_SATA_REG0F 0x00F // BIST - R - 8 bits
741#define FCH_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits
742#define FCH_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits
743#define FCH_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits
744#define FCH_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits
745#define FCH_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits
746#define FCH_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits
747#define FCH_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits
748#define FCH_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits
749#define FCH_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits
750#define FCH_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits
751#define FCH_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits
752#define FCH_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits
753#define FCH_SATA_REG3E 0x03E // Min Grant - R - 8 bits
754#define FCH_SATA_REG3F 0x03F // Max Latency - R - 8 bits
755#define FCH_SATA_REG40 0x040 // Configuration - RW - 32 bits
756#define FCH_SATA_REG44 0x044 // Software Data Register - RW - 32 bits
757#define FCH_SATA_REG48 0x048
758#define FCH_SATA_REG4C 0x04C
759#define FCH_SATA_REG50 0x050 // Message Capability - R - 16 bits
760#define FCH_SATA_REG52 0x052 // Message Control - R/W - 16 bits
761#define FCH_SATA_REG54 0x054 // Message Address - R/W - 32 bits
762#define FCH_SATA_REG58 0x058 // Message Data - R/W - 16 bits
763#define FCH_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits
764#define FCH_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits
765#define FCH_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits
766#define FCH_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits
767#define FCH_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits
768#define FCH_SATA_REG68 0x068 // MSI Program - R/W - 8 bits
769#define FCH_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits
770#define FCH_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits
771#define FCH_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits
772#define FCH_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits
773#define FCH_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits
774#define FCH_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits
775#define FCH_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits
776#define FCH_SATA_REG86 0x086 // PY Global Control
777#define FCH_SATA_REG87 0x087
778#define FCH_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23)
779#define FCH_SATA_REG8A 0x08A
780#define FCH_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23)
781#define FCH_SATA_REG8E 0x08E
782#define FCH_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23)
783#define FCH_SATA_REG92 0x092
784#define FCH_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23)
785#define FCH_SATA_REG96 0x096
786#define FCH_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits
787#define FCH_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits
788#define FCH_SATA_REGA0 0x0A0 //
789#define FCH_SATA_REGA4 0x0A4 //
790#define FCH_SATA_REGA5 0x0A5 //;
791#define FCH_SATA_REGA8 0x0A8 //
792#define FCH_SATA_REGAD 0x0AD //;
793#define FCH_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits
794#define FCH_SATA_REGB5 0x0B5 //;
795#define FCH_SATA_REGBD 0x0BD //;
796#define FCH_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits
797#define FCH_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits
798
799#define FCH_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits
800#define FCH_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits
801#define FCH_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits
802#define FCH_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits
803#define FCH_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits
804#define FCH_SATA_BAR5_REG1C 0x01C
805#define FCH_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits
806#define FCH_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits
807#define FCH_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits
808#define FCH_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits
809#define FCH_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
810#define FCH_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
811#define FCH_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
812#define FCH_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits
813#define FCH_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits
814#define FCH_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits
815#define FCH_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits
816#define FCH_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits
817#define FCH_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits
818#define FCH_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits
819#define FCH_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits
820#define FCH_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits
821#define FCH_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits
822#define FCH_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits
823#define FCH_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits
824#define FCH_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits
825#define FCH_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits
826#define FCH_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits
827#define FCH_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits
828#define FCH_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
829#define FCH_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
830#define FCH_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
831#define FCH_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits
832#define FCH_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits
833#define FCH_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits
834#define FCH_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits
835#define FCH_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits
836#define FCH_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits
837#define FCH_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
838#define FCH_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
839#define FCH_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
840#define FCH_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits
841#define FCH_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits
842#define FCH_SATA_BAR5_REGF8 0x0F8 // PORT Configuration
843#define FCH_SATA_BAR5_REGFC 0x0FC
844#define FCH_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
845#define FCH_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
846#define FCH_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
847#define FCH_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
848#define FCH_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits
849#define FCH_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
850#define FCH_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
851#define FCH_SATA_BAR5_REG120 0x0120 //
852#define FCH_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status
853#define FCH_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control
854#define FCH_SATA_BAR5_REG130 0x0130
855#define FCH_SATA_BAR5_REG1B0 0x01B0
856#define FCH_SATA_BAR5_REG230 0x0230
857#define FCH_SATA_BAR5_REG2B0 0x02B0
858#define FCH_SATA_BAR5_REG330 0x0330
859#define FCH_SATA_BAR5_REG3B0 0x03B0
860#define FCH_SATA_BAR5_REG430 0x0430
861#define FCH_SATA_BAR5_REG4B0 0x04B0
862
863
864// USB ports
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]865#define NUM_USB1_PORTS 4
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]866#define NUM_USB2_PORTS 5
867#define NUM_USB3_PORTS 4
868#define NUM_USB4_PORTS 2
869#define NUM_XHC0_PORTS 2
870#define NUM_XHC1_PORTS 2
871
872
873//
874// USB OHCI Device 0x7807
875// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
876// Device 20 (0x14) Func 5 (FL) 0x7809
877//
878#define FCH_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002ul)
879#define FCH_OHCI_REG04 0x04 // Command - RW
880#define FCH_OHCI_REG06 0x06 // Status - R
881#define FCH_OHCI_REG08 0x08 // Revision ID/Class Code - R
882#define FCH_OHCI_REG0C 0x0C // Miscellaneous - RW
883#define FCH_OHCI_REG10 0x10 // Bar_OCI - RW
884#define FCH_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW
885#define FCH_OHCI_REG34 0x34 // Capability Pointer - R
886#define FCH_OHCI_REG3C 0x3C // Interrupt Line - RW
887#define FCH_OHCI_REG3D 0x3D // Interrupt Line - RW
888#define FCH_OHCI_REG40 0x40 // Config Timers - RW
889#define FCH_OHCI_REG42 0x42 // Port Disable Control - RW (800)
890#define FCH_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800)
891#define FCH_OHCI_REG48 0x48 // Port Force Reset - RW (800)
892#define FCH_OHCI_REG4C 0x4C // MSI - RW (800)
893#define FCH_OHCI_REG50 0x50 // Misc Control - RW
894#define FCH_OHCI_REG51 0x51
895#define FCH_OHCI_REG52 0x52
896#define FCH_OHCI_REG58 0x58 // Over Current Control - RW
897#define FCH_OHCI_REG5C 0x5C // Over Current Control - RW
898#define FCH_OHCI_REG60 0x60 // Serial Bus Release Number - RW
899#define FCH_OHCI_REG68 0x68 // Over Current PME Enable - RW
900#define FCH_OHCI_REG74 0x74 // Target Timeout Control - RW
901#define FCH_OHCI_REG80 0x80 //
902#define FCH_OHCI_REGD0 0x0D0 // MSI Control - RW
903#define FCH_OHCI_REGD4 0x0D4 // MSI Address - RW
904#define FCH_OHCI_REGD8 0x0D8 // MSI Data - RW
905#define FCH_OHCI_REGE4 0x0E4 // HT MSI Support
906#define FCH_OHCI_REGF0 0x0F0 // Function Level Reset Capability
907#define FCH_OHCI_REGF4 0x0F4 // Function Level Reset Control
908
909#define FCH_OHCI_BAR_REG00 0x00 // cRevision - R
910#define FCH_OHCI_BAR_REG04 0x04 // cControl
911#define FCH_OHCI_BAR_REG08 0x08 // cCommandStatus
912#define FCH_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW
913#define FCH_OHCI_BAR_REG10 0x10 // cInterruptEnable
914#define FCH_OHCI_BAR_REG14 0x14 // cInterruptDisable
915#define FCH_OHCI_BAR_REG18 0x18 // HcCCA
916#define FCH_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED
917#define FCH_OHCI_BAR_REG20 0x20 // HcControleadED
918#define FCH_OHCI_BAR_REG24 0x24 // cControlCurrentED RW
919#define FCH_OHCI_BAR_REG28 0x28 // HcBulkeadED
920#define FCH_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW
921#define FCH_OHCI_BAR_REG30 0x30 // HcDoneead
922#define FCH_OHCI_BAR_REG34 0x34 // cFmInterval
923#define FCH_OHCI_BAR_REG38 0x38 // cFmRemaining
924#define FCH_OHCI_BAR_REG3C 0x3C // cFmNumber
925#define FCH_OHCI_BAR_REG40 0x40 // cPeriodicStart
926#define FCH_OHCI_BAR_REG44 0x44 // HcLSThresold
927#define FCH_OHCI_BAR_REG48 0x48 // HcRDescriptorA
928#define FCH_OHCI_BAR_REG4C 0x4C // HcRDescriptorB
929#define FCH_OHCI_BAR_REG50 0x50 // HcRStatus
930#define FCH_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800)
931#define FCH_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800)
932#define FCH_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800)
933
934#define FCH_OHCI_PORTSC_CCS 0x1 // HcRhPortStatus
935#define FCH_OHCI_PORTSC_PES 0x2 // HcRhPortStatus
936#define FCH_OHCI_PORTSC_PSS 0x4 // HcRhPortStatus
937#define FCH_OHCI_PORTSC_PPS 0x100 // HcRhPortStatus
938#define FCH_OHCI_PORTSC_LSDA 0x200 // HcRhPortStatus
939#define FCH_OHCI_PORTSC_PRS 0x10 // HcRhPortStatus
940
941//
942// USB EHCI Device 0x7808
943// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
944//
945#define FCH_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R
946#define FCH_EHCI_REG04 0x04 // Command - RW
947#define FCH_EHCI_REG06 0x06 // Status - R
948#define FCH_EHCI_REG08 0x08 // Revision ID/Class Code - R
949#define FCH_EHCI_REG0C 0x0C // Miscellaneous - RW
950#define FCH_EHCI_REG10 0x10 // BAR - RW
951#define FCH_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW
952#define FCH_EHCI_REG34 0x34 // Capability Pointer - R
953#define FCH_EHCI_REG3C 0x3C // Interrupt Line - RW
954#define FCH_EHCI_REG3D 0x3D // Interrupt Line - RW
955#define FCH_EHCI_REG40 0x40 // Config Timers - RW
956#define FCH_EHCI_REG4C 0x4C // MSI - RW
957#define FCH_EHCI_REG50 0x50 // EHCI Misc Control - RW
958#define FCH_EHCI_REG54 0x54 // EHCI Misc Control - RW
959#define FCH_EHCI_REG60 0x60 // SBRN - R
960#define FCH_EHCI_REG61 0x61 // FLADJ - RW
961#define FCH_EHCI_REG62 0x62 // PORTWAKECAP - RW
962#define FCH_EHCI_REG64 0x64 // Misc Control 2 - RW
963#define FCH_EHCI_REG70 0x70 // Over Current Control - RW
964#define FCH_EHCI_REG74 0x74 // EHCI Misc Control2 - RW
965#define FCH_EHCI_REG84 0x84 // HUB Configure 1 - RW
966#define FCH_EHCI_REG88 0x88 // - RW
967#define FCH_EHCI_REG90 0x90 // HUB Configure 4 - RW
968#define FCH_EHCI_REGA0 0xA0 //
969#define FCH_EHCI_REGA4 0xA4 //
970#define FCH_EHCI_REGC0 0x0C0 // PME control - RW (800)
971#define FCH_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800)
972#define FCH_EHCI_REGD0 0x0D0 // MSI Control - RW
973#define FCH_EHCI_REGD4 0x0D4 // MSI Address - RW
974#define FCH_EHCI_REGD8 0x0D8 // MSI Data - RW
975#define FCH_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800)
976#define FCH_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800)
977#define FCH_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800)
978
979#define FCH_EHCI_BAR_REG00 0x00 // CAPLENGT - R
980#define FCH_EHCI_BAR_REG02 0x002 // CIVERSION- R
981#define FCH_EHCI_BAR_REG04 0x004 // CSPARAMS - R
982#define FCH_EHCI_BAR_REG08 0x008 // CCPARAMS - R
983#define FCH_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R
984
985#define FCH_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits
986#define FCH_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits
987#define FCH_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits
988#define FCH_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits
989#define FCH_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits
990#define FCH_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits
991#define FCH_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits
992#define FCH_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits
993#define FCH_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits
994#define FCH_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800)
995#define FCH_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits
996#define FCH_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R
997#define FCH_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R
998#define FCH_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R
999#define FCH_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800)
1000#define FCH_EHCI_BAR_REGB8 0x0B8 // Loopback Test
1001#define FCH_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control
1002#define FCH_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration
1003#define FCH_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control
1004#define FCH_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose
1005#define FCH_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) **
1006#define FCH_EHCI_BAR_REGD0 0x0D0
1007#define FCH_EHCI_BAR_REGD4 0x0D4
1008#define FCH_EHCI_BAR_REGDC 0x0DC
1009#define FCH_EHCI_BAR_REG100 0x100 // USB debug port
1010
1011//
1012// USB XHCI Device 0x7812/0x7814
1013// Device 16 (0x10) Func 0/1
1014//
1015#define FCH_XHCI_REG00 0x00 // DEVICE/VENDOR ID - R
1016#define FCH_XHCI_REG04 0x04 // Command - RW
1017#define FCH_XHCI_REG10 0x10 // Bar0
1018#define FCH_XHCI_REG2C 0x2C // Sub System ID
1019#define FCH_XHCI_REG40 0x40 // Index0
1020#define FCH_XHCI_REG44 0x44 // Data0
1021#define FCH_XHCI_REG48 0x48 // Index1
1022#define FCH_XHCI_REG4C 0x4C // Data0
1023#define FCH_XHCI_REG54 0x54 // PME Control/Status
1024#define XHCI_EFUSE_LOCATION 0x18 // EFUSE bit 192, 193
1025
1026#define FCH_XHCI_BAR_REG420 0x420 // Port Status and Control
1027#define FCH_XHCI_PORTSC_CCS 0x1 // Port Status and Control
1028#define FCH_XHCI_PORTSC_PED 0x2 // Port Status and Control
1029#define FCH_XHCI_PORTSC_PLS 0x1E0 // Port Status and Control
1030#define FCH_XHCI_PORTSC_SPEED 0x3C00 // Port Status and Control
1031#define FCH_XHCI_PORTSC_PR 0x10 // Port Status and Control
1032
1033//
1034// FCH CFG device 0x780B
1035// Device 20 (0x14) Func 0
1036//
1037#define FCH_CFG_REG00 0x000 // VendorID - R
1038#define FCH_CFG_REG02 0x002 // DeviceID - R
1039#define FCH_CFG_REG04 0x004 // Command- RW
1040#define FCH_CFG_REG05 0x005 // Command- RW
1041#define FCH_CFG_REG06 0x006 // STATUS- RW
1042#define FCH_CFG_REG08 0x008 // Revision ID/Class Code- R
1043#define FCH_CFG_REG0A 0x00A //
1044#define FCH_CFG_REG0B 0x00B //
1045#define FCH_CFG_REG0C 0x00C // Cache Line Size- R
1046#define FCH_CFG_REG0D 0x00D // Latency Timer- R
1047#define FCH_CFG_REG0E 0x00E // Header Type- R
1048#define FCH_CFG_REG0F 0x00F // BIST- R
1049#define FCH_CFG_REG10 0x010 // Base Address 0- R
1050#define FCH_CFG_REG11 0x011 //;
1051#define FCH_CFG_REG12 0x012 //;
1052#define FCH_CFG_REG13 0x013 //;
1053#define FCH_CFG_REG14 0x014 // Base Address 1- R
1054#define FCH_CFG_REG18 0x018 // Base Address 2- R
1055#define FCH_CFG_REG1C 0x01C // Base Address 3- R
1056#define FCH_CFG_REG20 0x020 // Base Address 4- R
1057#define FCH_CFG_REG24 0x024 // Base Address 5- R
1058#define FCH_CFG_REG28 0x028 // Cardbus CIS Pointer- R
1059#define FCH_CFG_REG2C 0x02C // Subsystem Vendor ID- W
1060#define FCH_CFG_REG2E 0x02E // Subsystem ID- W
1061#define FCH_CFG_REG30 0x030 // Expansion ROM Base Address - R
1062#define FCH_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00
1063#define FCH_CFG_REG3C 0x03C // Interrupt Line - R
1064#define FCH_CFG_REG3D 0x03D // Interrupt Pin - R
1065#define FCH_CFG_REG3E 0x03E // Min_Gnt - R
1066#define FCH_CFG_REG3F 0x03F // Max_Lat - R
1067#define FCH_CFG_REG90 0x090 // Smbus Base Address - R
1068#define FCH_CFG_REG9C 0x09C // SBResourceMMIO_BASE
1069
1070//
1071// FCH SATA IDE device
1072// Device 20 (0x14) Func 1
1073//
1074
1075#define FCH_IDE_REG00 0x00 // Vendor ID
1076#define FCH_IDE_REG02 0x02 // Device ID
1077#define FCH_IDE_REG04 0x04 // Command
1078#define FCH_IDE_REG06 0x06 // Status
1079#define FCH_IDE_REG08 0x08 // Revision ID/Class Code
1080#define FCH_IDE_REG09 0x09 // Class Code
1081#define FCH_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID
1082#define FCH_IDE_REG40 0x40 // Configuration - RW - 32 bits
1083#define FCH_IDE_REG34 0x34
1084#define FCH_IDE_REG62 0x62 // IDE Internal Control
1085#define FCH_IDE_REG63 0x63 // IDE Internal Control
1086//
1087// FCH AZALIA device 0x780D
1088// Device 20 (0x14) Func 2
1089//
1090#define ATI_AZALIA_ExtBlk_Addr 0x0F8
1091#define ATI_AZALIA_ExtBlk_DATA 0x0FC
1092
1093#define FCH_AZ_REG00 0x00 // Vendor ID - R
1094#define FCH_AZ_REG02 0x02 // Device ID - R/W
1095#define FCH_AZ_REG04 0x04 // PCI Command
1096#define FCH_AZ_REG06 0x06 // PCI Status - R/W
1097#define FCH_AZ_REG08 0x08 // Revision ID
1098#define FCH_AZ_REG09 0x09 // Programming Interface
1099#define FCH_AZ_REG0A 0x0A // Sub Class Code
1100#define FCH_AZ_REG0B 0x0B // Base Class Code
1101#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W
1102#define FCH_AZ_REG0D 0x0D // Latency Timer
1103#define FCH_AZ_REG0E 0x0E // Header Type
1104#define FCH_AZ_REG0F 0x0F // BIST
1105#define FCH_AZ_REG10 0x10 // Lower Base Address Register
1106#define FCH_AZ_REG14 0x14 // Upper Base Address Register
1107#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID
1108#define FCH_AZ_REG2D 0x2D // Subsystem ID
1109#define FCH_AZ_REG34 0x34 // Capabilities Pointer
1110#define FCH_AZ_REG3C 0x3C // Interrupt Line
1111#define FCH_AZ_REG3D 0x3D // Interrupt Pin
1112#define FCH_AZ_REG3E 0x3E // Minimum Grant
1113#define FCH_AZ_REG3F 0x3F // Maximum Latency
1114#define FCH_AZ_REG40 0x40 // Misc Control 1
1115#define FCH_AZ_REG42 0x42 // Misc Control 2 Register
1116#define FCH_AZ_REG43 0x43 // Misc Control 3 Register
1117#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register
1118#define FCH_AZ_REG46 0x46 // Debug Control Register
1119#define FCH_AZ_REG4C 0x4C
1120#define FCH_AZ_REG50 0x50 // Power Management Capability ID
1121#define FCH_AZ_REG52 0x52 // Power Management Capabilities
1122#define FCH_AZ_REG54 0x54 // Power Management Control/Status
1123#define FCH_AZ_REG60 0x60 // MSI Capability ID
1124#define FCH_AZ_REG62 0x62 // MSI Message Control
1125#define FCH_AZ_REG64 0x64 // MSI Message Lower Address
1126#define FCH_AZ_REG68 0x68 // MSI Message Upper Address
1127#define FCH_AZ_REG6C 0x6C // MSI Message Data
1128
1129#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R
1130#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R
1131#define FCH_AZ_BAR_REG03 0x03 // Major Version - R
1132#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R
1133#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R
1134#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W
1135#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W
1136#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W
1137#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W
1138#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R
1139#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R
1140#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W
1141#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W
1142#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R
1143#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W
1144#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W
1145#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW
1146#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W
1147#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W
1148#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W
1149#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W
1150#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W
1151#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW
1152#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW
1153#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW
1154#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W
1155#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W
1156#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W
1157#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W
1158#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W
1159#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W
1160#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W
1161#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W
1162#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W
1163#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R
1164
1165//
1166// FCH LPC Device 0x780E
1167// Device 20 (0x14) Func 3
1168//
1169#define FCH_LPC_REG00 0x00 // VID- R
1170#define FCH_LPC_REG02 0x02 // DID- R
1171#define FCH_LPC_REG04 0x04 // CMD- RW
1172#define FCH_LPC_REG06 0x06 // STATUS- RW
1173#define FCH_LPC_REG08 0x08 // Revision ID/Class Code - R
1174#define FCH_LPC_REG0C 0x0C // Cache Line Size - R
1175#define FCH_LPC_REG0D 0x0D // Latency Timer - R
1176#define FCH_LPC_REG0E 0x0E // Header Type - R
1177#define FCH_LPC_REG0F 0x0F // BIST- R
1178#define FCH_LPC_REG10 0x10 // Base Address Reg 0- RW*
1179#define FCH_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro
1180#define FCH_LPC_REG34 0x34 // Capabilities Pointer - Ro
1181#define FCH_LPC_REG40 0x40 // PCI Control - RW
1182#define FCH_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW
1183#define FCH_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW
1184#define FCH_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW
1185#define FCH_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW
1186#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW
1187#define FCH_LPC_REG49 0x49 // LPC Sync Timeout Count - RW
1188#define FCH_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW
1189#define FCH_LPC_REG4C 0x4C // Memory Range Register - RW
1190#define FCH_LPC_REG50 0x50 // Rom Protect 0 - RW
1191#define FCH_LPC_REG54 0x54 // Rom Protect 1 - RW
1192#define FCH_LPC_REG58 0x58 // Rom Protect 2 - RW
1193#define FCH_LPC_REG5C 0x5C // Rom Protect 3 - RW
1194#define FCH_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -
1195#define FCH_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -
1196#define FCH_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW
1197#define FCH_LPC_REG65 0x65
1198#define FCH_LPC_REG66 0x66
1199#define FCH_LPC_REG67 0x67
1200#define FCH_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW
1201#define FCH_LPC_REG69 0x69
1202#define FCH_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW
1203#define FCH_LPC_REG6B 0x6B
1204#define FCH_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW
1205#define FCH_LPC_REG6D 0x6D
1206#define FCH_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW
1207#define FCH_LPC_REG6F 0x6F
1208#define FCH_LPC_REG70 0x70 // Firmware ub Select - RW*
1209#define FCH_LPC_REG71 0x71
1210#define FCH_LPC_REG72 0x72
1211#define FCH_LPC_REG73 0x73
1212#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R
1213#define FCH_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R
1214#define FCH_LPC_REG79 0x79 // Miscellaneous Control Bits- W/R
1215#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R
1216#define FCH_LPC_REG9C 0x9C
1217#define FCH_LPC_REG80 0x80 // MSI Capability Register- R
1218#define FCH_LPC_REGA0 0x0A0 // SPI base address
1219#define FCH_LPC_REGA1 0x0A1 // SPI base address
1220#define FCH_LPC_REGA2 0x0A2 // SPI base address
1221#define FCH_LPC_REGA3 0x0A3 // SPI base address
1222#define FCH_LPC_REGA4 0x0A4
1223#define FCH_LPC_REGB8 0x0B8
1224#define FCH_LPC_REGBA 0x0BA // EcControl
1225#define FCH_LPC_REGBB 0x0BB // HostControl
1226#define FCH_LPC_REGC8 0x0C8
1227#define FCH_LPC_REGCC 0x0CC // AutoRomCfg
1228#define FCH_LPC_REGD0 0x0D0
1229#define FCH_LPC_REGD3 0x0D3
1230#define FCH_LPC_REGD4 0x0D4
1231
1232//
1233// FCH PCIB 0x780F
1234// Device 20 (0x14) Func 4
1235//
1236#define FCH_PCIB_REG04 0x04 // Command
1237#define FCH_PCIB_REG0D 0x0D // Primary Master Latency Timer
1238#define FCH_PCIB_REG1B 0x1B // Secondary Latency Timer
1239#define FCH_PCIB_REG1C 0x1C // IO Base
1240#define FCH_PCIB_REG1D 0x1D // IO Limit
1241#define FCH_PCIB_REG40 0x40 // CPCTRL
1242#define FCH_PCIB_REG42 0x42 // CLKCTRL
1243#define FCH_PCIB_REG48 0x48 //
1244#define FCH_PCIB_REG4A 0x4A // PCICLK Enable Bits
1245#define FCH_PCIB_REG4B 0x4B // Misc Control
1246#define FCH_PCIB_REG4C 0x4C // AutoClockRun Control
1247#define FCH_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override
1248#define FCH_PCIB_REG65 0x65 // Misc Control
1249#define FCH_PCIB_REG66 0x66 // Misc Control
1250//
1251// FCH GEC 0x14E4 0x1699
1252// Device 20 (0x14) Func 6
1253//
1254#define FCH_GEC_REG10 0x10 // GEC BAR
1255
1256//
1257// FCH SD
1258// Device 20 (0x14) Func 7
1259//
1260#define SD_PCI_REG10 0x10
1261#define SD_PCI_REG2C 0x2C
1262#define SD_PCI_REGA4 0xA4
1263#define SD_PCI_REGA8 0xA8
1264#define SD_PCI_REGAC 0xAC
1265#define SD_PCI_REGB0 0xB0
1266#define SD_PCI_REGB8 0xB8
1267#define SD_PCI_REGBC 0xBC
1268#define SD_PCI_REGD0 0xD0
1269#define SD_PCI_REGF0 0xF0
1270#define SD_PCI_REGF4 0xF4
1271#define SD_PCI_REGF8 0xF8
1272#define SD_PCI_REGFC 0xFC
1273#define FCH_SD_BAR_REG28 0x28 // SDHC_CTRL1
1274#define SD_CARD_PRESENT BIT0
1275#define FCH_SD_BAR_REG2C 0x2C // SDHC_CTRL2
1276#define FCH_SD_FREQUENCY_SLT BIT2
1277#define FCH_SD_BAR_REG3C 0x3C // SDHC_HOST_CTRL2
1278#define FCH_SD_1_8V BIT3
1279
1280//
1281// FCH MMIO Base (SMI)
1282// offset : 0x200
1283//
1284#define FCH_SMI_REG00 0x00 // EventStatus
1285#define FCH_SMI_REG04 0x04 // EventEnable
1286#define FCH_SMI_REG08 0x08 // SciTrig
1287#define FCH_SMI_REG0C 0x0C // SciLevl
1288#define FCH_SMI_REG10 0x10 // SmiSciStatus
1289#define FCH_SMI_REG14 0x14 // SmiSciEn
1290#define FCH_SMI_REG18 0x18 // ForceSciEn
1291#define FCH_SMI_REG1C 0x1C // SciRwData
1292#define FCH_SMI_REG3C 0x3C // DataErrorStatus
1293#define FCH_SMI_REG20 0x20 // SciS0En
1294#define FCH_SMI_Gevent0 0x40 // SciMap0
1295#define FCH_SMI_Gevent1 0x41 // SciMap1
1296#define FCH_SMI_Gevent2 0x42 // SciMap2
1297#define FCH_SMI_Gevent3 0x43 // SciMap3
1298#define FCH_SMI_Gevent4 0x44 // SciMap4
1299#define FCH_SMI_Gevent5 0x45 // SciMap5
1300#define FCH_SMI_Gevent6 0x46 // SciMap6
1301#define FCH_SMI_Gevent7 0x47 // SciMap7
1302#define FCH_SMI_Gevent8 0x48 // SciMap8
1303#define FCH_SMI_Gevent9 0x49 // SciMap9
1304#define FCH_SMI_Gevent10 0x4A // SciMap10
1305#define FCH_SMI_Gevent11 0x4B // SciMap11
1306#define FCH_SMI_Gevent12 0x4C // SciMap12
1307#define FCH_SMI_Gevent13 0x4D // SciMap13
1308#define FCH_SMI_Gevent14 0x4E // SciMap14
1309#define FCH_SMI_Gevent15 0x4F // SciMap15
1310#define FCH_SMI_Gevent16 0x50 // SciMap16
1311#define FCH_SMI_Gevent17 0x51 // SciMap17
1312#define FCH_SMI_Gevent18 0x52 // SciMap18
1313#define FCH_SMI_Gevent19 0x53 // SciMap19
1314#define FCH_SMI_Gevent20 0x54 // SciMap20
1315#define FCH_SMI_Gevent21 0x55 // SciMap21
1316#define FCH_SMI_Gevent22 0x56 // SciMap22
1317#define FCH_SMI_Gevent23 0x57 // SciMap23
1318#define FCH_SMI_Usbwakup0 0x58 // SciMap24
1319#define FCH_SMI_Usbwakup1 0x59 // SciMap25
1320#define FCH_SMI_Usbwakup2 0x5A // SciMap26
1321#define FCH_SMI_Usbwakup3 0x5B // SciMap27
1322#define FCH_SMI_SBGppPme0 0x5C // SciMap28
1323#define FCH_SMI_SBGppPme1 0x5D // SciMap29
1324#define FCH_SMI_SBGppPme2 0x5E // SciMap30
1325#define FCH_SMI_SBGppPme3 0x5F // SciMap31
1326#define FCH_SMI_SBGppHp0 0x60 // SciMap32
1327#define FCH_SMI_SBGppHp1 0x61 // SciMap33
1328#define FCH_SMI_SBGppHp2 0x62 // SciMap34
1329#define FCH_SMI_SBGppHp3 0x63 // SciMap35
1330#define FCH_SMI_AzaliaPme 0x64 // SciMap36
1331#define FCH_SMI_SataGevent0 0x65 // SciMap37
1332#define FCH_SMI_SataGevent1 0x66 // SciMap38
1333#define FCH_SMI_GecPme 0x67 // SciMap39
1334#define FCH_SMI_IMCGevent0 0x68 // SciMap40
1335#define FCH_SMI_IMCGevent1 0x69 // SciMap41
1336#define FCH_SMI_CIRPme 0x6A // SciMap42
1337#define FCH_SMI_WakePinGevent 0x6B // SciMap43
1338#define FCH_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent
1339#define FCH_SMI_ASFMasterIntr 0x6D // SciMap45
1340#define FCH_SMI_ASFSlaveIntr 0x6E // SciMap46
1341#define FCH_SMI_SMBUS0 0x6F // SciMap47
1342#define FCH_SMI_TWARN 0x70 // SciMap48
1343#define FCH_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr
1344#define FCH_SMI_iLLB 0x72 // SciMap50
1345#define FCH_SMI_PowerButton 0x73 // SciMap51
1346#define FCH_SMI_ProcHot 0x74 // SciMap52
1347#define FCH_SMI_APUHwAssertion 0x75 // SciMap53
1348#define FCH_SMI_APUSciAssertion 0x76 // SciMap54
1349#define FCH_SMI_RAS 0x77 // SciMap55
1350#define FCH_SMI_xHC0Pme 0x78 // SciMap56
1351#define FCH_SMI_xHC1Pme 0x79 // SciMap57
1352#define FCH_SMI_AcDcWake 0x7A // SciMap58
1353
1354// Empty from 0x72-0x7F
1355//#Define FCH_SMI_REG7C 0x7F // SciMap63 ***
1356
1357#define FCH_SMI_REG80 0x80 // SmiStatus0
1358#define FCH_SMI_REG84 0x84 // SmiStatus1
1359#define FCH_SMI_REG88 0x88 // SmiStatus2
1360#define FCH_SMI_REG8C 0x8C // SmiStatus3
1361#define FCH_SMI_REG90 0x90 // SmiStatus4
1362#define FCH_SMI_REG94 0x94 // SmiPointer
1363#define FCH_SMI_REG96 0x96 // SmiTimer
1364#define FCH_SMI_REG98 0x98 // SmiTrig
1365#define FCH_SMI_REG9C 0x9C // SmiTrig
1366#define FCH_SMI_REGA0 0xA0
1367#define FCH_SMI_REGA1 0xA1
1368#define FCH_SMI_REGA2 0xA2
1369#define FCH_SMI_REGA3 0xA3
1370#define FCH_SMI_REGA4 0xA4
1371#define FCH_SMI_REGA5 0xA5
1372#define FCH_SMI_REGA6 0xA6
1373#define FCH_SMI_REGA7 0xA7
1374#define FCH_SMI_REGA8 0xA8
1375#define FCH_SMI_REGA9 0xA9
1376#define FCH_SMI_REGAA 0xAA
1377#define FCH_SMI_REGAB 0xAB
1378#define FCH_SMI_REGAC 0xAC
1379#define FCH_SMI_REGAD 0xAD
1380#define FCH_SMI_REGAE 0xAE
1381#define FCH_SMI_REGAF 0xAF
1382#define FCH_SMI_REGB0 0xB0
1383#define FCH_SMI_REGB1 0xB1
1384#define FCH_SMI_REGB2 0xB2
1385#define FCH_SMI_REGB3 0xB3
1386#define FCH_SMI_REGB4 0xB4
1387#define FCH_SMI_REGB5 0xB5
1388#define FCH_SMI_REGB6 0xB6
1389#define FCH_SMI_REGB7 0xB7
1390#define FCH_SMI_REGB8 0xB8
1391#define FCH_SMI_REGB9 0xB9
1392#define FCH_SMI_REGBA 0xBA
1393#define FCH_SMI_REGBB 0xBB
1394#define FCH_SMI_REGBC 0xBC
1395#define FCH_SMI_REGBD 0xBD
1396#define FCH_SMI_REGBE 0xBE
1397#define FCH_SMI_REGBF 0xBF
1398#define FCH_SMI_REGC0 0xC0
1399#define FCH_SMI_REGC1 0xC1
1400#define FCH_SMI_REGC2 0xC2
1401#define FCH_SMI_REGC3 0xC3
1402#define FCH_SMI_REGC4 0xC4
1403#define FCH_SMI_REGC5 0xC5
1404#define FCH_SMI_REGC6 0xC6
1405#define FCH_SMI_REGC7 0xC7
1406#define FCH_SMI_REGC8 0xC8
1407#define FCH_SMI_REGCA 0xCA // IoTrapping1
1408#define FCH_SMI_REGCC 0xCC // IoTrapping2
1409#define FCH_SMI_REGCE 0xCE // IoTrapping3
1410#define FCH_SMI_TRAPPING_WRITE 0x01
1411#define FCH_SMI_REGD0 0xD0 // MemTrapping0
1412#define FCH_SMI_REGD4 0xD4 // MemRdOvrData0
1413#define FCH_SMI_REGD8 0xD8 // MemTrapping1
1414#define FCH_SMI_REGDC 0xDC // MemRdOvrData1
1415#define FCH_SMI_REGE0 0xE0 // MemTrapping2
1416#define FCH_SMI_REGE4 0xE4 // MemRdOvrData2
1417#define FCH_SMI_REGE8 0xE8 // MemTrapping3
1418#define FCH_SMI_REGEC 0xEC // MemRdOvrData3
1419#define FCH_SMI_REGF0 0xF0 // CfgTrapping0
1420#define FCH_SMI_REGF4 0xF4 // CfgTrapping1
1421#define FCH_SMI_REGF8 0xF8 // CfgTrapping2
1422#define FCH_SMI_REGFC 0xFC // CfgTrapping3
1423
1424//
1425// FCH MMIO Base (PMIO)
1426// offset : 0x300
1427//
1428#define FCH_PMIOA_REG00 0x00 // ISA Decode
1429#define FCH_PMIOA_REG04 0x04 // ISA Control
1430#define FCH_PMIOA_REG08 0x08 // PCI Control
1431#define FCH_PMIOA_REG0C 0x0C // StpClkSmaf
1432#define FCH_PMIOA_REG10 0x10 // RetryDetect
1433#define FCH_PMIOA_REG14 0x14 // StuckDetect
1434#define FCH_PMIOA_REG20 0x20 // BiosRamEn
1435#define FCH_PMIOA_REG24 0x24 // AcpiMmioEn
1436#define FCH_PMIOA_REG28 0x28 // AsfEn
1437#define FCH_PMIOA_REG2C 0x2C // Smbus0En
1438#define FCH_PMIOA_REG2E 0x2E // Smbus0Sel
1439#define FCH_PMIOA_REG34 0x34 // IoApicEn
1440#define FCH_PMIOA_REG3C 0x3C // SmartVoltEn
1441#define FCH_PMIOA_REG40 0x40 // SmartVolt2En
1442#define FCH_PMIOA_REG44 0x44 // BootTimerEn
1443#define FCH_PMIOA_REG48 0x48 // WatchDogTimerEn
1444#define FCH_PMIOA_REG4C 0x4C // WatchDogTimerConfig
1445#define FCH_PMIOA_REG50 0x50 // HPETEn
1446#define FCH_PMIOA_REG54 0x54 // SerialIrqConfig
1447#define FCH_PMIOA_REG56 0x56 // RtcControl
1448#define FCH_PMIOA_REG58 0x58 // VRT_T1
1449#define FCH_PMIOA_REG59 0x59 // VRT_T2
1450#define FCH_PMIOA_REG5A 0x5A // IntruderControl
1451#define FCH_PMIOA_REG5B 0x5B // RtcShadow
1452#define FCH_PMIOA_REG5C 0x5C
1453#define FCH_PMIOA_REG5D 0x5D
1454#define FCH_PMIOA_REG5E 0x5E // RtcExtIndex
1455#define FCH_PMIOA_REG5F 0x5F // RtcExtData
1456#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk
1457#define FCH_PMIOA_REG62 0x62 // AcpiPm1CntBlk
1458#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk
1459#define FCH_PMIOA_REG66 0x66 // P_CNTBlk
1460#define FCH_PMIOA_REG68 0x68 // AcpiGpe0Blk
1461#define FCH_PMIOA_REG6A 0x6A // AcpiSmiCmd
1462#define FCH_PMIOA_REG6C 0x6C // AcpiPm2CntBlk
1463#define FCH_PMIOA_REG6E 0x6E // AcpiPmaCntBlk
1464#define FCH_PMIOA_REG74 0x74 // AcpiConfig
1465#define FCH_PMIOA_REG78 0x78 // WakeIoAddr
1466#define FCH_PMIOA_REG7A 0x7A // HaltCountEn
1467#define FCH_PMIOA_REG7C 0x7C // C1eWrPortAdr
1468#define FCH_PMIOA_REG7E 0x7E // CStateEn
1469#define FCH_PMIOA_REG7F 0x7F // CStateEn
1470#define FCH_PMIOA_REG80 0x80 // BreakEvent
1471#define FCH_PMIOA_REG84 0x84 // AutoArbEn
1472#define FCH_PMIOA_REG88 0x88 // CStateControl
1473#define FCH_PMIOA_REG89 0x89 //
1474#define FCH_PMIOA_REG8C 0x8C // StpClkHoldTime
1475#define FCH_PMIOA_REG8E 0x8E // PopUpEndTime
1476#define FCH_PMIOA_REG90 0x90 // C4Control
1477#define FCH_PMIOA_REG94 0x94 // CStateTiming0
1478#define FCH_PMIOA_REG96 0x96 //
1479#define FCH_PMIOA_REG97 0x97 //
1480#define FCH_PMIOA_REG98 0x98 // CStateTiming1
1481#define FCH_PMIOA_REG99 0x99 //
1482#define FCH_PMIOA_REG9B 0x9B //
1483#define FCH_PMIOA_REG9C 0x9C // C2Count
1484#define FCH_PMIOA_REG9D 0x9D // C3Count
1485#define FCH_PMIOA_REG9E 0x9E // C4Count
1486#define FCH_PMIOA_REGA0 0xA0 // MessageCState
1487#define FCH_PMIOA_REGA4 0xA4 //
1488#define FCH_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime
1489#define FCH_PMIOA_REGAA 0xAA // TrafficMonitorIntTime
1490#define FCH_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount
1491#define FCH_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount
1492#define FCH_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick
1493#define FCH_PMIOA_REGB4 0xB4 // FidVidControl
1494#define FCH_PMIOA_REGB6 0xB6 // TPRESET1
1495#define FCH_PMIOA_REGB7 0xB7 // Tpreset1b
1496#define FCH_PMIOA_REGB8 0xB8 // TPRESET2
1497#define FCH_PMIOA_REGB9 0xB9 // Test0
1498#define FCH_PMIOA_REGBA 0xBA // S_StateControl
1499#define FCH_PMIOA_REGBB 0xBB //
1500#define FCH_PMIOA_REGBC 0xBC // ThrottlingControl
1501#define FCH_PMIOA_REGBE 0xBE // ResetControl
1502#define FCH_PMIOA_REGBF 0xBF // ResetControl
1503#define FCH_PMIOA_REGC0 0xC0 // S5Status
1504#define FCH_PMIOA_REGC2 0xC2 // ResetStatus
1505#define FCH_PMIOA_REGC4 0xC4 // ResetCommand
1506#define FCH_PMIOA_REGC5 0xC5 // CF9Shadow
1507#define FCH_PMIOA_REGC6 0xC6 // HTControl
1508#define FCH_PMIOA_REGC8 0xC8 // Misc
1509#define FCH_PMIOA_REGCC 0xCC // IoDrvSth
1510#define FCH_PMIOA_REGD0 0xD0 // CLKRunEn
1511#define FCH_PMIOA_REGD2 0xD2 // PmioDebug
1512#define FCH_PMIOA_REGD3 0xD3 // SD
1513#define FCH_PMIOA_REGD6 0xD6 // IMCGating
1514#define FCH_PMIOA_REGD7 0xD7 //
1515#define FCH_PMIOA_REGD8 0xD8 // MiscIndex
1516#define FCH_PMIOA_REGD9 0xD9 // MiscData
1517#define FCH_PMIOA_REGDA 0xDA // SataConfig
1518#define FCH_PMIOA_REGDC 0xDC // HyperFlashConfig
1519#define FCH_PMIOA_REGDE 0xDE // ABConfig
1520#define FCH_PMIOA_REGE0 0xE0 // ABRegBar
1521#define FCH_PMIOA_REGE4 0xE4
1522#define FCH_PMIOA_REGE6 0xE6 // FcEn
1523#define FCH_PMIOA_REGE7 0xE7
1524#define FCH_PMIOA_REGE8 0xE8
1525#define FCH_PMIOA_REGEA 0xEA // PcibConfig
1526#define FCH_PMIOA_REGEB 0xEB // AzEn
1527#define FCH_PMIOA_REGEC 0xEC // LpcGating
1528#define FCH_PMIOA_REGED 0xED // UsbGating
1529#define FCH_PMIOA_REGEE 0xEE // UsbCntrl
1530#define FCH_PMIOA_REGEF 0xEF // UsbEnable
1531#define FCH_PMIOA_REGF0 0xF0 // UsbControl
1532#define FCH_PMIOA_REGF2 0xF2 // UsbControl2
1533#define FCH_PMIOA_REGF3 0xF3 // UsbDebug
1534#define FCH_PMIOA_REGF4 0xF4 // UsbDebug
1535#define FCH_PMIOA_REGF6 0xF6 // GecEn
1536#define FCH_PMIOA_REGF8 0xF8 // GecConfig
1537#define FCH_PMIOA_REGFC 0xFC // TraceMemoryEn
1538
1539#define FCH_PMx00_DecodeEn 0xFED80300ul //
1540#define FCH_PMxC0_ResetStatus 0xFED803C0ul //
1541#define FCH_PMxC0_ResetStatus_Mask 0x3fff0000ul //
1542#define FCH_PMxC4_ResetCommand 0xFED803C4ul //
1543#define FCH_PMxDC_SataConfig2 0xFED803DCul //
1544
1545//
1546// FCH MMIO Base (PMIO2)
1547// offset : 0x400
1548//
1549#define FCH_PMIO2_REG00 0x00 // Fan0InputControl
1550#define FCH_PMIO2_REG01 0x01 // Fan0Control
1551#define FCH_PMIO2_REG02 0x02 // Fan0Freq
1552#define FCH_PMIO2_REG03 0x03 // LowDuty0
1553#define FCH_PMIO2_REG04 0x04 // MidDuty0
1554
1555#define FCH_PMIO2_REG10 0x00 // Fan1InputControl
1556#define FCH_PMIO2_REG11 0x01 // Fan1Control
1557#define FCH_PMIO2_REG12 0x02 // Fan1Freq
1558#define FCH_PMIO2_REG13 0x03 // LowDuty1
1559#define FCH_PMIO2_REG14 0x04 // MidDuty1
1560
1561#define FCH_PMIO2_REG63 0x63 // SampleFreqDiv
1562#define FCH_PMIO2_REG69 0x69 // Fan0 Speed
1563#define FCH_PMIO2_REG95 0x95 // Temperature
1564#define FCH_PMIO2_REGB8 0xB8 // Voltage
1565#define FCH_PMIO2_REGEA 0xEA // Hwm_Calibration
1566
1567#define FCH_PMIO2_REG92 0x92 //
1568#define FCH_PMIO2_REGF8 0xF8 // VoltageSamleSel
1569#define FCH_PMIO2_REGF9 0xF9 // TempSampleSel
1570
1571#define FCH_PMIO2_REG 0xFC // TraceMemoryEn
1572
1573
1574//
1575// FCH MMIO Base (GPIO/IoMux)
1576// offset : 0x100/0xD00
1577//
1578/*
1579GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
1580*/
1581#define FCH_GPIO_REG00 0x00
1582#define FCH_GPIO_REG06 0x06
1583#define FCH_GPIO_REG09 0x09
1584#define FCH_GPIO_REG10 0x0A
1585#define FCH_GPIO_REG17 0x11
1586#define FCH_GPIO_REG21 0x15
1587#define FCH_GPIO_REG28 0x1C
1588#define FCH_GPIO_REG32 0x20
1589#define FCH_GPIO_REG33 0x21
1590#define FCH_GPIO_REG34 0x22
1591#define FCH_GPIO_REG35 0x23
1592#define FCH_GPIO_REG36 0x24
1593#define FCH_GPIO_REG37 0x25
1594#define FCH_GPIO_REG38 0x26
1595#define FCH_GPIO_REG39 0x27
1596#define FCH_GPIO_REG40 0x28
1597#define FCH_GPIO_REG41 0x29
1598#define FCH_GPIO_REG42 0x2A
1599#define FCH_GPIO_REG43 0x2B
1600#define FCH_GPIO_REG44 0x2C
1601#define FCH_GPIO_REG45 0x2D
1602#define FCH_GPIO_REG46 0x2E
1603#define FCH_GPIO_REG47 0x2F
1604#define FCH_GPIO_REG48 0x30
1605#define FCH_GPIO_REG49 0x31
1606#define FCH_GPIO_REG50 0x32
1607#define FCH_GPIO_REG51 0x33
1608#define FCH_GPIO_REG52 0x34
1609#define FCH_GPIO_REG53 0x35
1610#define FCH_GPIO_REG54 0x36
1611#define FCH_GPIO_REG55 0x37
1612#define FCH_GPIO_REG56 0x38
1613#define FCH_GPIO_REG57 0x39
1614#define FCH_GPIO_REG58 0x3A
1615#define FCH_GPIO_REG59 0x3B
1616#define FCH_GPIO_REG60 0x3C
1617#define FCH_GPIO_REG61 0x3D
1618#define FCH_GPIO_REG62 0x3E
1619#define FCH_GPIO_REG63 0x3F
1620#define FCH_GPIO_REG64 0x40
1621#define FCH_GPIO_REG65 0x41
1622#define FCH_GPIO_REG66 0x42
1623#define FCH_GPIO_REG67 0x43
1624#define FCH_GPIO_REG68 0x44
1625#define FCH_GPIO_REG69 0x45
1626#define FCH_GPIO_REG70 0x46
1627#define FCH_GPIO_REG71 0x47
1628#define FCH_GPIO_REG72 0x48
1629#define FCH_GPIO_REG73 0x49
1630#define FCH_GPIO_REG74 0x4A
1631#define FCH_GPIO_REG75 0x4B
1632#define FCH_GPIO_REG76 0x4C
1633#define FCH_GPIO_REG77 0x4D
1634#define FCH_GPIO_REG78 0x4E
1635#define FCH_GPIO_REG79 0x4F
1636#define FCH_GPIO_REG80 0x50
1637
1638#define FCH_GEVENT_REG00 0x60
1639#define FCH_GEVENT_REG01 0x61
1640#define FCH_GEVENT_REG02 0x62
1641#define FCH_GEVENT_REG03 0x63
1642#define FCH_GEVENT_REG04 0x64
1643#define FCH_GEVENT_REG05 0x65
1644#define FCH_GEVENT_REG06 0x66
1645#define FCH_GEVENT_REG07 0x67
1646#define FCH_GEVENT_REG08 0x68
1647#define FCH_GEVENT_REG09 0x69
1648#define FCH_GEVENT_REG10 0x6A
1649#define FCH_GEVENT_REG11 0x6B
1650#define FCH_GEVENT_REG12 0x6C
1651#define FCH_GEVENT_REG13 0x6D
1652#define FCH_GEVENT_REG14 0x6E
1653#define FCH_GEVENT_REG15 0x6F
1654#define FCH_GEVENT_REG16 0x70
1655#define FCH_GEVENT_REG17 0x71
1656#define FCH_GEVENT_REG18 0x72
1657#define FCH_GEVENT_REG19 0x73
1658#define FCH_GEVENT_REG20 0x74
1659#define FCH_GEVENT_REG21 0x75
1660#define FCH_GEVENT_REG22 0x76
1661#define FCH_GEVENT_REG23 0x77
1662// S5-DOMAIN GPIO
1663#define FCH_GPIO_REG160 0xA0
1664#define FCH_GPIO_REG161 0xA1
1665#define FCH_GPIO_REG162 0xA2
1666#define FCH_GPIO_REG163 0xA3
1667#define FCH_GPIO_REG164 0xA4
1668#define FCH_GPIO_REG165 0xA5
1669#define FCH_GPIO_REG166 0xA6
1670#define FCH_GPIO_REG167 0xA7
1671#define FCH_GPIO_REG168 0xA8
1672#define FCH_GPIO_REG169 0xA9
1673#define FCH_GPIO_REG170 0xAA
1674#define FCH_GPIO_REG171 0xAB
1675#define FCH_GPIO_REG172 0xAC
1676#define FCH_GPIO_REG173 0xAD
1677#define FCH_GPIO_REG174 0xAE
1678#define FCH_GPIO_REG175 0xAF
1679#define FCH_GPIO_REG176 0xB0
1680#define FCH_GPIO_REG177 0xB1
1681#define FCH_GPIO_REG178 0xB2
1682#define FCH_GPIO_REG179 0xB3
1683#define FCH_GPIO_REG180 0xB4
1684#define FCH_GPIO_REG181 0xB5
1685#define FCH_GPIO_REG182 0xB6
1686#define FCH_GPIO_REG183 0xB7
1687#define FCH_GPIO_REG184 0xB8
1688#define FCH_GPIO_REG185 0xB9
1689#define FCH_GPIO_REG186 0xBA
1690#define FCH_GPIO_REG187 0xBB
1691#define FCH_GPIO_REG188 0xBC
1692#define FCH_GPIO_REG189 0xBD
1693#define FCH_GPIO_REG190 0xBE
1694#define FCH_GPIO_REG191 0xBF
1695#define FCH_GPIO_REG192 0xC0
1696#define FCH_GPIO_REG193 0xC1
1697#define FCH_GPIO_REG194 0xC2
1698#define FCH_GPIO_REG195 0xC3
1699#define FCH_GPIO_REG196 0xC4
1700#define FCH_GPIO_REG197 0xC5
1701#define FCH_GPIO_REG198 0xC6
1702#define FCH_GPIO_REG199 0xC7
1703#define FCH_GPIO_REG200 0xC8
1704#define FCH_GPIO_REG201 0xC9
1705#define FCH_GPIO_REG202 0xCA
1706#define FCH_GPIO_REG203 0xCB
1707#define FCH_GPIO_REG204 0xCC
1708#define FCH_GPIO_REG205 0xCD
1709#define FCH_GPIO_REG206 0xCE
1710#define FCH_GPIO_REG207 0xCF
1711#define FCH_GPIO_REG208 0xD0
1712#define FCH_GPIO_REG209 0xD1
1713#define FCH_GPIO_REG210 0xD2
1714#define FCH_GPIO_REG211 0xD3
1715#define FCH_GPIO_REG212 0xD4
1716#define FCH_GPIO_REG213 0xD5
1717#define FCH_GPIO_REG214 0xD6
1718#define FCH_GPIO_REG215 0xD7
1719#define FCH_GPIO_REG216 0xD8
1720#define FCH_GPIO_REG217 0xD9
1721#define FCH_GPIO_REG218 0xDA
1722#define FCH_GPIO_REG219 0xDB
1723#define FCH_GPIO_REG220 0xDC
1724#define FCH_GPIO_REG221 0xDD
1725#define FCH_GPIO_REG222 0xDE
1726#define FCH_GPIO_REG223 0xDF
1727#define FCH_GPIO_REG224 0xF0
1728#define FCH_GPIO_REG225 0xF1
1729#define FCH_GPIO_REG226 0xF2
1730#define FCH_GPIO_REG227 0xF3
1731#define FCH_GPIO_REG228 0xF4
1732
1733#define FCH_IOMUXx0D_IR_TX0_USB_OC5_L_AGPIO13 0xFED80D0Dul //
1734#define FCH_IOMUXx0E_IR_TX1_USB_OC6_L_AGPIO14 0xFED80D0Eul //
1735#define FCH_IOMUXx13_SCL1_I2C3_SCL_EGPIO19 0xFED80D13ul //
1736#define FCH_IOMUXx14_SDA1_I2C3_SDA_EGPIO20 0xFED80D14ul //
1737#define FCH_IOMUX_55_FANOUT0_AGPIO85 0xFED80D55ul // FANOUT0_AGPIO85
1738#define FCH_IOMUXx66_SD0_PWR_CTRL_AGPIO102 0xFED80D66ul //
1739#define FCH_IOMUXx71_SCL0_I2C2_SCL_EGPIO113 0xFED80D71ul //
1740#define FCH_IOMUXx72_SDA0_I2C2_SDA_EGPIO114 0xFED80D72ul //
1741#define FCH_IOMUXx89_UART0_RTS_L_EGPIO137 0xFED80D89ul //
1742#define FCH_IOMUXx8A_UART0_TXD_EGPIO138 0xFED80D8Aul //
1743#define FCH_IOMUXx8E_UART1_RTS_L_EGPIO142 0xFED80D8Eul //
1744#define FCH_IOMUXx8F_UART1_TXD_EGPIO143 0xFED80D8Ful //
1745
1746//
1747// FCH MMIO Base (GPIO BANK0)
1748// offset : 0x1500
1749//
1750#define FCH_GPIO_PULL_UP_ENABLE BIT4
1751#define FCH_GPIO_PULL_DOWN_ENABLE BIT5
1752#define FCH_GPIO_OUTPUT_VALUE BIT6
1753#define FCH_GPIO_OUTPUT_ENABLE (1 << 7)
1754
1755#define FCH_GPIO_068_AZ_SDIN0_GPIO26 0x68
1756#define FCH_GPIO_06C_AZ_SDIN1_GPIO27 0x6C
1757#define FCH_GPIO_070_AZ_SDIN2_GPIO28 0x70
1758#define FCH_GPIO_074_AZ_SDIN3_GPIO29 0x74
1759
1760#define FCH_GPIO_10C_GPIO55_AGPI067 0x10C
1761#define FCH_GPIO_118_GPIO59_AGPI070 0x118
1762
1763//
1764// FCH MMIO Base (IoMux)
1765// offset : 0xD00
1766//
1767#define FCH_IOMUX_1A_AZ_SDIN0_EGPIO26 0x1A
1768#define FCH_IOMUX_1B_AZ_SDIN1_EGPIO27 0x1B
1769#define FCH_IOMUX_1C_AZ_SDIN2_EGPIO28 0x1C
1770#define FCH_IOMUX_1D_AZ_SDIN3_EGPIO29 0x1D
1771
1772//
1773// FCH MMIO Base (SMBUS)
1774// offset : 0xA00
1775//
1776#define FCH_SMBUS_REG12 0x12 // I2CbusConfig
1777
1778//
1779// FCH MMIO Base (MISC)
1780// offset : 0xE00
1781//
1782#define FCH_MISC_REG00 0x00 // ClkCntrl0
1783/*
1784FCH_MISC_REG00 EQU 000h
1785 ClkCntrl0 EQU 0FFFFFFFFh
1786*/
1787#define FCH_MISC_REG04 0x04 // ClkCntrl1
1788/*
1789FCH_MISC_REG04 EQU 004h
1790 ClkCntrl1 EQU 0FFFFFFFFh
1791*/
1792#define FCH_MISC_REG08 0x08 // ClkCntrl2
1793/*
1794FCH_MISC_REG08 EQU 008h
1795 ClkCntrl2 EQU 0FFFFFFFFh
1796*/
1797#define FCH_MISC_REG0C 0x0C // ClkCntrl3
1798/*
1799FCH_MISC_REG0C EQU 00Ch
1800 ClkCntrl3 EQU 0FFFFFFFFh
1801*/
1802#define FCH_MISC_REG10 0x10 // ClkCntrl4
1803/*
1804FCH_MISC_REG10 EQU 010h
1805 ClkCntrl4 EQU 0FFFFFFFFh
1806*/
1807#define FCH_MISC_REG14 0x14 // ClkCntrl5
1808/*
1809FCH_MISC_REG14 EQU 014h
1810 ClkCntrl5 EQU 0FFFFFFFFh
1811*/
1812#define FCH_MISC_REG18 0x18 // ClkCntrl6
1813/*
1814FCH_MISC_REG18 EQU 018h
1815 ClkCntrl6 EQU 0FFFFFFFFh
1816*/
1817#define FCH_MISC_REG1C 0x1C
1818#define FCH_MISC_REG20 0x20
1819#define FCH_MISC_REG30 0x30 // OscFreqCounter
1820/*
1821FCH_MISC_REG30 EQU 030h
1822 OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second.
1823*/
1824#define FCH_MISC_REG34 0x34 // HpetClkPeriod
1825/*
1826FCH_MISC_REG34 EQU 034h
1827 HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M).
1828*/
1829#define FCH_MISC_REG28 0x28 // ClkDrvSth2
1830#define FCH_MISC_REG2C 0x2C
1831#define FCH_MISC_REG40 0x40 // MiscCntrl for clock only
1832#define FCH_MISC_REG41 0x41 // MiscCntr2
1833#define FCH_MISC_REG42 0x42 // MiscCntr3
1834#define FCH_MISC_REG44 0x44 // ValueOnPort80
1835#define FCH_MISC_REG50 0x50 //
1836#define FCH_MISCx50_JTAG_CONTROL_ECO 0xFED80E50ul //
1837#define FCH_MISCx68_MEMORY_POWER_SAVING_CONTROL 0xFED80E68ul //
1838
1839#define FCH_MISC_REG6C 0x6C // EcoBit2
1840/*
1841FCH_MISC_REG40 EQU 040h
1842*/
1843
1844#define FCH_MISC_REG80 0x80 /**< FCH_MISC_REG80
1845 * @par
1846 * StrapStatus [15.0] - FCH chip Strap Status
1847 * @li <b>0001</b> - Not USED FWH
1848 * @li <b>0002</b> - Not USED LPC ROM
1849 * @li <b>0004</b> - EC enabled
1850 * @li <b>0008</b> - Reserved
1851 * @li <b>0010</b> - Internal Clock mode
1852 */
1853#define FCH_MISC_REGB6 0xB6 //
1854
1855#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad
1856#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1)
1857 // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
1858#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC)
1859#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function
1860#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
1861
1862#define FCH_MISC_REG84 0x84 // StrapOverride
1863/*
1864FCH_MISC_REG84 EQU 084h
1865 Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin.
1866 Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin.
1867 Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin.
1868 Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin.
1869 Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin.
1870 Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin.
1871 Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin.
1872 Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin.
1873 Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin.
1874 Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin.
1875 Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin
1876 PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin
1877 BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin
1878 ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin.
1879 BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
1880 StrapOverrideEn EQU BIT31 ; Enable override strapping feature.
1881*/
1882#define FCH_MISC_REGC0 0xC0 // CPU_Pstate0
1883/*
1884FCH_MISC_REGC0 EQU 0C0h
1885 Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
1886 Core1_PState EQU BIT4+BIT5+BIT6
1887 Core2_PState EQU BIT8+BIT9+BIT10
1888 Core3_PState EQU BIT12+BIT13+BIT14
1889 Core4_PState EQU BIT16++BIT17+BIT18
1890 Core5_PState EQU BIT20+BIT21+BIT22
1891 Core6_PState EQU BIT24+BIT25+BIT26
1892 Core7_PState EQU BIT28+BIT29+BIT30
1893*/
1894#define FCH_MISC_REGC4 0xC4 // CPU_Pstate1
1895/*
1896FCH_MISC_REGC4 EQU 0C4h
1897 Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
1898 Core9_PState EQU BIT4+BIT5+BIT6
1899 Core10_PState EQU BIT8+BIT9+BIT10
1900 Core11_PState EQU BIT12+BIT13+BIT14
1901 Core12_PState EQU BIT16++BIT17+BIT18
1902 Core13_PState EQU BIT20+BIT21+BIT22
1903 Core14_PState EQU BIT24+BIT25+BIT26
1904 Core15_PState EQU BIT28+BIT29+BIT30
1905*/
1906#define FCH_MISC_REGD0 0xD0 // CPU_Cstate0
1907/*
1908FCH_MISC_REGD0 EQU 0D0h
1909 Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
1910 Core1_CState EQU BIT4+BIT5+BIT6
1911 Core2_CState EQU BIT8+BIT9+BIT10
1912 Core3_CState EQU BIT12+BIT13+BIT14
1913 Core4_CState EQU BIT16++BIT17+BIT18
1914 Core5_CState EQU BIT20+BIT21+BIT22
1915 Core6_CState EQU BIT24+BIT25+BIT26
1916 Core7_CState EQU BIT28+BIT29+BIT30
1917*/
1918#define FCH_MISC_REGD4 0xD4 // CPU_Cstate1
1919/*
1920FCH_MISC_REGD4 EQU 0D4h
1921 Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
1922 Core9_CState EQU BIT4+BIT5+BIT6
1923 Core10_CState EQU BIT8+BIT9+BIT10
1924 Core11_CState EQU BIT12+BIT13+BIT14
1925 Core12_CState EQU BIT16++BIT17+BIT18
1926 Core13_CState EQU BIT20+BIT21+BIT22
1927 Core14_CState EQU BIT24+BIT25+BIT26
1928 Core15_CState EQU BIT28+BIT29+BIT30
1929*/
1930#define FCH_MISC_REGF0 0xF0 // SataPortSts
1931/*
1932FCH_MISC_REGF0 EQU 0F0h
1933 Port0Sts EQU BIT0 ; The selected status of Port 0.
1934 Port1Sts EQU BIT1 ; The selected status of Port 1
1935 Port2Sts EQU BIT2 ; The selected status of Port 2.
1936 Port3Sts EQU BIT3 ; The selected status of Port 3
1937 Port4Sts EQU BIT4 ; The selected status of Port 4.
1938 Port5Sts EQU BIT5 ; The selected status of Port 5
1939 SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5
1940 ; 01 - Select "delete" for Port 0 to 5
1941 ; 10 - Select "err" for Port 0 to 5
1942 ; 11 - Select "led" for Port 0 to 5
1943*/
1944
1945//
1946// FCH MMIO Base (SERIAL_DEBUG_BASE)
1947// offset : 0x1000
1948//
1949#define FCH_SDB_REG00 0x00 //
1950#define FCH_SDB_REG74 0x74
1951
1952#define FCH_RTC_REG00 0x00 // Seconds - RW
1953#define FCH_RTC_REG01 0x01 // Seconds Alarm - RW
1954#define FCH_RTC_REG02 0x02 // Minutes - RW
1955#define FCH_RTC_REG03 0x03 // Minutes Alarm - RW
1956#define FCH_RTC_REG04 0x04 // ours - RW
1957#define FCH_RTC_REG05 0x05 // ours Alarm- RW
1958#define FCH_RTC_REG06 0x06 // Day of Week - RW
1959#define FCH_RTC_REG07 0x07 // Date of Mont - RW
1960#define FCH_RTC_REG08 0x08 // Mont - RW
1961#define FCH_RTC_REG09 0x09 // Year - RW
1962#define FCH_RTC_REG0A 0x0A // Register A - RW
1963#define FCH_RTC_REG0B 0x0B // Register B - RW
1964#define FCH_RTC_REG0C 0x0C // Register C - R
1965#define FCH_RTC_REG0D 0x0D // DateAlarm - RW
1966#define FCH_RTC_REG32 0x32 // AltCentury - RW
1967#define FCH_RTC_REG48 0x48 // Century - RW
1968#define FCH_RTC_REG50 0x50 // Extended RAM Address Port - RW
1969#define FCH_RTC_REG53 0x53 // Extended RAM Data Port - RW
1970#define FCH_RTC_REG7E 0x7E // RTC Time Clear - RW
1971#define FCH_RTC_REG7F 0x7F // RTC RAM Enable - RW
1972
1973#define FCH_ECMOS_REG00 0x00 // scratch - reg
1974//;BIT0=0 AsicDebug is enabled
1975//;BIT1=0 SLT S3 runs
1976#define FCH_ECMOS_REG01 0x01
1977#define FCH_ECMOS_REG02 0x02
1978#define FCH_ECMOS_REG03 0x03
1979#define FCH_ECMOS_REG04 0x04
1980#define FCH_ECMOS_REG05 0x05
1981#define FCH_ECMOS_REG06 0x06
1982#define FCH_ECMOS_REG07 0x07
1983#define FCH_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure
1984#define FCH_ECMOS_REG09 0x09
1985#define FCH_ECMOS_REG0A 0x0A
1986#define FCH_ECMOS_REG0B 0x0B
1987
1988#define FCH_ECMOS_REG0C 0x0C //;save MODULE_ID
1989#define FCH_ECMOS_REG0D 0x0D //;Reserve for NB
1990
1991//
1992// FCH SMI Base (FCH_SMI_BASE)
1993// offset : 0x0200
1994//
1995#define FCH_SMIx0C_Level 0xFED8020Cul // Level
1996#define FCH_SMIx58_EHCI_WAKE 0xFED80258ul // EHCI WAKE
1997#define FCH_SMIx78_XHCI_WAKE 0xFED80278ul // XHCI WAKE
1998
1999#define FCH_SMIx88_SmiStatus2 0xFED80288ul // SmiStatus2
2000#define FCH_SMIx88_SmiStatus2_UsbSmiEvent76 ( 1 << 12 )
2001
2002//
2003// FCH PMIO Base (FCH_PMIO_BASE)
2004// offset : 0x0300
2005//
2006#define FCH_PMIOx10_Power_Reset_Config 0xFED80310ul //Power Reset Config
2007#define FCH_PMIOx10_Power_Reset_Config_ToggleAllPwrGoodOnCf9 (1 << 1)
2008
2009#define FCH_PMIOx74_AcpiConfig 0xFED80374ul // AcpiConfig
2010#define FCH_PMIOx74_AcpiConfig_PwnBtnEn (1 << 8)
2011#define FCH_PMIOx74_AcpiConfig_AcpiReducedHwEn (1 << 9)
2012
2013#define FCH_PMIOxC0_S5ResetStatus 0xFED803C0ul // S5ResetStatus
2014#define FCH_PMIOxC0_S5ResetStatus_ThermalTrip (1 << 0)
2015#define FCH_PMIOxC0_S5ResetStatus_FourSecondPwrBtn (1 << 1)
2016#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3fe | (1 << 20))
2017#define FCH_PMIOxC0_S5ResetStatus_All_Status 0x3FFF03FFul
2018#define FCH_PMIOxC0_S5ResetStatus_Clr_Status 0x3FFF03FEul
2019
2020#define FCH_PMxC8_Misc 0xFED803C8ul // Misc
2021#define FCH_PMxC8_Misc_UseAcpiStraps (1 << 4)
2022
2023#define FCH_PMxE8_SDFlashCntrl 0xFED803E8ul // SDFlashCntrl
2024#define FCH_PMxE8_SDFlashCntrl_SdCd2Acpi (1 << 5)
2025//
2026// FCH MISC Base (FCH_MISC_BASE)
2027// offset : 0x0E00
2028//
2029#define FCH_MISCx28_ClkDrvStr2 0xFED80E28ul // ClkDrvStr2
2030#define FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn (1 << 30)
2031#define FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn (1 << 31)
2032
2033#define FCH_MISCx40_MiscClkCntl1 0xFED80E40ul // MiscClkCntl1
2034#define FCH_MISCx40_MiscClkCntl1_CG1PLL_FBDIV_Test (1 << 26)
2035
2036#define FCH_MISCx50_JTAG_Control_ECO_bits 0xFED80E50ul // JTAG_Control_ECO_bits
2037#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT12 (1 << 12)
2038#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT16 (1 << 16)
2039
2040// FCH GPIO
2041// offset : 0x1500
2042//
2043#define FCH_GPIOx018_AGPIO6_LDT_RST_L 0xFED81518ul //
2044#define FCH_GPIOx10C_DEVSLP0_EGPIO67 0xFED8160Cul //
2045
2046// FCH XHC PM (FCH_XHC_PM)
2047// offset : 0x1C00
2048//
2049#define FCH_XHC_PMx00_Configure0 0xFED81C00ul //
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]2050#define FCH_XHC_PMx00_Configure0_U3pPllReset BIT8
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]2051#define FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN BIT15
2052#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]2053
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]2054#define FCH_XHC_PMx10_Xhc_Memory_Configure 0xFED81C10ul //
2055#define FCH_XHC_PMx18_Usb20_Link_Status 0xFED81C18ul //
2056#define FCH_XHC_PMx20_Usb20_Wake_Control 0xFED81C20ul //
2057#define FCH_XHC_PMx24_Misc0 0xFED81C24ul //
2058#define FCH_XHC_PMx28_Misc1 0xFED81C28ul //
2059#define FCH_XHC_PMx2C_Misc2 0xFED81C2Cul //
2060#define FCH_XHC_PMx30_Xhci10_Enable 0xFED81C30ul //
2061#define FCH_XHC_PMx60_xHC_Battery_Charger_Enable 0xFED81C60ul //
2062
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]2063#define FCH_XHC_PMx88_SSPHY_Common_Clock_Control_Status 0xFED81C88ul //
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]2064
2065
2066
2067// FCH AOAC Base (FCH_AOAC_BASE)
2068// offset : 0x1E00
2069//
2070#define FCH_AOACx40_D3_CONTROL 0xFED81E40ul //
2071#define FCH_AOACx41_D3_STATUS 0xFED81E40ul //
2072#define FCH_AOACx5E_SATA_D3_CONTROL 0xFED81E5Eul //
2073#define FCH_AOACx64_EHCI_D3_CONTROL 0xFED81E64ul //
2074#define FCH_AOACx65_EHCI_D3_STATE 0xFED81E65ul //
2075#define FCH_AOACx6E_USB3_D3_CONTROL 0xFED81E6Eul //
2076#define FCH_AOACx6F_USB3_D3_STATE 0xFED81E6Ful //
2077#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul //
2078#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul //
2079#define FCH_AOACx88Shadow_Register_SRAM_Addr 0xFED81E88ul //
2080#define FCH_AOACx8CShadow_Register_SRAM_Data 0xFED81E8Cul //
2081#define FCH_AOACx94S013_CONTROL 0xFED81E94ul //
2082#define FCH_AOACx94S013_CONTROL_ARBITER_DIS (1 << 14)
2083#define FCH_AOACx94S013_CONTROL_INTERRUPT_DIS (1 << 15)
2084#define FCH_AOACx9C_Shadow_Timer_Control 0xFED81E9Cul //
2085#define FCH_AOACx9C_Shadow_Timer_Control_ShadowHpetEn (1 << 0) //
2086#define FCH_AOACx9C_Shadow_Timer_Control_ShadowAcpiTimerEn (1 << 1) //
2087
2088#define FCH_AOACxA0_PwrGood_Control 0xFED81EA0ul //
2089#define FCH_AOACxA0_PwrGood_Control_XhcPwrGood (1 << 3) //
2090#define FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown (1 << 29) //
2091#define FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB (1 << 30) //
2092
2093#define FCH_AOAC_REG00 0x00 // PerfMonControl
2094#define FCH_AOAC_REG04 0x04 // PerfMonTimeLimit
2095#define FCH_AOAC_REG08 0x08 // PerfMonWeight[3:0]
2096#define FCH_AOAC_REG0C 0x0C // PerfMonWeight[7:4]
2097#define FCH_AOAC_REG10 0x10 // PerfMonTrafficCnt[1:0]
2098#define FCH_AOAC_REG14 0x14 // PerfMonTrafficCnt[3:2]
2099#define FCH_AOAC_REG18 0x18 // PerfMonTrafficCnt[5:4]
2100#define FCH_AOAC_REG1C 0x1C // PerfMonTrafficCnt[7:6]
2101#define FCH_AOAC_REG20 0x20 // PerfMonTrafficCntAll
2102#define FCH_AOAC_REG24 0x24 // PerfMonIntrCnt
2103#define FCH_AOAC_REG28 0x28 //
2104#define FCH_AOAC_REG2C 0x2C //
2105#define FCH_AOAC_REG30 0x30 // Alternative HPET Timer
2106#define FCH_AOAC_REG34 0x34 // Alternative HPET Timer (HIGH 32BITS)
2107#define FCH_AOAC_REG38 0x38 // Alternative HPET Alarm
2108#define FCH_AOAC_REG3C 0x3C // Alternative HPET Alarm (HIGH 32BITS)
2109/*
2110FCH_AOAC_REG4X-7x Control field
2111*/
2112#define AOAC_TARGET_DEVICE_STATE (BIT0 + BIT1) // TargetedDeviceState -
2113 // 00 - D0 un-initialized
2114 // 01 - D0 initialized
2115 // 10 - D1/D2/D3hot
2116 // 11 - D3cold
2117 //
2118#define AOAC_DEVICE_STATE BIT2 // DeviceState
2119 // 0 - Device power is removed
2120 // 1 - Device power is applied
2121#define AOAC_PWR_ON_DEV BIT3 // PwrOnDev -
2122 // If IsSwControl==0, software can write this bit to trigger a HW
2123 // controlled power-down or reset sequence to the device.
2124 // 0 - Power down the device.
2125 // 1 - Power up the device.
2126 //
2127#define AOAC_SW_PWR_ON_RSTB BIT4 // SwPwrOnRstB -
2128 //
2129 // 0 - PwrRstB is asserted to the device if IsSwControl==1.
2130 // 1 - 1=PwrRstB is de-asserted to the device if IsSwControl==1.
2131 //
2132#define AOAC_SW_REF_CLK_OK BIT5 // SwRefClkOk -
2133 //
2134 // 0 - 0=RefClkOk is de-asserted to the device if IsSwControl==1.
2135 // 1 - RefClkOk is asserted to the device if IsSwControl==1.
2136 //
2137#define AOAC_SW_RST_B BIT6 // SwRstB -
2138 // 0 - RstB is asserted to the device if IsSwControl==1.
2139 // 1 - RstB is deasserted to the device if IsSwControl==1.
2140 //
2141#define AOAC_IS_SW_CONTROL BIT7 // IsSwControl
2142 // To avoid glitch on the reset signals, software must set bit IsSwControl first before programming bit
2143 // SwPwrOnRstB, SwRefClkOk and SwRstB.
2144 // 0 - Hardware controls control signals (PwrRstB, RefClkOk, RstB) to the device.
2145 // 1 - Software controls control signals (PwrRstB, RefClkOk, RstB) to the device.
2146 //
2147/*
2148FCH_AOAC_REG4X-7x State field
2149*/
2150#define A0AC_PWR_RST_STATE BIT0
2151#define AOAC_RST_CLK_OK_STATE BIT1
2152#define AOAC_RST_B_STATE BIT2
2153#define AOAC_DEV_OFF_GATING_STATE BIT3
2154#define AOAC_D3COLD BIT4
2155#define AOAC_CLK_OK_STATE BIT5
2156#define AOAC_STAT0 BIT6
2157#define AOAC_STAT1 BIT7
2158#define FCH_AOAC_REG40 0x40 // ClkGen Control
2159#define FCH_AOAC_REG41 0x41 // ClkGen State
2160#define FCH_AOAC_REG42 0x42 // AB Control
2161#define FCH_AOAC_REG43 0x43 // AB State
2162#define FCH_AOAC_REG44 0x44 // ACPI S0 Control
2163#define FCH_AOAC_REG45 0x45 // ACPI S0 State
2164#define FCH_AOAC_REG46 0x46 // ACPI S5 Control
2165#define FCH_AOAC_REG47 0x47 // ACPI S5 State
2166#define FCH_AOAC_REG48 0x48 // LPC Control
2167#define FCH_AOAC_REG49 0x49 // LPC State
2168#define FCH_AOAC_REG4A 0x4A // I_2_C 0 Control
2169#define FCH_AOAC_REG4B 0x4B // I_2_C 0 State
2170#define FCH_AOAC_REG4C 0x4C // I_2_C 1 Control
2171#define FCH_AOAC_REG4D 0x4D // I_2_C 1 State
2172#define FCH_AOAC_REG4E 0x4E // I_2_C 2 Control
2173#define FCH_AOAC_REG4F 0x4F // I_2_C 2 State
2174#define FCH_AOAC_REG50 0x50 // I_2_C 3 Control
2175#define FCH_AOAC_REG51 0x51 // I_2_C 3 State
2176
2177#define FCH_AOAC_REG56 0x56 // UART0 Control
2178#define FCH_AOAC_REG57 0x57 // UART0 State
2179#define FCH_AOAC_REG58 0x58 // UART1 Control
2180#define FCH_AOAC_REG59 0x59 // UART1 State
2181
2182#define FCH_AOAC_REG5E 0x5E // SATA Control
2183#define FCH_AOAC_REG5F 0x5F // SATA State
2184
2185#define FCH_AOAC_REG62 0x62 // AMBA Control
2186#define FCH_AOAC_REG63 0x63 // AMBA State
2187#define FCH_AOAC_REG64 0x64 // USB2 Control
2188#define FCH_AOAC_REG65 0x65 // USB2 State
2189
2190#define FCH_AOAC_REG6E 0x6E // USB3 Control
2191#define FCH_AOAC_REG6F 0x6F // USB3 State
2192#define FCH_AOAC_REG70 0x70 // SD Control
2193#define FCH_AOAC_REG71 0x71 // SD State
2194
2195#define FCH_AOAC_REG76 0x76 // eSPI Control
2196#define FCH_AOAC_REG77 0x77 // eSPI State
2197
2198#define FCH_AOAC_REG7A 0x7A // IMC Control
2199#define FCH_AOAC_REG7B 0x7B // IMC State
2200#define FCH_AOAC_REG7C 0x7C // NB Control
2201#define FCH_AOAC_REG7D 0x7D // NB State
2202#define FCH_AOAC_REG7E 0x7E // APU Control
2203#define FCH_AOAC_REG7F 0x7F // APU State
2204#define FCH_AOAC_REG80 0x80 //
2205#define FCH_AOAC_REG84 0x84 //
2206#define FCH_AOAC_REG88 0x88 //
2207#define FCH_AOAC_REG8C 0x8C //
2208#define FCH_AOAC_REG90 0x90 //
2209#define FCH_AOAC_REG94 0x94 //
2210#define FCH_AOAC_REG98 0x98 //
2211#define FCH_AOAC_REG9C 0x9C //
2212#define FCH_AOAC_REGA0 0xA0 //
2213#define FCH_AOAC_REGA4 0xA4 //
2214#define FCH_AOAC_REGA8 0xA8 //
2215#define FCH_AOAC_REGAC 0xAC //
2216#define FCH_AOAC_REGB0 0xB0 //
2217#define FCH_AOAC_REGB4 0xB4 //
2218#define FCH_AOAC_REGB8 0xB8 //
2219#define FCH_AOAC_REGBC 0xBC //
2220#define FCH_AOAC_REGC0 0xC0 //
2221#define FCH_AOAC_REGC4 0xC4 //
2222#define FCH_AOAC_REGC8 0xC8 //
2223#define FCH_AOAC_REGCC 0xCC //
2224#define FCH_AOAC_REGD0 0xD0 //
2225#define FCH_AOAC_REGD4 0xD4 //
2226#define FCH_AOAC_REGD8 0xD8 //
2227#define FCH_AOAC_REGDC 0xDC //
2228#define FCH_AOAC_REGE0 0xE0 //
2229#define FCH_AOAC_REGE4 0xE4 //
2230#define FCH_AOAC_REGE8 0xE8 //
2231#define FCH_AOAC_REGEC 0xEC //
2232#define FCH_AOAC_REGF0 0xF0 //
2233#define FCH_AOAC_REGF4 0xF4 //
2234#define FCH_AOAC_REGF8 0xF8 //
2235#define FCH_AOAC_REGFC 0xFC //
2236#define FCH_AOACx98S013_DEBUG 0xFED81E98ul //
2237#define FCH_AOACx98S013_DEBUG_BYPASS_SHDW_TMR (1 << 8)
2238#define FCH_AOACx98S013_DEBUG_BYPASS_SHDW_REG (1 << 9)
2239//Set S0I3_BypassShdwTmr in AOAC offset 0x98 bit 8 to 0
2240//Set S0I3_BypassShdwReg in AOAC offset 0x98 bit 9 to 1
2241
2242#define FCH_AOACx9CS013_TIMER_CONTROL 0xFED81E9Cul //
2243#define FCH_AOACx9CS013_TIMER_CONTROL_SHADOW_HPET_EN (1 << 0)
2244#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_UNIT (1 << 2)
2245#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_MASK (0xff << 8)
2246#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_VALUE (0x23 << 8)
2247//Set ShadowHPETEn in AOAC offset 0x9C bit 0 to 1
2248//Set EarlyCountUnit in AOAC offset 0x9C bit 2 to 1
2249//Program EarlyCount in AOAC offset 0x9C bit[15:8]. (please set 0x23 for now)
2250
2251
2252#define FCH_AL2AHBx10_CONTROL 0xFEDC0010ul //
2253#define FCH_AL2AHBx10_CONTROL_CLOCK_GATE_EN (1 << 1)
2254
2255#define FCH_AL2AHBx30_HCLK_CONTROL 0xFEDC0030ul //
2256#define FCH_AL2AHBx30_HCLK_CONTROL_CLOCK_GATE_EN (1 << 1)
2257
2258#define FCH_IOMAP_REG00 0x000 // Dma_C 0
2259#define FCH_IOMAP_REG02 0x002 // Dma_C 1
2260#define FCH_IOMAP_REG04 0x004 // Dma_C 2
2261#define FCH_IOMAP_REG06 0x006 // Dma_C 3
2262#define FCH_IOMAP_REG08 0x008 // Dma_Status
2263#define FCH_IOMAP_REG09 0x009 // Dma_WriteRest
2264#define FCH_IOMAP_REG0A 0x00A // Dma_WriteMask
2265#define FCH_IOMAP_REG0B 0x00B // Dma_WriteMode
2266#define FCH_IOMAP_REG0C 0x00C // Dma_Clear
2267#define FCH_IOMAP_REG0D 0x00D // Dma_MasterClr
2268#define FCH_IOMAP_REG0E 0x00E // Dma_ClrMask
2269#define FCH_IOMAP_REG0F 0x00F // Dma_AllMask
2270#define FCH_IOMAP_REG20 0x020 // IntrCntrlReg1
2271#define FCH_IOMAP_REG21 0x021 // IntrCntrlReg2
2272#define FCH_IOMAP_REG40 0x040 // TimerC0
2273#define FCH_IOMAP_REG41 0x041 // TimerC1
2274#define FCH_IOMAP_REG42 0x042 // TimerC2
2275#define FCH_IOMAP_REG43 0x043 // Tmr1CntrlWord
2276#define FCH_IOMAP_REG61 0x061 // Nmi_Status
2277#define FCH_IOMAP_REG70 0x070 // Nmi_Enable
2278#define FCH_IOMAP_REG71 0x071 // RtcDataPort
2279#define FCH_IOMAP_REG72 0x072 // AlternatRtcAddrPort
2280#define FCH_IOMAP_REG73 0x073 // AlternatRtcDataPort
2281#define FCH_IOMAP_REG80 0x080 // Dma_Page_Reserved0
2282#define FCH_IOMAP_REG81 0x081 // Dma_PageC2
2283#define FCH_IOMAP_REG82 0x082 // Dma_PageC3
2284#define FCH_IOMAP_REG83 0x083 // Dma_PageC1
2285#define FCH_IOMAP_REG84 0x084 // Dma_Page_Reserved1
2286#define FCH_IOMAP_REG85 0x085 // Dma_Page_Reserved2
2287#define FCH_IOMAP_REG86 0x086 // Dma_Page_Reserved3
2288#define FCH_IOMAP_REG87 0x087 // Dma_PageC0
2289#define FCH_IOMAP_REG88 0x088 // Dma_Page_Reserved4
2290#define FCH_IOMAP_REG89 0x089 // Dma_PageC6
2291#define FCH_IOMAP_REG8A 0x08A // Dma_PageC7
2292#define FCH_IOMAP_REG8B 0x08B // Dma_PageC5
2293#define FCH_IOMAP_REG8C 0x08C // Dma_Page_Reserved5
2294#define FCH_IOMAP_REG8D 0x08D // Dma_Page_Reserved6
2295#define FCH_IOMAP_REG8E 0x08E // Dma_Page_Reserved7
2296#define FCH_IOMAP_REG8F 0x08F // Dma_Refres
2297#define FCH_IOMAP_REG92 0x092 // FastInit
2298#define FCH_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1
2299#define FCH_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2
2300#define FCH_IOMAP_REGC0 0x0C0 // Dma2_C4Addr
2301#define FCH_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt
2302#define FCH_IOMAP_REGC4 0x0C4 // Dma2_C5Addr
2303#define FCH_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt
2304#define FCH_IOMAP_REGC8 0x0C8 // Dma2_C6Addr
2305#define FCH_IOMAP_REGCA 0x0CA // Dma2_C6Cnt
2306#define FCH_IOMAP_REGCC 0x0CC // Dma2_C7Addr
2307#define FCH_IOMAP_REGCE 0x0CE // Dma2_C7Cnt
2308#define FCH_IOMAP_REGD0 0x0D0 // Dma_Status
2309#define FCH_IOMAP_REGD2 0x0D2 // Dma_WriteRest
2310#define FCH_IOMAP_REGD4 0x0D4 // Dma_WriteMask
2311#define FCH_IOMAP_REGD6 0x0D6 // Dma_WriteMode
2312#define FCH_IOMAP_REGD8 0x0D8 // Dma_Clear
2313#define FCH_IOMAP_REGDA 0x0DA // Dma_Clear
2314#define FCH_IOMAP_REGDC 0x0DC // Dma_ClrMask
2315#define FCH_IOMAP_REGDE 0x0DE // Dma_ClrMask
2316#define FCH_IOMAP_REGED 0x0ED // DUMMY IO PORT
2317#define FCH_IOMAP_REGF0 0x0F0 // NCP_Error
2318#define FCH_IOMAP_REG40B 0x040B // DMA1_Extend
2319#define FCH_IOMAP_REG4D0 0x04D0 // IntrEdgeControl
2320#define FCH_IOMAP_REG4D6 0x04D6 // DMA2_Extend
2321#define FCH_IOMAP_REGC00 0x0C00 // Pci_Intr_Index
2322#define FCH_IOMAP_REGC01 0x0C01 // Pci_Intr_Data
2323#define FCH_IOMAP_REGC14 0x0C14 // Pci_Error
2324#define FCH_IOMAP_REGC50 0x0C50 // CMIndex
2325#define FCH_IOMAP_REGC51 0x0C51 // CMData
2326#define FCH_IOMAP_REGC52 0x0C52 // GpmPort
2327#define FCH_IOMAP_REGC6F 0x0C6F // Isa_Misc
2328#define FCH_IOMAP_REGCD0 0x0CD0 // PMio2_Index
2329#define FCH_IOMAP_REGCD1 0x0CD1 // PMio2_Data
2330#define FCH_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index
2331#define FCH_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data
2332#define FCH_IOMAP_REGCD6 0x0CD6 // PM_Index
2333#define FCH_IOMAP_REGCD7 0x0CD7 // PM_Data
2334#define FCH_IOMAP_REGCF9 0x0CF9 // CF9Rst reg
2335
2336#define FCH_IRQ_INTA 0x00 // INTA#
2337#define FCH_IRQ_INTB 0x01 // INTB#
2338#define FCH_IRQ_INTC 0x02 // INTC#
2339#define FCH_IRQ_INTD 0x03 // INTD#
2340#define FCH_IRQ_INTE 0x04 // INTE#
2341#define FCH_IRQ_INTF 0x05 // INTF#
2342#define FCH_IRQ_INTG 0x06 // INTG#
2343#define FCH_IRQ_INTH 0x07 // INTH#
2344#define FCH_IRQ_SCI 0x10 // SCI
2345#define FCH_IRQ_SMBUS0 0x11 // SMBUS0
2346#define FCH_IRQ_ASF 0x12 // ASF
2347#define FCH_IRQ_HDAUDIO 0x13 // HD Audio
2348#define FCH_IRQ_FC 0x14 // FC
2349#define FCH_IRQ_GEC 0x15 // GEC
2350#define FCH_IRQ_SD 0x17 // SD
2351#define FCH_IRQ_IMCINT0 0x20 // IMC INT0
2352#define FCH_IRQ_IMCINT1 0x21 // IMC INT1
2353#define FCH_IRQ_IMCINT2 0x22 // IMC INT2
2354#define FCH_IRQ_IMCINT3 0x23 // IMC INT3
2355#define FCH_IRQ_IMCINT4 0x24 // IMC INT4
2356#define FCH_IRQ_IMCINT5 0x25 // IMC INT5
2357#define FCH_IRQ_USB18INTA 0x30 // Dev 18 (USB) INTA#
2358#define FCH_IRQ_USB18INTB 0x31 // Dev 18 (USB) INTB#
2359#define FCH_IRQ_USB19INTA 0x32 // Dev 19 (USB) INTA#
2360#define FCH_IRQ_USB19INTB 0x33 // Dev 19 (USB) INTB#
2361#define FCH_IRQ_USB22INTA 0x34 // Dev 22 (USB) INTA#
2362#define FCH_IRQ_USB22INTB 0x35 // Dev 22 (USB) INTB#
2363#define FCH_IRQ_USB20INTC 0x36 // Dev 20 (USB) INTC#
2364#define FCH_IRQ_IDE 0x40 // IDE pci interrupt
2365#define FCH_IRQ_SATA 0x41 // SATA pci interrupt
2366#define FCH_IRQ_GPPINT0 0x50 // Gpp Int0
2367#define FCH_IRQ_GPPINT1 0x51 // Gpp Int1
2368#define FCH_IRQ_GPPINT2 0x52 // Gpp Int2
2369#define FCH_IRQ_GPPINT3 0x53 // Gpp Int3
2370#define FCH_IRQ_GPIO 0x62 // GPIO Controller
2371#define FCH_IRQ_I2C0 0x70 // I2C0 Controller
2372#define FCH_IRQ_I2C1 0x71 // I2C1 Controller
2373#define FCH_IRQ_I2C2 0x72 // I2C2 Controller
2374#define FCH_IRQ_I2C3 0x73 // I2C3 Controller
2375#define FCH_IRQ_UART0 0x74 // UART0 Controller
2376#define FCH_IRQ_UART1 0x75 // UART1 Controller
2377#define FCH_IRQ_IOAPIC 0x80 // Select IRQ routing to IoApic mode
2378#define FCH_IRQ_PIC 0x00 // Select IRQ routing to PIC mode
2379
2380#define FCH_IRQ_INTERNAL_SHARE 0x07 // Fch Internal Shared IRQ
2381#define FCH_IRQ_GPIO_IRQ FCH_IRQ_INTERNAL_SHARE
2382#define FCH_IRQ_I2C0_IRQ 3
2383#define FCH_IRQ_I2C1_IRQ 15
2384#define FCH_IRQ_I2C2_IRQ 6
2385#define FCH_IRQ_I2C3_IRQ 14
2386#define FCH_IRQ_UART0_IRQ 10
2387#define FCH_IRQ_UART1_IRQ 11
2388
2389
2390#define FCH_SPI_MMIO_REG00 0x00 //SPI_
2391#define FCH_SPI_OPCODE 0x000000FFl //
2392#define FCH_SPI_TX_COUNT 0x00000F00l //
2393#define FCH_SPI_RX_COUNT 0x0000F000l //
2394#define FCH_SPI_EXEC_OPCODE 0x00010000l //
2395#define FCH_SPI_FIFO_PTR_CRL 0x00100000l //
2396#define FCH_SPI_FIFO_PTR_INC 0x00200000l //
2397#define FCH_SPI_BUSY 0x80000000l //
2398#define FCH_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register
2399#define FCH_SPI_PARAMETER 0x000000FFl //
2400#define FCH_SPI_FIFO_PTR 0x00000700l //
2401#define FCH_SPI_BYTE_PROGRAM 0xFF000000l //
2402#define FCH_SPI_MMIO_REG1C 0x1C //
2403#define FCH_SPI_RETRY_TIMES 0x3 //
2404
2405#define FCH_SPI_MMIO_REG1D 0x1D //
2406#define FCH_SPI_MMIO_REG1E 0x1E //
2407#define FCH_SPI_MMIO_REG1F 0x1F //
2408#define FCH_SPI_MMIO_REG4E 0x4E //
2409
2410#define FCH_SPI_MMIO_REG1F_X05_TX_BYTE_COUNT 0x05 //
2411#define FCH_SPI_MMIO_REG1F_X06_RX_BYTE_COUNT 0x06 //
2412
2413#define FCH_SPI_MMIO_REG20 0x20 //
2414#define FCH_SPI_MMIO_REG22 0x22 //
2415#define FCH_SPI_MMIO_REG2C 0x2C //
2416#define FCH_SPI_MMIO_REG38 0x38 //
2417#define FCH_SPI_MMIO_REG3C 0x3C //
2418
2419#define FCH_SPI_MMIO_REG45_CMDCODE 0x45 //
2420#define FCH_SPI_MMIO_REG47_CMDTRIGGER 0x47 //
2421#define FCH_SPI_MMIO_REG48_TXBYTECOUNT 0x48 //
2422#define FCH_SPI_MMIO_REG4B_RXBYTECOUNT 0x4B //
2423#define FCH_SPI_MMIO_REG4C_SPISTATUS 0x4C //
2424#define FCH_SPI_MMIO_REG80_FIFO 0x80 //
2425
2426#define FCH_SPI_MODE_FAST 0x7 //
2427#define FCH_SPI_MODE_NORMAL 0x6 //
2428#define FCH_SPI_MODE_QUAL_144 0x5 //
2429#define FCH_SPI_MODE_QUAL_122 0x4 //
2430#define FCH_SPI_MODE_QUAL_114 0x3 //
2431#define FCH_SPI_MODE_QUAL_112 0x2 //
2432
2433#define FCH_SPI_DEVICE_MODE_DIS 0x7 //
2434#define FCH_SPI_DEVICE_MODE_144 0x4 //
2435#define FCH_SPI_DEVICE_MODE_114 0x3 //
2436#define FCH_SPI_DEVICE_MODE_122 0x2 //
2437#define FCH_SPI_DEVICE_MODE_112 0x1 //
2438#define FCH_SPI_DEVICE_MODE_FAST 0x0 //
2439
2440#define FCH_SPI_SPEED_16M 0x4 //
2441#define FCH_SPI_SPEED_22M 0x3 //
2442#define FCH_SPI_SPEED_33M 0x2 //
2443#define FCH_SPI_SPEED_66M 0x1 //
2444#define FCH_SPI_SPEED_100M 0x5 //
2445
2446#define AMD_NB_REG78 0x78
2447#define AMD_NB_SCRATCH AMD_NB_REG78
2448#define MailBoxPort 0x3E
2449
2450#define MAX_LT_POLLINGS 0x4000
2451#define SMI_TIMER_ENABLE BIT15
2452
2453#define ACPIMMIO32(x) (*(volatile UINT32*)(UINTN)(x))
2454#define ACPIMMIO16(x) (*(volatile UINT16*)(UINTN)(x))
2455#define ACPIMMIO8(x) (*(volatile UINT8*)(UINTN)(x))
2456
2457#define U3PLL_LOCK BIT7
2458#define U3PLL_RESET BIT8
2459#define U3PHY_RESET BIT9
2460#define U3CORE_RESET BIT10
2461#define XHC0_FUNC_RESET BIT11
2462#define XHC1_FUNC_RESET BIT12
2463
2464#define XHCI_ACPI_MMIO_AMD_REG00 0x00
2465#define XHCI_ACPI_MMIO_AMD_REG04 0x04
2466#define XHCI_ACPI_MMIO_AMD_REG08 0x08
2467#define XHCI_ACPI_MMIO_AMD_REG10 0x10
2468#define XHCI_ACPI_MMIO_AMD_REG14 0x14
2469#define XHCI_ACPI_MMIO_AMD_REG20 0x20
2470#define XHCI_ACPI_MMIO_AMD_REG24 0x24
2471#define XHCI_ACPI_MMIO_AMD_REG28 0x28
2472#define XHCI_ACPI_MMIO_AMD_REG30 0x30
2473#define XHCI_ACPI_MMIO_AMD_REG40 0x40
2474#define XHCI_ACPI_MMIO_AMD_REG48 0x48 // USB3.0_Ind_REG Index
2475#define XHCI_ACPI_MMIO_AMD_REG4C 0x4C // USB2.0_Ind_REG Data
2476#define XHCI_ACPI_MMIO_AMD_REG8C 0x8C
2477#define XHCI_ACPI_MMIO_AMD_REG90 0x90 // adaptation timer settings
2478#define XHCI_ACPI_MMIO_AMD_REG98 0x98
2479#define XHCI_ACPI_MMIO_AMD_REGA0 0xA0 // BAR 0
2480#define XHCI_ACPI_MMIO_AMD_REGA4 0xA4 // BAR 1
2481#define XHCI_ACPI_MMIO_AMD_REGA8 0xA8 // BAR 2
2482#define XHCI_ACPI_MMIO_AMD_REGB0 0xB0 // SPI_Valid_Base.
2483#define XHCI_ACPI_MMIO_AMD_REGC0 0xC0 // Firmware starting offset for coping
2484#define XHCI_ACPI_MMIO_AMD_REGB4 0xB4
2485#define XHCI_ACPI_MMIO_AMD_REGD0 0xD0
2486
2487#define FCH_XHCI_REG48 0x48 // XHCI IND_REG Index registers
2488#define FCH_XHCI_REG4C 0x4C // XHCI IND_REG Data registers
2489
2490#define FCH_XHCI_IND60_BASE 0x40000000ul //
2491
2492#define FCH_XHCI_IND60_REG00 FCH_XHCI_IND60_BASE + 0x00 //
2493#define FCH_XHCI_IND60_REG04 FCH_XHCI_IND60_BASE + 0x04 //
2494#define FCH_XHCI_IND60_REG08 FCH_XHCI_IND60_BASE + 0x08 //
2495#define FCH_XHCI_IND60_REG0C FCH_XHCI_IND60_BASE + 0x0C //
2496#define FCH_XHCI_IND60_REG18 FCH_XHCI_IND60_BASE + 0x18 //
2497#define FCH_XHCI_IND60_REG48 FCH_XHCI_IND60_BASE + 0x48 //
2498#define FCH_XHCI_IND60_REG50 FCH_XHCI_IND60_BASE + 0x50 //
2499#define FCH_XHCI_IND60_REG54 FCH_XHCI_IND60_BASE + 0x54 //
2500#define FCH_XHCI_IND60_REG58 FCH_XHCI_IND60_BASE + 0x58 //
2501#define FCH_XHCI_IND60_REG5C FCH_XHCI_IND60_BASE + 0x5C //
2502#define FCH_XHCI_IND60_REG68 FCH_XHCI_IND60_BASE + 0x68 //
2503#define FCH_XHCI_IND60_REG6C FCH_XHCI_IND60_BASE + 0x6C //
2504
2505#define FCH_XHCI_IND_REG00 0x00 //
2506#define FCH_XHCI_IND_REG04 0x04 //
2507#define FCH_XHCI_IND_REG48 0x48 //
2508#define FCH_XHCI_IND_REG54 0x54 //
2509#define FCH_XHCI_IND_REG88 0x88 //
2510#define FCH_XHCI_IND_REG94 0x94 // adaptation mode settings
2511#define FCH_XHCI_IND_REG98 0x98 // CR phase and frequency filter settings
2512#define FCH_XHCI_IND_REGC8 0xC8 //
2513#define FCH_XHCI_IND_REGD4 0xD4 // adaptation mode settings
2514#define FCH_XHCI_IND_REGD8 0xD8 // CR phase and frequency filter settings
2515#define FCH_XHCI_IND_REG100 0x100 //
2516#define FCH_XHCI_IND_REG120 0x120 //
2517#define FCH_XHCI_IND_REG128 0x128 //
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]2518#define FCH_XHCI_IND_REG140 0x140 //
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]2519#define FCH_XHCI_IND_REG200 0x200 //
2520#define FCH_XHCI_IND_REG240 0x240 //
2521#define FCH_XHCI_IND_REG280 0x280 //
2522#define FCH_XHCI_IND_REG2C0 0x2C0 //
2523#define MAX_XHCI_PORTS 0x04
2524
2525//SMBUS
2526#define FCH_SMB_IOREG00 0x00 // SMBusStatus
2527#define FCH_SMB_IOREG01 0x01 // SMBusSlaveStatus
2528#define FCH_SMB_IOREG02 0x02 // SMBusControl
2529#define FCH_SMB_IOREG03 0x03 // SMBusHostCmd
2530#define FCH_SMB_IOREG04 0x04 // SMBusAddress
2531#define FCH_SMB_IOREG05 0x05 // SMBusData0
2532#define FCH_SMB_IOREG06 0x06 // SMBusData1
2533#define FCH_SMB_IOREG07 0x07 // SMBusBlockData
2534#define FCH_SMB_IOREG08 0x08 // SMBusSlaveControl
2535#define FCH_SMB_IOREG14 0x14 // SMBusAutoPoll
2536#define FCH_SMB_IOREG16 0x16 // SMBusPausePoll
2537#define FCH_SMB_IOREG17 0x17 // SMBusHostCmd2
2538
2539#define FCH_SMB_CMD_QUICK 0x00 << 2 // Quick Read or Write
2540#define FCH_SMB_CMD_BYTE 0x01 << 2 // Byte Read or Write
2541#define FCH_SMB_CMD_BYTE_DATA 0x02 << 2 // Byte Data Read or Write
2542#define FCH_SMB_CMD_WORD_DATA 0x03 << 2 // Word Data Read or Write
2543#define FCH_SMB_CMD_BLOCK 0x05 << 2 // Block Read or Write
2544
2545#define FCH_SMB_ALL_HOST_STATUS 0x1f // HostBusy+SMBInterrupt+DeviceErr+BusCollision+Failed
2546#define FCH_SMB_CMD_BYTE_DATA_START 0x48 // Byte Data Read or Write
2547#define FCH_SMB_CMD_START BIT6
2548#define FCH_SMB_READ_ENABLE BIT0
2549#define FCH_SMB_AUTO_POLL_EN BIT0
2550#define FCH_SMB_POLL2BYTE BIT7
2551
2552#define SBTSI_ADDR 0x98
2553#define SBTSI_REG01 0x01
2554#define SBTSI_REG09 0x09
2555#define SBTSI_REG10 0x10
2556#define SBTSI_READORDER BIT5
2557
Subrata Banik8e6d5f22020-08-30 13:51:44 +0530[diff] [blame]2558#define FCH_EC_ENTER_CONFIG 0x5A
2559#define FCH_EC_EXIT_CONFIG 0xA5
2560#define FCH_EC_REG07 0x07
2561#define FCH_EC_REG30 0x30
2562#define FCH_EC_REG60 0x60
2563#define FCH_EC_REG61 0x61
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]2564
2565#define FCH_IMC_ROMSIG 0x55aa55aaul
2566
2567#define SPI_HEAD_LENGTH 0x0E
2568#define SPI_BAR0_VLD 0x01
2569#define SPI_BASE0 (0x00 << 7)
2570#define SPI_BAR1_VLD (0x01 << 8)
2571#define SPI_BASE1 (SPI_HEAD_LENGTH << 10)
2572#define SPI_BAR2_VLD (0x01 << 16)
2573#define SPI_BASE2(x) ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
2574
2575#define FW_TO_SIGADDR_OFFSET 0x0C
2576#define BCD_ADDR_OFFSET 0x02
2577#define BCD_SIZE_OFFSET 0x04
2578#define FW_ADDR_OFFSET 0x06
2579#define FW_SIZE_OFFSET 0x08
2580#define ACD_ADDR_OFFSET 0x0A
2581#define ACD_SIZE_OFFSET 0x0C
2582#define XHC_BOOT_RAM_SIZE 0x8000
2583
2584#define PKT_DATA_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
2585#define PKT_LEN_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
2586#define PKT_CTRL_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
2587#define EFUS_DAC_ADJUSTMENT_CONTROL 0x850A8ul
2588#define BGADJ 0x1F
2589#define DACADJ 0x1B
2590#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA (BGADJ + (DACADJ << 8) + BIT16 )
2591
2592#define KABINI_OSC_OUT_CLOCK_SEL_48MHz 0x02
2593#define KABINI_OSC_OUT_CLOCK_SEL_25MHz 0x01
2594
2595#define KERN_OSC_OUT_CLOCK_SEL_48MHz 0x02
2596#define KERN_OSC_OUT_CLOCK_SEL_25MHz 0x01
2597
2598#define RTC_WORKAROUND_SECOND 0x00
2599#define RTC_VALID_SECOND_VALUE 0x59
2600#define RTC_SECOND_RESET_VALUE 0x30
2601#define RTC_SECOND_LOWER_NIBBLE 0x0F
2602#define RTC_VALID_SECOND_VALUE_LN 0x09
2603
2604#ifndef FCH_DEADLOOP
2605 #define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
2606#endif
2607
2608#define OHCI_ARB_REGQ_VLD_EN BIT2
2609
2610#define HCEx40_Control 0xFED80040ul
2611#define HCEx44_Input 0xFED80044ul
2612#define HCEx48_Output 0xFED80048ul
2613#define HCEx4C_Status 0xFED8004Cul
2614#define HCEx50_IntrEn 0xFED80050ul
2615#define EmulationSmiEn BIT4
2616
2617#define FCH_PMx08_PciControl 0xFED80308ul // PCI Control
2618#define FCH_PMx08_PciControl_ShutDownOption BIT20
2619
2620#define FCH_PMxD2_PmioDebug 0xFED803D2ul // Pmio Debug
2621#define FCH_PMxD6_Imc_Gating 0xFED803D6ul // IMC Gating
2622#define FCH_PMxEC_LpcGating 0xFED803ECul // LPC Gating
2623