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review.coreboot.org / coreboot / 7687e7767f2d2321b57fa8eab68b7e954e57ad42 / . / src / vendorcode / amd / pi / 00670F00 / Proc / Fch / Common / FchCommonCfg.h
blob: 8e52e1a29ffae0c78311d491e7c117306258976d [file] [log] [blame]
Martin Roth7687e772023-08-22 16:32:20 -0600[diff] [blame^]1/* SPDX-License-Identifier: BSD-3-Clause */
2
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]3/* $NoKeywords:$ */
4/**
5 * @file
6 *
7 * FCH Function Support Definition
8 *
9 *
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: FCH
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]14 * @e \$Revision$ @e \$Date$
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]15 *
16 */
17 /*****************************************************************************
18 *
Marc Jones823dbde2018-01-25 17:05:46 -0700[diff] [blame]19 * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *
44 ***************************************************************************/
Martin Rothae016342017-11-16 22:46:56 -0700[diff] [blame]45
46#include <check_for_wrapper.h>
47
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]48#ifndef _FCH_COMMON_CFG_H_
49#define _FCH_COMMON_CFG_H_
50
51#pragma pack (push, 1)
52
53//-----------------------------------------------------------------------------
54// FCH DEFINITIONS AND MACROS
55//-----------------------------------------------------------------------------
56
57//
58// FCH Component Data Structure Definitions
59//
60
61/// PCI_ADDRESS - PCI access structure
62#define PCI_ADDRESS(bus, dev, func, reg) \
63 (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
64
65#define CPUID_FMF 0x80000001ul // Family Model Features information
66///
67/// - Byte Register R/W structure
68///
69typedef struct _REG8_MASK {
70 UINT8 RegIndex; /// RegIndex - Reserved
71 UINT8 AndMask; /// AndMask - Reserved
72 UINT8 OrMask; /// OrMask - Reserved
73} REG8_MASK;
74
75
76///
77/// PCIE Reset Block
78///
79typedef enum {
80 NbBlock, ///< Reset for NB PCIE
81 FchBlock ///< Reset for FCH GPP
82} RESET_BLOCK;
83
84///
85/// PCIE Reset Operation
86///
87typedef enum {
88 DeassertReset, ///< DeassertRese - Deassert reset
89 AssertReset ///< AssertReset - Assert reset
90} RESET_OP;
91
92
93///
94/// Fch Run Time Parameters
95///
96typedef struct {
97 UINT32 PcieMmioBase; ///< PcieMmioBase
98 UINT32 FchDeviceEnableMap; ///< FchDeviceEnableMap
99 UINT32 FchDeviceD3ColdMap; ///< FchDeviceD3ColdMap
100 UINT16 XHCI_PMx04_XhciFwRomAddr_Rom; ///< XHCI_PMx04_XhciFwRomAddr_Rom
101 UINT32 XHCI_PMx08_xHCI_Firmware_Addr_1_Rom; ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram
102 UINT16 XHCI_PMx04_XhciFwRomAddr_Ram; ///< XHCI_PMx04_XhciFwRomAddr_Rom
103 UINT32 XHCI_PMx08_xHCI_Firmware_Addr_1_Ram; ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram
104 UINT8 SataDevSlpPort0S5Pin; ///< SataDevSlpPort0S5Pin - Reserved
105 UINT8 SataDevSlpPort1S5Pin; ///< SataDevSlpPort1S5Pin - Reserved
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]106 UINT16 FchFlag16; ///< Dummy16 - Reserved
107 UINT32 FchFlag32; ///< Dummy32 - Reserved
108 /// @li <b>0</b> - Carrizo
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]109 UINT32 SdMmioBase; ///< Sd Mmio Base - Reserved
110 UINT32 EhciMmioBase; ///< Ehci Mmio Base - Reserved
111 UINT32 XhciMmioBase; ///< Xhci Mmio Base - Reserved
112 UINT32 SataMmioBase; ///< Sata Mmio Base - Reserved
113} FCH_RUNTIME;
114
115///
116/// SD structure
117///
118typedef struct {
119 SD_MODE SdConfig; ///< SD Mode configuration
120 /// @li <b>00</b> - Disabled
121 /// @li <b>00</b> - AMDA
122 /// @li <b>01</b> - DMA
123 /// @li <b>10</b> - PIO
124 ///
125 UINT8 SdSpeed; ///< SD Speed
126 /// @li <b>0</b> - Low speed
127 /// @li <b>1</b> - High speed
128 ///
129 UINT8 SdBitWidth; ///< SD Bit Width
130 /// @li <b>0</b> - 32BIT clear 23
131 /// @li <b>1</b> - 64BIT, set 23,default
132 ///
133 UINT32 SdSsid; ///< SD Subsystem ID
134 SD_CLOCK_CONTROL SdClockControl; ///< SD Clock Control
135 BOOLEAN SdClockMultiplier; ///< SD Clock Multiplier enable/disable
136 UINT8 SdReTuningMode; ///< SD Re-tuning modes select
137 /// @li <b>0</b> - mode 1
138 /// @li <b>1</b> - mode 2
139 /// @li <b>2</b> - mode 3
140 UINT8 SdHostControllerVersion; ///< SD controller Version
141 /// @li <b>1</b> - SD 2.0
142 /// @li <b>2</b> - SD 3.0
143 UINT8 SdrCapabilities; ///< SDR Capability mode select
144 /// @li <b>00</b> - SDR25/15
145 /// @li <b>01</b> - SDR50
146 /// @li <b>11</b> - SDR104
147 UINT8 SdSlotType; ///< SDR Slot Type select
148 /// @li <b>00</b> - Removable Card Slot
149 /// @li <b>01</b> - Embedded Slot for One Device
150 /// @li <b>10</b> - Shared Bus Slot
151 BOOLEAN SdForce18; ///< SD Force18
152 UINT8 SdDbgConfig; ///< SD Mode configuration
153 /// @li <b>00</b> - Disabled
154 /// @li <b>00</b> - AMDA
155 /// @li <b>01</b> - DMA
156 /// @li <b>10</b> - PIO
157 ///
158} FCH_SD;
159
160///
161/// CODEC_ENTRY - Fch HD Audio OEM Codec structure
162///
163typedef struct _CODEC_ENTRY {
164 UINT8 Nid; /// Nid - Reserved
165 UINT32 Byte40; /// Byte40 - Reserved
166} CODEC_ENTRY;
167
168///
169/// CODEC_TBL_LIST - Fch HD Audio Codec table list
170///
171typedef struct _CODEC_TBL_LIST {
172 UINT32 CodecId; /// CodecID - Codec ID
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]173 const CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]174} CODEC_TBL_LIST;
175
176///
177/// AZALIA_PIN - HID Azalia or GPIO define structure.
178///
179typedef struct _AZALIA_PIN {
180 UINT8 AzaliaSdin0; ///< AzaliaSdin0
181 /// @par
182 /// @li <b>00</b> - GPIO PIN
183 /// @li <b>10</b> - As a Azalia SDIN pin
184
185 UINT8 AzaliaSdin1; ///< AzaliaSdin1
186 /// @par
Paul Menzel30935b62020-10-06 08:53:57 +0200[diff] [blame]187 /// SDIN1 is defined at BIT2 & BIT3
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]188 /// @li <b>00</b> - GPIO PIN
189 /// @li <b>10</b> - As a Azalia SDIN pin
190
191 UINT8 AzaliaSdin2; ///< AzaliaSdin2
192 /// @par
Paul Menzel30935b62020-10-06 08:53:57 +0200[diff] [blame]193 /// SDIN2 is defined at BIT4 & BIT5
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]194 /// @li <b>00</b> - GPIO PIN
195 /// @li <b>10</b> - As a Azalia SDIN pin
196
197 UINT8 AzaliaSdin3; ///< AzaliaSdin3
198 /// @par
Paul Menzel30935b62020-10-06 08:53:57 +0200[diff] [blame]199 /// SDIN3 is defined at BIT6 & BIT7
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]200 /// @li <b>00</b> - GPIO PIN
201 /// @li <b>10</b> - As a Azalia SDIN pin
202} AZALIA_PIN;
203
204///
205/// Azalia structure
206///
207typedef struct {
208 HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration
209 BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability
210 UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID
211 UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
212 /// @par
213 /// @li <b>0</b> - disable
214 /// @li <b>1</b> - enable
215
216 UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
217 /// @par
218 /// Support Front Panel configuration
219 /// @li <b>0</b> - Auto
220 /// @li <b>1</b> - disable
221 /// @li <b>2</b> - enable
222
223 UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
224 /// @par
225 /// Force Front Panel configuration
226 /// @li <b>0</b> - Not Detected
227 /// @li <b>1</b> - Detected
228
229 UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration
230 /// @par
231 /// Azalia Controller Snoop feature Configuration
232 /// @li <b>0</b> - disable
233 /// @li <b>1</b> - enable
234
235 UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */
236
237 AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration
238
239///
240/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer
241///
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]242 const CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]243
244///
245/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
246///
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]247 const VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]248} FCH_AZALIA;
249
250///
251/// _SPI_DEVICE_PROFILE Spi Device Profile structure
252///
253typedef struct _SPI_DEVICE_PROFILE {
254 UINT32 JEDEC_ID; /// JEDEC ID
255 UINT32 RomSize; /// ROM Size
256 UINT32 SectorSize; /// Sector Size
257 UINT16 MaxNormalSpeed; /// Max Normal Speed
258 UINT16 MaxFastSpeed; /// Max Fast Speed
259 UINT16 MaxDualSpeed; /// Max Dual Speed
260 UINT16 MaxQuadSpeed; /// Max Quad Speed
261 UINT8 QeReadRegister; /// QE Read Register
262 UINT8 QeWriteRegister; /// QE Write Register
263 UINT8 QeOperateSize; /// QE Operate Size 1byte/2bytes
264 UINT16 QeLocation; // QE Location in the register
265} SPI_DEVICE_PROFILE;
266
267///
268/// _SPI_CONTROLLER_PROFILE Spi Device Profile structure
269///
270typedef struct _SPI_CONTROLLER_PROFILE {
271// UINT32 SPI_CONTROLLER_ID; /// SPI Controller ID
272 UINT16 FifoSize; /// FIFO Size
273 UINT16 MaxNormalSpeed; /// Max Normal Speed
274 UINT16 MaxFastSpeed; /// Max Fast Speed
275 UINT16 MaxDualSpeed; /// Max Dual Speed
276 UINT16 MaxQuadSpeed; /// Max Quad Speed
277} SPI_CONTROLLER_PROFILE;
278
279///
280/// SPI structure
281///
282typedef struct {
283 BOOLEAN LpcMsiEnable; ///< LPC MSI capability
284 UINT32 LpcSsid; ///< LPC Subsystem ID
285 UINT32 RomBaseAddress; ///< SpiRomBaseAddress
286 /// @par
287 /// SPI ROM BASE Address
288 ///
289 UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency
290 /// @par
291 /// SPI Speed [1.0] - the clock speed for non-fast read command
292 /// @li <b>00</b> - 66Mhz
293 /// @li <b>01</b> - 33Mhz
294 /// @li <b>10</b> - 22Mhz
295 /// @li <b>11</b> - 16.5Mhz
296 ///
297 UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature
298 /// SPIFastSpeed [1.0] - the clock speed for Fast Speed Feature
299 /// @li <b>00</b> - 66Mhz
300 /// @li <b>01</b> - 33Mhz
301 /// @li <b>10</b> - 22Mhz
302 /// @li <b>11</b> - 16.5Mhz
303 ///
304 UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed
305 /// @par
306 /// WriteSpeed [1.0] - the clock speed for Spi write command
307 /// @li <b>00</b> - 66Mhz
308 /// @li <b>01</b> - 33Mhz
309 /// @li <b>10</b> - 22Mhz
310 /// @li <b>11</b> - 16.5Mhz
311 ///
312 UINT8 SpiMode; ///< SpiMode - Spi Mode Setting
313 /// @par
314 /// @li <b>101</b> - Qual-io 1-4-4
315 /// @li <b>100</b> - Dual-io 1-2-2
316 /// @li <b>011</b> - Qual-io 1-1-4
317 /// @li <b>010</b> - Dual-io 1-1-2
318 /// @li <b>111</b> - FastRead
319 /// @li <b>110</b> - Normal
320 ///
321 UINT8 AutoMode; ///< AutoMode - Spi Auto Mode
322 /// @par
323 /// SPI Auto Mode
324 /// @li <b>0</b> - Disabled
325 /// @li <b>1</b> - Enabled
326 ///
327 UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode
328 /// @par
329 /// SPI Burst Write
330 /// @li <b>0</b> - Disabled
331 /// @li <b>1</b> - Enabled
332 BOOLEAN LpcClk0; ///< Lclk0En - LPCCLK0
333 /// @par
334 /// LPC Clock 0 mode
335 /// @li <b>0</b> - forced to stop
336 /// @li <b>1</b> - functioning with CLKRUN protocol
337 BOOLEAN LpcClk1; ///< Lclk1En - LPCCLK1
338 /// @par
339 /// LPC Clock 1 mode
340 /// @li <b>0</b> - forced to stop
341 /// @li <b>1</b> - functioning with CLKRUN protocol
342// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
343// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
344// UINT8 SpiProtectEn0_1d_34; ///
345 UINT8 SPI100_Enable; ///< Spi 100 Enable
346 SPI_DEVICE_PROFILE SpiDeviceProfile; ///< Spi Device Profile
347} FCH_SPI;
348
349
350///
351/// IDE structure
352///
353typedef struct {
354 BOOLEAN IdeEnable; ///< IDE function switch
355 BOOLEAN IdeMsiEnable; ///< IDE MSI capability
356 UINT32 IdeSsid; ///< IDE controller Subsystem ID
357} FCH_IDE;
358
359///
360/// IR Structure
361///
362typedef struct {
363 IR_CONFIG IrConfig; ///< IrConfig
364 UINT8 IrPinControl; ///< IrPinControl
365} FCH_IR;
366
367
368///
369/// PCI Bridge Structure
370///
371typedef struct {
372 BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability
373 UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID
374 UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used
375 /// @li <b>0</b> - disable
376 /// @li <b>1</b> - enable
377 ///
378 UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override
379 BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality
380 /// @li <b>0</b> - disable
381 /// @li <b>1</b> - enable
382 ///
383} FCH_PCIB;
384
385
386///
387/// - SATA Phy setting structure
388///
389typedef struct _SATA_PHY_SETTING {
390 UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved
391 UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved
392} SATA_PHY_SETTING;
393
394///
395/// SATA main setting structure
396///
397typedef struct _SATA_ST {
398 UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode
399 BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function
400 /// @par
401 /// Sata Controller
402 /// @li <b>0</b> - disable
403 /// @li <b>1</b> - enable
404 ///
405 UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */
406 BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode
407 /// @par
408 /// Sata Controller Set to Max Gen2 mode
409 /// @li <b>0</b> - disable
410 /// @li <b>1</b> - enable
411 ///
412 BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE
413 /// @par
414 /// Sata IDE Controller Combined Mode
415 /// Enable - SATA controller has control over Port0 through Port3,
416 /// IDE controller has control over Port4 and Port7.
417 /// Disable - SATA controller has full control of all 8 Ports
418 /// when operating in non-IDE mode.
419 /// @li <b>0</b> - enable
420 /// @li <b>1</b> - disable
421 ///
422 UINT8 SataClkMode; /// SataClkMode - Reserved
423} SATA_ST;
424
425///
426/// SATA_PORT_ST - SATA PORT structure
427///
428typedef struct _SATA_PORT_ST {
429 UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7
430 /// @li <b>0</b> - disable
431 /// @li <b>1</b> - enable
432 ///
433 BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable
434 BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable
435 BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable
436 BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable
437 BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable
438 BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable
439 BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable
440 BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable
441} SATA_PORT_ST;
442
443///
444///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode
445///
446typedef struct _SATA_PORT_MD {
447 UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7
448 UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
449 UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
450 UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
451 UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
452 UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
453 UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
454 UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
455 UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
456} SATA_PORT_MD;
457///
458/// SATA structure
459///
460typedef struct {
461 BOOLEAN SataMsiEnable; ///< SATA MSI capability
462 UINT32 SataIdeSsid; ///< SATA IDE mode SSID
463 UINT32 SataRaidSsid; ///< SATA RAID mode SSID
464 UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID
465 UINT32 SataAhciSsid; ///< SATA AHCI mode SSID
466
467 SATA_ST SataMode; /// SataMode - Reserved
468 SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0]
469 UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode
470 /// @par
471 /// @li <b>0</b> - Legacy IDE mode
472 /// @li <b>1</b> - Native IDE mode
473 ///
474 UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel
475 /// @par
476 /// @li <b>0</b> - Channel Enable
477 /// @li <b>1</b> - Channel Disable
478 ///
479 UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel
480 /// @par
481 /// @li <b>0</b> - Channel Enable
482 /// @li <b>1</b> - Channel Disable
483 ///
484 UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel
485 /// @par
486 /// @li <b>0</b> - Channel Enable
487 /// @li <b>1</b> - Channel Disable
488 ///
489 UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel
490 /// @par
491 /// @li <b>0</b> - Channel Enable
492 /// @li <b>1</b> - Channel Disable
493 ///
494 UINT8 SataOptionReserved; /// SataOptionReserved - Reserved
495
496 SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
497
498 SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration
499
500 SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode
501
502 UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON
503 UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON
504 UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled
505 UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability
506 UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved
507 UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved
508 UINT8 SataCccSupport; /// SataCccSupport - Reserved
509 UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability
510 UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible
511 UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID
512 UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved
513 UINT8 SataDebugDummy; /// SataDebugDummy - Reserved
514 UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved
515 UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved
516 BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved
517 UINT8 SataSgpio0; /// SataSgpio0 - Reserved
518 UINT8 SataSgpio1; /// SataSgpio1 - Reserved
519 UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved
520 BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved
521
522 SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove
523
524 BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE
525 BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE
526 UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3]
527 BOOLEAN SataRasSupport; /// SataRasSupport - Support RAS function TRUE: Enable FALSE: Disable
528 BOOLEAN SataAhciDisPrefetchFunction; /// SataAhciDisPrefetchFunction - Disable AHCI Prefetch Function Support
529 BOOLEAN SataDevSlpPort0; /// SataDevSlpPort0 - Reserved
530 BOOLEAN SataDevSlpPort1; /// SataDevSlpPort1 - Reserved
531// UINT8 SataDevSlpPort0S5Pin; /// SataDevSlpPort0S5Pin - Reserved
532// UINT8 SataDevSlpPort1S5Pin; /// SataDevSlpPort1S5Pin - Reserved
533 UINT8 SataDbgTX_DRV_STR ; /// TX_DRV_STR - Reserved
534 UINT8 SataDbgTX_DE_EMPH_STR ; /// TX_DE_EMPH_STR - Reserved
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]535 BOOLEAN SataLongTrace[2]; /// Long Trace - Reserved
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]536 UINT32 TempMmio; /// TempMmio - Reserved
537} FCH_SATA;
538
539
540//
541// IMC Message Register Software Interface
542//
543#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
544
545#define MSG_SYS_TO_IMC 0x80
546#define Fun_80 0x80
547#define Fun_81 0x81
548#define Fun_82 0x82
549#define Fun_83 0x83
550#define Fun_84 0x84
551#define Fun_85 0x85
552#define Fun_86 0x86
553#define Fun_87 0x87
554#define Fun_88 0x88
555#define Fun_89 0x89
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]556#define Fun_8B 0x8B
557#define Fun_8C 0x8C
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]558#define Fun_90 0x90
559#define MSG_IMC_TO_SYS 0x81
560#define MSG_REG0 0x82
561#define MSG_REG1 0x83
562#define MSG_REG2 0x84
563#define MSG_REG3 0x85
564#define MSG_REG4 0x86
565#define MSG_REG5 0x87
566#define MSG_REG6 0x88
567#define MSG_REG7 0x89
568#define MSG_REG8 0x8A
569#define MSG_REG9 0x8B
570#define MSG_REGA 0x8C
571#define MSG_REGB 0x8D
572#define MSG_REGC 0x8E
573#define MSG_REGD 0x8F
574
575#define DISABLED 0
576#define ENABLED 1
577
578
579
580///
581/// EC structure
582///
583typedef struct _FCH_EC {
584 UINT8 MsgFun81Zone0MsgReg0; ///<Thermal zone
585 UINT8 MsgFun81Zone0MsgReg1; ///<Thermal zone
586 UINT8 MsgFun81Zone0MsgReg2; ///<Thermal zone control byte 1
587 UINT8 MsgFun81Zone0MsgReg3; ///<Thermal zone control byte 2
588 UINT8 MsgFun81Zone0MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
589 UINT8 MsgFun81Zone0MsgReg5; ///<Hysteresis information
590 UINT8 MsgFun81Zone0MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
591 UINT8 MsgFun81Zone0MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
592 UINT8 MsgFun81Zone0MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
593 UINT8 MsgFun81Zone0MsgReg9; ///<Fan PWM ramping rate in 5ms unit
594//
595// EC LDN9 function 81 zone 1
596//
597 UINT8 MsgFun81Zone1MsgReg0; ///<Thermal zone
598 UINT8 MsgFun81Zone1MsgReg1; ///<Thermal zone
599 UINT8 MsgFun81Zone1MsgReg2; ///<Thermal zone control byte 1
600 UINT8 MsgFun81Zone1MsgReg3; ///<Thermal zone control byte 2
601 UINT8 MsgFun81Zone1MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
602 UINT8 MsgFun81Zone1MsgReg5; ///<Hysteresis information
603 UINT8 MsgFun81Zone1MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
604 UINT8 MsgFun81Zone1MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
605 UINT8 MsgFun81Zone1MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
606 UINT8 MsgFun81Zone1MsgReg9; ///<Fan PWM ramping rate in 5ms unit
607//
608//EC LDN9 function 81 zone 2
609//
610 UINT8 MsgFun81Zone2MsgReg0; ///<Thermal zone
611 UINT8 MsgFun81Zone2MsgReg1; ///<Thermal zone
612 UINT8 MsgFun81Zone2MsgReg2; ///<Thermal zone control byte 1
613 UINT8 MsgFun81Zone2MsgReg3; ///<Thermal zone control byte 2
614 UINT8 MsgFun81Zone2MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
615 UINT8 MsgFun81Zone2MsgReg5; ///<Hysteresis information
616 UINT8 MsgFun81Zone2MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
617 UINT8 MsgFun81Zone2MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
618 UINT8 MsgFun81Zone2MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
619 UINT8 MsgFun81Zone2MsgReg9; ///<Fan PWM ramping rate in 5ms unit
620//
621//EC LDN9 function 81 zone 3
622//
623 UINT8 MsgFun81Zone3MsgReg0; ///<Thermal zone
624 UINT8 MsgFun81Zone3MsgReg1; ///<Thermal zone
625 UINT8 MsgFun81Zone3MsgReg2; ///<Thermal zone control byte 1
626 UINT8 MsgFun81Zone3MsgReg3; ///<Thermal zone control byte 2
627 UINT8 MsgFun81Zone3MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
628 UINT8 MsgFun81Zone3MsgReg5; ///<Hysteresis information
629 UINT8 MsgFun81Zone3MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
630 UINT8 MsgFun81Zone3MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
631 UINT8 MsgFun81Zone3MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
632 UINT8 MsgFun81Zone3MsgReg9; ///<Fan PWM ramping rate in 5ms unit
633//
634//EC LDN9 function 83 zone 0
635//
636 UINT8 MsgFun83Zone0MsgReg0; ///<Thermal zone
637 UINT8 MsgFun83Zone0MsgReg1; ///<Thermal zone
638 UINT8 MsgFun83Zone0MsgReg2; ///<_AC0
639 UINT8 MsgFun83Zone0MsgReg3; ///<_AC1
640 UINT8 MsgFun83Zone0MsgReg4; ///<_AC2
641 UINT8 MsgFun83Zone0MsgReg5; ///<_AC3
642 UINT8 MsgFun83Zone0MsgReg6; ///<_AC4
643 UINT8 MsgFun83Zone0MsgReg7; ///<_AC5
644 UINT8 MsgFun83Zone0MsgReg8; ///<_AC6
645 UINT8 MsgFun83Zone0MsgReg9; ///<_AC7
646 UINT8 MsgFun83Zone0MsgRegA; ///<_CRT
647 UINT8 MsgFun83Zone0MsgRegB; ///<_PSV
648//
649//EC LDN9 function 83 zone 1
650//
651 UINT8 MsgFun83Zone1MsgReg0; ///<Thermal zone
652 UINT8 MsgFun83Zone1MsgReg1; ///<Thermal zone
653 UINT8 MsgFun83Zone1MsgReg2; ///<_AC0
654 UINT8 MsgFun83Zone1MsgReg3; ///<_AC1
655 UINT8 MsgFun83Zone1MsgReg4; ///<_AC2
656 UINT8 MsgFun83Zone1MsgReg5; ///<_AC3
657 UINT8 MsgFun83Zone1MsgReg6; ///<_AC4
658 UINT8 MsgFun83Zone1MsgReg7; ///<_AC5
659 UINT8 MsgFun83Zone1MsgReg8; ///<_AC6
660 UINT8 MsgFun83Zone1MsgReg9; ///<_AC7
661 UINT8 MsgFun83Zone1MsgRegA; ///<_CRT
662 UINT8 MsgFun83Zone1MsgRegB; ///<_PSV
663//
664//EC LDN9 function 83 zone 2
665//
666 UINT8 MsgFun83Zone2MsgReg0; ///<Thermal zone
667 UINT8 MsgFun83Zone2MsgReg1; ///<Thermal zone
668 UINT8 MsgFun83Zone2MsgReg2; ///<_AC0
669 UINT8 MsgFun83Zone2MsgReg3; ///<_AC1
670 UINT8 MsgFun83Zone2MsgReg4; ///<_AC2
671 UINT8 MsgFun83Zone2MsgReg5; ///<_AC3
672 UINT8 MsgFun83Zone2MsgReg6; ///<_AC4
673 UINT8 MsgFun83Zone2MsgReg7; ///<_AC5
674 UINT8 MsgFun83Zone2MsgReg8; ///<_AC6
675 UINT8 MsgFun83Zone2MsgReg9; ///<_AC7
676 UINT8 MsgFun83Zone2MsgRegA; ///<_CRT
677 UINT8 MsgFun83Zone2MsgRegB; ///<_PSV
678//
679//EC LDN9 function 83 zone 3
680//
681 UINT8 MsgFun83Zone3MsgReg0; ///<Thermal zone
682 UINT8 MsgFun83Zone3MsgReg1; ///<Thermal zone
683 UINT8 MsgFun83Zone3MsgReg2; ///<_AC0
684 UINT8 MsgFun83Zone3MsgReg3; ///<_AC1
685 UINT8 MsgFun83Zone3MsgReg4; ///<_AC2
686 UINT8 MsgFun83Zone3MsgReg5; ///<_AC3
687 UINT8 MsgFun83Zone3MsgReg6; ///<_AC4
688 UINT8 MsgFun83Zone3MsgReg7; ///<_AC5
689 UINT8 MsgFun83Zone3MsgReg8; ///<_AC6
690 UINT8 MsgFun83Zone3MsgReg9; ///<_AC7
691 UINT8 MsgFun83Zone3MsgRegA; ///<_CRT
692 UINT8 MsgFun83Zone3MsgRegB; ///<_PSV
693//
694//EC LDN9 function 85 zone 0
695//
696 UINT8 MsgFun85Zone0MsgReg0; ///<Thermal zone
697 UINT8 MsgFun85Zone0MsgReg1; ///<Thermal zone
698 UINT8 MsgFun85Zone0MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
699 UINT8 MsgFun85Zone0MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
700 UINT8 MsgFun85Zone0MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
701 UINT8 MsgFun85Zone0MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
702 UINT8 MsgFun85Zone0MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
703 UINT8 MsgFun85Zone0MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
704 UINT8 MsgFun85Zone0MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
705 UINT8 MsgFun85Zone0MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
706//
707//EC LDN9 function 85 zone 1
708//
709 UINT8 MsgFun85Zone1MsgReg0; ///<Thermal zone
710 UINT8 MsgFun85Zone1MsgReg1; ///<Thermal zone
711 UINT8 MsgFun85Zone1MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
712 UINT8 MsgFun85Zone1MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
713 UINT8 MsgFun85Zone1MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
714 UINT8 MsgFun85Zone1MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
715 UINT8 MsgFun85Zone1MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
716 UINT8 MsgFun85Zone1MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
717 UINT8 MsgFun85Zone1MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
718 UINT8 MsgFun85Zone1MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
719//
720//EC LDN9 function 85 zone 2
721//
722 UINT8 MsgFun85Zone2MsgReg0; ///<Thermal zone
723 UINT8 MsgFun85Zone2MsgReg1; ///<Thermal zone
724 UINT8 MsgFun85Zone2MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
725 UINT8 MsgFun85Zone2MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
726 UINT8 MsgFun85Zone2MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
727 UINT8 MsgFun85Zone2MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
728 UINT8 MsgFun85Zone2MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
729 UINT8 MsgFun85Zone2MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
730 UINT8 MsgFun85Zone2MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
731 UINT8 MsgFun85Zone2MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
732//
733//EC LDN9 function 85 zone 3
734//
735 UINT8 MsgFun85Zone3MsgReg0; ///<Thermal zone
736 UINT8 MsgFun85Zone3MsgReg1; ///<Thermal zone
737 UINT8 MsgFun85Zone3MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
738 UINT8 MsgFun85Zone3MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
739 UINT8 MsgFun85Zone3MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
740 UINT8 MsgFun85Zone3MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
741 UINT8 MsgFun85Zone3MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
742 UINT8 MsgFun85Zone3MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
743 UINT8 MsgFun85Zone3MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
744 UINT8 MsgFun85Zone3MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
745//
746//EC LDN9 function 89 TEMPIN channel 0
747//
748 UINT8 MsgFun89Zone0MsgReg0; ///<Thermal zone
749 UINT8 MsgFun89Zone0MsgReg1; ///<Thermal zone
750 UINT8 MsgFun89Zone0MsgReg2; ///<At DWORD bit 0-7
751 UINT8 MsgFun89Zone0MsgReg3; ///<At DWORD bit 15-8
752 UINT8 MsgFun89Zone0MsgReg4; ///<At DWORD bit 23-16
753 UINT8 MsgFun89Zone0MsgReg5; ///<At DWORD bit 31-24
754 UINT8 MsgFun89Zone0MsgReg6; ///<Ct DWORD bit 0-7
755 UINT8 MsgFun89Zone0MsgReg7; ///<Ct DWORD bit 15-8
756 UINT8 MsgFun89Zone0MsgReg8; ///<Ct DWORD bit 23-16
757 UINT8 MsgFun89Zone0MsgReg9; ///<Ct DWORD bit 31-24
758 UINT8 MsgFun89Zone0MsgRegA; ///<Mode bit 0-7
759//
760//EC LDN9 function 89 TEMPIN channel 1
761//
762 UINT8 MsgFun89Zone1MsgReg0; ///<Thermal zone
763 UINT8 MsgFun89Zone1MsgReg1; ///<Thermal zone
764 UINT8 MsgFun89Zone1MsgReg2; ///<At DWORD bit 0-7
765 UINT8 MsgFun89Zone1MsgReg3; ///<At DWORD bit 15-8
766 UINT8 MsgFun89Zone1MsgReg4; ///<At DWORD bit 23-16
767 UINT8 MsgFun89Zone1MsgReg5; ///<At DWORD bit 31-24
768 UINT8 MsgFun89Zone1MsgReg6; ///<Ct DWORD bit 0-7
769 UINT8 MsgFun89Zone1MsgReg7; ///<Ct DWORD bit 15-8
770 UINT8 MsgFun89Zone1MsgReg8; ///<Ct DWORD bit 23-16
771 UINT8 MsgFun89Zone1MsgReg9; ///<Ct DWORD bit 31-24
772 UINT8 MsgFun89Zone1MsgRegA; ///<Mode bit 0-7
773//
774//EC LDN9 function 89 TEMPIN channel 2
775//
776 UINT8 MsgFun89Zone2MsgReg0; ///<Thermal zone
777 UINT8 MsgFun89Zone2MsgReg1; ///<Thermal zone
778 UINT8 MsgFun89Zone2MsgReg2; ///<At DWORD bit 0-7
779 UINT8 MsgFun89Zone2MsgReg3; ///<At DWORD bit 15-8
780 UINT8 MsgFun89Zone2MsgReg4; ///<At DWORD bit 23-16
781 UINT8 MsgFun89Zone2MsgReg5; ///<At DWORD bit 31-24
782 UINT8 MsgFun89Zone2MsgReg6; ///<Ct DWORD bit 0-7
783 UINT8 MsgFun89Zone2MsgReg7; ///<Ct DWORD bit 15-8
784 UINT8 MsgFun89Zone2MsgReg8; ///<Ct DWORD bit 23-16
785 UINT8 MsgFun89Zone2MsgReg9; ///<Ct DWORD bit 31-24
786 UINT8 MsgFun89Zone2MsgRegA; ///<Mode bit 0-7
787//
788//EC LDN9 function 89 TEMPIN channel 3
789//
790 UINT8 MsgFun89Zone3MsgReg0; ///<Thermal zone
791 UINT8 MsgFun89Zone3MsgReg1; ///<Thermal zone
792 UINT8 MsgFun89Zone3MsgReg2; ///<At DWORD bit 0-7
793 UINT8 MsgFun89Zone3MsgReg3; ///<At DWORD bit 15-8
794 UINT8 MsgFun89Zone3MsgReg4; ///<At DWORD bit 23-16
795 UINT8 MsgFun89Zone3MsgReg5; ///<At DWORD bit 31-24
796 UINT8 MsgFun89Zone3MsgReg6; ///<Ct DWORD bit 0-7
797 UINT8 MsgFun89Zone3MsgReg7; ///<Ct DWORD bit 15-8
798 UINT8 MsgFun89Zone3MsgReg8; ///<Ct DWORD bit 23-16
799 UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24
800 UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7
801//
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]802//EC LDN9 function 8C Startup PWM channel 0
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]803//
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]804 UINT8 MsgFun8CZone0MsgReg0; ///<Reture 0xFA stands for success
805 UINT8 MsgFun8CZone0MsgReg1; ///<Bit 2-0 Thermal zone number
806 UINT8 MsgFun8CZone0MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
807 UINT8 MsgFun8CZone0MsgReg3; ///<Startup PWM (effective range 1~100)
808//
809//EC LDN9 function 8C Startup PWM channel 1
810//
811 UINT8 MsgFun8CZone1MsgReg0; ///<Reture 0xFA stands for success
812 UINT8 MsgFun8CZone1MsgReg1; ///<Bit 2-0 Thermal zone number
813 UINT8 MsgFun8CZone1MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
814 UINT8 MsgFun8CZone1MsgReg3; ///<Startup PWM (effective range 1~100)
815//
816//EC LDN9 function 8C Startup PWM channel 2
817//
818 UINT8 MsgFun8CZone2MsgReg0; ///<Reture 0xFA stands for success
819 UINT8 MsgFun8CZone2MsgReg1; ///<Bit 2-0 Thermal zone number
820 UINT8 MsgFun8CZone2MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
821 UINT8 MsgFun8CZone2MsgReg3; ///<Startup PWM (effective range 1~100)
822//
823//EC LDN9 function 8C Startup PWM channel 3
824//
825 UINT8 MsgFun8CZone3MsgReg0; ///<Reture 0xFA stands for success
826 UINT8 MsgFun8CZone3MsgReg1; ///<Bit 2-0 Thermal zone number
827 UINT8 MsgFun8CZone3MsgReg2; ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
828 UINT8 MsgFun8CZone3MsgReg3; ///<Startup PWM (effective range 1~100)
829//
830// FLAG for Fun83/85/89/8C support
831//
832 UINT32 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]833} FCH_EC;
834
835///
836/// IMC structure
837///
838typedef struct _FCH_IMC {
839 UINT8 ImcEnable; ///< ImcEnable - IMC Enable
840 UINT8 ImcEnabled; ///< ImcEnabled - IMC Enable
841 UINT8 ImcSureBootTimer; ///< ImcSureBootTimer - IMc SureBootTimer function
842 FCH_EC EcStruct; ///< EC structure
843 UINT8 ImcEnableOverWrite; ///< OverWrite IMC with the EC structure
844 /// @li <b>00</b> - by default strapping
845 /// @li <b>01</b> - enable
846 /// @li <b>10</b> - disable
847 ///
848} FCH_IMC;
849
850
851///
852/// Hpet structure
853///
854typedef struct {
855 BOOLEAN HpetEnable; ///< HPET function switch
856
857 BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration
858 /// @par
859 /// @li <b>1</b> - disable
860 /// @li <b>0</b> - enable
861
862 UINT32 HpetBase; ///< HpetBase
863 /// @par
864 /// HPET Base address
865} FCH_HPET;
866
867
868///
869/// GCPU related parameters
870///
871typedef struct {
872 UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery)
873 /// @li <b>1</b> - disable
874 /// @li <b>0</b> - enable
875
876 UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval
877 /// @li <b>1</b> - disable
878 /// @li <b>0</b> - enable
879
880 UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt
881 /// @li <b>1</b> - disable
882 /// @li <b>0</b> - enable
883
884 UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic
885 /// @li <b>1</b> - disable
886 /// @li <b>0</b> - enable
887
888 UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic
889 /// @li <b>1</b> - disable
890 /// @li <b>0</b> - enable
891
892 UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message
893 /// @li <b>1</b> - disable
894 /// @li <b>0</b> - enable
895
896 UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic
897 /// @li <b>1</b> - disable
898 /// @li <b>0</b> - enable
899} FCH_GCPU;
900
901
902///
903/// Timer
904///
905typedef struct {
906 BOOLEAN Enable; ///< Whether to register timer SMI in POST
907 BOOLEAN StartNow; ///< Whether to start the SMI immediately during registration
908 UINT16 CycleDuration; ///< [14:0] - Actual cycle duration = CycleDuration + 1
909} TIMER_SMI;
910
911///
912/// CS support
913///
914typedef struct {
915 BOOLEAN FchCsD3Cold; ///< FCH Cs D3 Cold function
916 BOOLEAN FchCsHwReduced; ///< FCH Cs hardware reduced ACPI flag
917 BOOLEAN FchCsPwrBtn; ///< FCH Cs Power Button function
918 BOOLEAN FchCsAcDc; ///< FCH Cs AcDc function
919 BOOLEAN AsfNfcEnable; ///< FCH Cs NFC function
920 UINT8 AsfNfcInterruptPin; ///< NFC Interrupt pin define
921 UINT8 AsfNfcRegPuPin; ///< NFC RegPu pin define
922 UINT8 AsfNfcWakePin; ///< NFC Wake Pin define
923 UINT8 PowerButtonGpe; ///< GPE# used by Power Button device
924 UINT8 AcDcTimerGpe; ///< GPE# used by Timer device
925} FCH_CS;
926
927
928///
929/// MISC structure
930///
931typedef struct {
932 BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled
933 BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume.
934 BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required.
935 UINT8 FchVariant; /// FchVariant - FCH Variant value.
936 UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
937 TIMER_SMI LongTimer; ///< Long Timer SMI
938 TIMER_SMI ShortTimer; ///< Short Timer SMI
939 UINT32 FchCpuId; ///< Saving CpuId for FCH Module.
940 BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )
941 FCH_CS FchCsSupport; ///< FCH Cs function structure
Marc Jones823dbde2018-01-25 17:05:46 -0700[diff] [blame]942 BOOLEAN FchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]943} FCH_MISC;
944
945
946///
947/// SMBus structure
948///
949typedef struct {
950 UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID
951} FCH_SMBUS;
952
953
954///
955/// Acpi structure
956///
957typedef struct {
958 UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress
959 /// @par
960 /// Smbus BASE Address
961 ///
962 UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress
963 /// @par
964 /// Smbus1 (ASF) BASE Address
965 ///
966 UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress
967 /// @par
968 /// SIO PME BASE Address
969 ///
970 UINT32 WatchDogTimerBase; ///< WatchDogTimerBase
971 /// @par
972 /// Watch Dog Timer Address
973 ///
974 UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr
975 /// @par
976 /// ACPI PM1 event block Address
977 ///
978 UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr
979 /// @par
980 /// ACPI PM1 Control block Address
981 ///
982 UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr
983 /// @par
984 /// ACPI PM timer block Address
985 ///
986 UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr
987 /// @par
988 /// ACPI CPU control block Address
989 ///
990 UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr
991 /// @par
992 /// ACPI GPE0 block Address
993 ///
994 UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr
995 /// @par
996 /// SMI command port Address
997 ///
998 UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr
999 /// @par
1000 /// ACPI PMA Control block Address
1001 ///
1002 BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink
1003 /// @par
1004 /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable)
1005 ///
1006 BOOLEAN SpreadSpectrum; ///< SpreadSpectrum
1007 /// @par
1008 /// Spread Spectrum function
1009 /// @li <b>0</b> - disable
1010 /// @li <b>1</b> - enable
1011 ///
1012 POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0]
1013 /// @par
1014 /// @li <b>00</b> - Always off
1015 /// @li <b>01</b> - Always on
1016 /// @li <b>11</b> - Use previous
1017 ///
1018 UINT8 StressResetMode; ///< StressResetMode 01-10
1019 /// @li <b>00</b> - Disabed
1020 /// @li <b>01</b> - Io Write 0x64 with 0xfe
1021 /// @li <b>10</b> - Io Write 0xcf9 with 0x06
1022 /// @li <b>11</b> - Io Write 0xcf9 with 0x0e
1023 ///
1024 BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e
1025 VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table
1026 UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option
1027 BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings
1028 BOOLEAN NoClearThermalTripSts; /// Skip clearing ThermalTrip status
1029} FCH_ACPI;
1030
1031
1032///
1033/// HWM temp parameter structure
1034///
1035typedef struct _FCH_HWM_TEMP_PAR {
1036 UINT16 At; ///< At
1037 UINT16 Ct; ///< Ct
1038 UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent
1039} FCH_HWM_TEMP_PAR;
1040
1041///
1042/// HWM Current structure
1043///
1044typedef struct _FCH_HWM_CUR {
1045 UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed
1046 UINT16 Temperature[5]; ///< Temperature - temperature
1047 UINT16 Voltage[8]; ///< Voltage - voltage
1048} FCH_HWM_CUR;
1049
1050///
1051/// HWM fan control structure
1052///
1053typedef struct _FCH_HWM_FAN_CTR {
1054 UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0
1055 UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1
1056 UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2
1057 UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3
1058 UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4
1059 UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5
1060 UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6
1061 UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8
1062 UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A
1063 UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C
1064 UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D
1065} FCH_HWM_FAN_CTR;
1066
1067///
1068/// Hwm structure
1069///
1070typedef struct _FCH_HWM {
1071 UINT8 HwMonitorEnable; ///< HwMonitorEnable
1072 UINT32 HwmControl; ///< hwmControl
1073 /// @par
1074 /// HWM control configuration
1075 /// @li <b>0</b> - HWM is Enabled
1076 /// @li <b>1</b> - IMC is Enabled
1077 ///
1078 UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed
1079 /// @li <b>00</b> - Base(22.5KHz)
1080 /// @li <b>01</b> - Base(22.5KHz)/2
1081 /// @li <b>10</b> - Base(22.5KHz)/4
1082 /// @li <b>11</b> - Base(22.5KHz)/8
1083 ///
1084 UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling
1085 /// @li <b>0</b> - disable
1086 /// @li <b>1</b> - enable
1087 ///
1088 UINT8 HwmFchtsiAutoPollStarted; ///< HwmSbtsiAutoPollStarted
1089 UINT8 FanLinearEnhanceEn; ///< FanLinearEnhanceEn
1090 UINT8 FanLinearHoldFix; ///< FanLinearHoldFix
1091 UINT8 FanLinearRangeOutLimit; ///< FanLinearRangeOutLimit
1092 UINT16 HwmCalibrationFactor; /// Calibration Factor
1093 FCH_HWM_CUR HwmCurrent; /// HWM Current structure
1094 FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure
1095 FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure
1096 FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure
1097 FCH_HWM_FAN_CTR HwmFanControlCooked[5]; /// HWM Fan Control structure
1098} FCH_HWM;
1099
1100
1101///
1102/// Gec structure
1103///
1104typedef struct {
1105 BOOLEAN GecEnable; ///< GecEnable - GEC function switch
1106 UINT8 GecPhyStatus; /// GEC PHY Status
1107 UINT8 GecPowerPolicy; /// GEC Power Policy
1108 /// @li <b>00</b> - GEC is powered down in S3 and S5
1109 /// @li <b>01</b> - GEC is powered down only in S5
1110 /// @li <b>10</b> - GEC is powered down only in S3
1111 /// @li <b>11</b> - GEC is never powered down
1112 ///
1113 UINT8 GecDebugBus; /// GEC Debug Bus
1114 /// @li <b>0</b> - disable
1115 /// @li <b>1</b> - enable
1116 ///
1117 UINT32 GecShadowRomBase; ///< GecShadowRomBase
1118 /// @par
1119 /// GEC (NIC) SHADOWROM BASE Address
1120 ///
1121 VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address
1122} FCH_GEC;
1123
1124
1125///
1126/// _ABTblEntry - AB link register table R/W structure
1127///
1128typedef struct _AB_TBL_ENTRY {
1129 UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on)
1130 UINT32 RegIndex; /// RegIndex : AB Register Index
1131 UINT32 RegMask; /// RegMask : AB Register Mask
1132 UINT32 RegData; /// RegData : AB Register Data
1133} AB_TBL_ENTRY;
1134
1135///
1136/// AB structure
1137///
1138typedef struct {
1139 BOOLEAN AbMsiEnable; ///< ABlink MSI capability
1140 UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR
1141 UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR
1142 UINT8 GppClockRequest0; /// GPP Clock Request.
1143 UINT8 GppClockRequest1; /// GPP Clock Request.
1144 UINT8 GppClockRequest2; /// GPP Clock Request.
1145 UINT8 GppClockRequest3; /// GPP Clock Request.
1146 UINT8 GfxClockRequest; /// GPP Clock Request.
1147 UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR *CZ
1148 UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable
1149 UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value
1150 UINT8 UmiLinkWidth; /// UMI Link Width
1151 UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable
1152 UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value
1153 UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength
1154 BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2
1155 UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted
1156 UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR
1157 BOOLEAN ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR
1158 BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only
1159 BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR *CZ
1160 BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only
1161 BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR *CZ
1162 BOOLEAN SbgClockGating; /// SBG Clock Gate *CZ
1163 BOOLEAN XdmaDmaWrite16ByteMode; /// XDMA DMA Write 16 byte mode *CZ
1164 BOOLEAN XdmaMemoryPowerSaving; /// XDMA memory power saving *CZ
1165 UINT8 XdmaPendingNprThreshold; /// XDMA PENDING NPR THRESHOLD *CZ
1166 BOOLEAN XdmaDncplOrderDis; /// XDMA DNCPL ORDER DIS *CZ
1167} FCH_AB;
1168
1169
1170/**
1171 * PCIE_CAP_ID - PCIe Cap ID
1172 *
1173 */
1174#define PCIE_CAP_ID 0x10
1175
1176///
1177/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure
1178///
1179typedef struct {
1180 BOOLEAN PortPresent; ///< Port connection
1181 /// @par
1182 /// @li <b>0</b> - Port doesn't have slot. No need to train the link
1183 /// @li <b>1</b> - Port connection defined and needs to be trained
1184 ///
1185 BOOLEAN PortDetected; ///< Link training status
1186 /// @par
1187 /// @li <b>0</b> - EP not detected
1188 /// @li <b>1</b> - EP detected
1189 ///
1190 BOOLEAN PortIsGen2; ///< Port link speed configuration
1191 /// @par
1192 /// @li <b>00</b> - Auto
1193 /// @li <b>01</b> - Forced GEN1
1194 /// @li <b>10</b> - Forced GEN2
1195 /// @li <b>11</b> - Reserved
1196 ///
1197 BOOLEAN PortHotPlug; ///< Support hot plug?
1198 /// @par
1199 /// @li <b>0</b> - No support
1200 /// @li <b>1</b> - support
1201 ///
1202 UINT8 PortMisc; /// PortMisc - Reserved
1203} FCH_GPP_PORT_CONFIG;
1204
1205///
1206/// GPP structure
1207///
1208typedef struct {
1209 FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure
1210 GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0]
1211 /// @li <b>0000</b> - Port ABCD -> 4:0:0:0
1212 /// @li <b>0010</b> - Port ABCD -> 2:2:0:0
1213 /// @li <b>0011</b> - Port ABCD -> 2:1:1:0
1214 /// @li <b>0100</b> - Port ABCD -> 1:1:1:1
1215 ///
1216 BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable
1217 BOOLEAN GppToggleReset; ///< Toggle GPP core reset
1218 UINT8 GppHotPlugGeventNum; ///< Hotplug GEVENT # - valid value 0-31
1219 UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device
1220 /// @li <b>0</b> - Not found
1221 /// @li <b>1</b> - Found
1222 ///
1223 BOOLEAN GppGen2; ///< GPP Gen2 - 0:disable, 1:enable
1224 UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this
1225 BOOLEAN GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable
1226 BOOLEAN GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable
1227 UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports
1228 /// @li <b>01</b> - Disabled
1229 /// @li <b>01</b> - L0s
1230 /// @li <b>10</b> - L1
1231 /// @li <b>11</b> - L0s + L1
1232 ///
1233 BOOLEAN GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable
1234 BOOLEAN GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable
1235 BOOLEAN GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable
1236 BOOLEAN PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable
1237 BOOLEAN PcieRas; ///< PCIe RAS - 0:disable, 1:enable
1238 BOOLEAN PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable
1239 BOOLEAN PcieSoftwareDownGrade; ///< PCIe Software Down Grade
1240 BOOLEAN UmiPhyPllPowerDown; ///< UMI PHY PLL Power Down - 0:disable, 1:enable
1241 BOOLEAN SerialDebugBusEnable; ///< Serial Debug Bus Enable
1242 UINT8 GppHardwareDownGrade; ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D
1243 UINT8 GppL1ImmediateAck; ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable
1244 BOOLEAN NewGppAlgorithm; ///< NewGppAlgorithm - New GPP procedure
1245 UINT8 HotPlugPortsStatus; ///< HotPlugPortsStatus - Save Hot-Plug Ports Status
1246 UINT8 FailPortsStatus; ///< FailPortsStatus - Save Failure Ports Status
1247 UINT8 GppPortMinPollingTime; ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training
1248 BOOLEAN IsCapsuleMode; ///< IsCapsuleMode - Support Capsule Mode in FCH
1249} FCH_GPP;
1250
1251
1252///
1253/// FCH USB3 Debug Sturcture
1254///
1255typedef struct {
1256 BOOLEAN ServiceIntervalEnable; ///< Service Interval Enable
1257 BOOLEAN BandwidthExpandEnable; ///< Bandwidth Expand Enable
1258 BOOLEAN AoacEnable; ///< Aoac Enable
1259 BOOLEAN HwLpmEnable; ///< HwLpm Enable
1260 BOOLEAN DbcEnable; ///< DBC Enable
1261 BOOLEAN MiscPlusEnable; ///< Misc Plus Enable
1262 BOOLEAN EcoFixEnable; ///< Eco Fix Enable
1263 BOOLEAN SsifEnable; ///< SSIF Enable
1264 BOOLEAN U2ifEnable; ///< U2IF Enable
1265 BOOLEAN FseEnable; ///< FSE Enable
1266 BOOLEAN XhcPmeEnable; ///< Xhc Pme Enable
1267} USB3_DEBUG;
1268
1269///
1270/// FCH IoMux Sturcture
1271///
1272typedef struct {
1273 UINT8 CbsDbgFchSmbusI2c2Egpio; ///< SMBUS/I2C_2/EGPIO_113_114
1274 UINT8 CbsDbgFchAsfI2c3Egpio; ///< ASF/I2C_3/EGPIO_019_020
1275} FCH_IOMUX;
1276
1277///
1278/// FCH USB sturcture
1279///
1280typedef struct {
1281 BOOLEAN Ohci1Enable; ///< OHCI1 controller enable
1282 BOOLEAN Ohci2Enable; ///< OHCI2 controller enable
1283 BOOLEAN Ohci3Enable; ///< OHCI3 controller enable
1284 BOOLEAN Ohci4Enable; ///< OHCI4 controller enable
1285 BOOLEAN Ehci1Enable; ///< EHCI1 controller enable
1286 BOOLEAN Ehci2Enable; ///< EHCI2 controller enable
1287 BOOLEAN Ehci3Enable; ///< EHCI3 controller enable
1288 BOOLEAN Xhci0Enable; ///< XHCI0 controller enable
1289 BOOLEAN Xhci1Enable; ///< XHCI1 controller enable
1290 BOOLEAN UsbMsiEnable; ///< USB MSI capability
1291 UINT32 OhciSsid; ///< OHCI SSID
1292 UINT32 Ohci4Ssid; ///< OHCI 4 SSID
1293 UINT32 EhciSsid; ///< EHCI SSID
1294 UINT32 XhciSsid; ///< XHCI SSID
1295 BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable
1296 UINT32 UserDefineXhciRomAddr; ///< XHCI ROM address define by platform BIOS
1297 UINT8 Ehci1Phy[5]; ///< EHCI1 USB PHY Driving Strength value table
1298 UINT8 Ehci2Phy[5]; ///< EHCI2 USB PHY Driving Strength value table
1299 UINT8 Ehci3Phy[4]; ///< EHCI3 USB PHY Driving Strength value table
1300 UINT8 Xhci20Phy[4]; ///< XHCI USB 2.0 PHY Driving Strength value table
1301 UINT8 Ehci1DebugPortSel; ///< DebugPortSel for Ehci1 Hub
1302 /// @li <b>000</b> - Disable
1303 /// @li <b>001</b> - HubDownStreamPort0
1304 /// @li <b>010</b> - HubDownStreamPort1
1305 /// @li <b>011</b> - HubDownStreamPort2
1306 /// @li <b>100</b> - HubDownStreamPort3
1307 UINT8 Ehci2DebugPortSel; ///< DebugPortSel for Ehci2 Hub
1308 /// @li <b>000</b> - Disable
1309 /// @li <b>001</b> - HubDownStreamPort0
1310 /// @li <b>010</b> - HubDownStreamPort1
1311 /// @li <b>011</b> - HubDownStreamPort2
1312 /// @li <b>100</b> - HubDownStreamPort3
1313 UINT8 Ehci3DebugPortSel; ///< DebugPortSel for Ehci3 Hub
1314 /// @li <b>000</b> - Disable
1315 /// @li <b>001</b> - HubDownStreamPort0
1316 /// @li <b>010</b> - HubDownStreamPort1
1317 /// @li <b>011</b> - HubDownStreamPort2
1318 /// @li <b>100</b> - HubDownStreamPort3
1319 UINT8 Ehci1NPort; ///< N_Port for Ehci1, 2 to 4
1320 UINT8 Ehci2NPort; ///< N_Port for Ehci2, 2 to 4
1321 USB3_DEBUG Usb3Debug; ///< Usb3 Debug Options
1322 BOOLEAN EhciSimpleDebugPort; ///< Ehci Simple Debug Port
1323 BOOLEAN UsbBatteryChargeEnable; ///< USB Battery Charge Enable
1324 BOOLEAN ReduceUSB3PortToLastTwo; ///< Reduce USB3.0 ports to last 2
1325 UINT8 USB30PortInit; ///< USB 3.0 Port Init
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]1326 UINT8 USB30RxLfpsDetTh; ///< USB 3.0 Rx Lfps Detect Threshhold
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]1327} FCH_USB;
1328
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]1329//++++++++++++++++++++++++++++++++++ Promontory param structure
1330///PTXhciStructure
1331typedef struct {
1332 UINT8 PTXhciGen1; ///< PTXhciGen1
1333 UINT8 PTXhciGen2; ///< PTXhciGen2
1334 UINT8 PTAOAC; ///< PTAOAC
1335 UINT8 PTHW_LPM ; ///< PTHW_LPM
1336 UINT8 PTDbC; ///< PTDbC
1337 UINT8 PTXHC_PME; ///< PTXHC_PME
1338 UINT8 PTSystemSpreadSpectrum; ///< PTSystemSpreadSpectrum
1339 UINT8 Equalization4; ///< Enable/Disable Equalization 4
1340 UINT8 Redriver; ///< Enable/Disable Redriver Setting
1341} PT_USB;
1342///PTSataStructure
1343typedef struct {
1344 UINT8 PTSataPortEnable; ///< PTSataEnable
1345 UINT8 PTSataMode; ///< PTSataMode
1346 UINT8 PTSataAggresiveDevSlpP0; ///< PTSataAggresiveDevSlpP0
1347 UINT8 PTSataAggresiveDevSlpP1; ///< PTSataAggresiveDevSlpP1
1348 UINT8 PTSataAggrLinkPmCap; ///< PTSataAggrLinkPmCap
1349 UINT8 PTSataPscCap; ///< PTSataPscCap
1350 UINT8 PTSataSscCap; ///< PTSataSscCap
1351 UINT8 PTSataMsiCapability; ///< PTSataPscCap
1352 UINT8 PTSataPortMdPort0; ///< PTSataPortMdPort0
1353 UINT8 PTSataPortMdPort1; ///< PTSataPortMdPort1
1354 UINT8 PTSataHotPlug; ///< PTSataHotPlug
1355} PT_SATA;
1356///PTPcieStructure
1357typedef struct {
1358 UINT8 PromontoryPCIeEnable; ///< PCIeEnable
1359 UINT8 PromontoryPCIeASPM; ///< PCIeASPM
1360} PT_PCIE;
1361///PTAddressStructure
1362typedef struct {
1363 UINT8 GppNumber; ///< GppNumber
1364 UINT32 XhciID; ///< XhciDIDVID
1365 UINT32 SataID; ///< SataDIDVID
1366 UINT32 GpioID; ///< GpioDIDVID
1367 UINT64 FwVersion; ///< FwVersion
1368} PT_ADDR;
1369///PTUSBPortStructure
1370typedef struct {
1371 UINT8 PTUsb31P0; ///< PTUsb31Port0 Enable/Disable
1372 UINT8 PTUsb31P1; ///< PTUsb31Port0 Enable/Disable
1373 UINT8 PTUsb30P0; ///< PTUsb30Port0 Enable/Disable
1374 UINT8 PTUsb30P1; ///< PTUsb30Port1 Enable/Disable
1375 UINT8 PTUsb30P2; ///< PTUsb30Port2 Enable/Disable
1376 UINT8 PTUsb30P3; ///< PTUsb30Port3 Enable/Disable
1377 UINT8 PTUsb30P4; ///< PTUsb30Port4 Enable/Disable
1378 UINT8 PTUsb30P5; ///< PTUsb30Port5 Enable/Disable
1379 UINT8 PTUsb20P0; ///< PTUsb20Port0 Enable/Disable
1380 UINT8 PTUsb20P1; ///< PTUsb20Port1 Enable/Disable
1381 UINT8 PTUsb20P2; ///< PTUsb20Port2 Enable/Disable
1382 UINT8 PTUsb20P3; ///< PTUsb20Port3 Enable/Disable
1383 UINT8 PTUsb20P4; ///< PTUsb20Port4 Enable/Disable
1384 UINT8 PTUsb20P5; ///< PTUsb20Port5 Enable/Disable
1385} PT_USBPort;
1386///PTUSB31TxStructure
1387typedef struct {
1388UINT8 USB31Gen1Swing; ///< PTUSB31PCS_B1 genI swing
1389UINT8 USB31Gen2Swing; ///< PTUSB31PCS_B1 genI swing
1390UINT8 USB31Gen1PreEmEn; ///< PTUSB31PCS_B1 genI pre-emphasis enable
1391UINT8 USB31Gen2PreEmEn; ///< PTUSB31PCS_B1 genII pre-emphasis enable
1392UINT8 USB31Gen1PreEmLe; ///< PTUSB31PCS_B1 genI pre-emphasis level
1393UINT8 USB31Gen2PreEmLe; ///< PTUSB31PCS_B1 genII pre-emphasis level
1394UINT8 USB31Gen1PreShEn; ///< PTUSB31PCS_B1 genI pre-shoot enable
1395UINT8 USB31Gen2PreShEn; ///< PTUSB31PCS_B1 genII pre-shoot enable
1396UINT8 USB31Gen1PreShLe; ///< PTUSB31PCS_B1 genI pre-shoot level
1397UINT8 USB31Gen2PreShLe; ///< PTUSB31PCS_B1 genII pre-shoot level
1398} PT_USB31Tx;
1399
1400///PTUSB30TxStructure
1401typedef struct {
1402UINT8 USB30Gen1Swing; ///< PTUSB30PCS_B3 genI swing
1403UINT8 USB30Gen1PreEmEn; ///< PTUSB30PCS_B3 genI pre-emphasis enable
1404UINT8 USB30Gen1PreEmLe; ///< PTUSB30PCS_B3 genI pre-emphasis level
1405} PT_USB30Tx;
1406
1407
1408///PTUSBTxStructure
1409typedef struct {
1410PT_USB31Tx USB31Tx[2]; ///< USB31Tx setting
Marc Jones823dbde2018-01-25 17:05:46 -0700[diff] [blame]1411PT_USB30Tx USB30Tx[6]; ///< USB30Tx setting
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]1412UINT8 USB20B2Tx00; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[0]
1413UINT8 USB20B2Tx05; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[5]
1414UINT8 USB20B3Tx1113; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[13][11]
1415UINT8 USB20B3Tx1012; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[12][10]
1416UINT8 USB20B4Tx0206; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[2][6]
1417UINT8 USB20B4Tx0307; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[3][7]
1418UINT8 USB20B5Tx0408; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[4][8]
1419UINT8 USB20B5Tx0109; ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[1][9]
1420} PT_USBTx;
1421
1422///PTSataTxStructure
1423typedef struct {
1424UINT8 SATAGen1Swing; ///< genI swing
1425UINT8 SATAGen2Swing; ///< genII swing
1426UINT8 SATAGen3Swing; ///< genIII swing
1427UINT8 SATAGen1PreEmEn; ///< genI pre-emphasis enable
1428UINT8 SATAGen2PreEmEn; ///< genII pre-emphasis enable
1429UINT8 SATAGen3PreEmEn; ///< genIII pre-emphasis enable
1430UINT8 SATAGen1PreEmLevel; ///< genI pre-emphasis level
1431UINT8 SATAGen2PreEmLevel; ///< genII pre-emphasis level
1432UINT8 SATAGen3PreEmLevel; ///< genIII pre-emphasis level
1433} PT_SATATx;
1434///PTDataStructure
1435typedef struct _FCH_PT {
1436 PT_USB PromontoryUSB; ///<PTXhciStructure
1437 PT_SATA PromontorySATA; ///<PTSataStructure
1438 PT_PCIE PromontoryPCIE; ///<PTPcieStructure
1439 PT_ADDR PromontoryAddr; ///<PTAddressStructure
1440 PT_USBPort PromontoryUSBPort; ///<PTUSBPortStructure
1441 PT_USBTx PTUSBTX; ///<PTUSBTX
1442 PT_SATATx PTSATATX[8]; ///<PTSATATX
1443} FCH_PT;
1444
1445//-------------------------------------------- Promontory param structure
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]1446
1447/// Private: FCH_DATA_BLOCK_RESET
1448typedef struct _FCH_RESET_DATA_BLOCK {
1449 AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
1450 FCH_RESET_INTERFACE FchReset; ///< Reset interface
1451
1452 UINT8 FastSpeed; ///< SPI FastSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
1453 UINT8 WriteSpeed; ///< SPI Write Speed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
1454 UINT8 Mode; ///< SPI Mode
1455 /// @li <b>101</b> - Qual-io 1-4-4
1456 /// @li <b>100</b> - Dual-io 1-2-2
1457 /// @li <b>011</b> - Qual-io 1-1-4
1458 /// @li <b>010</b> - Dual-io 1-1-2
1459 /// @li <b>111</b> - FastRead
1460 /// @li <b>110</b> - Normal
1461 ///
1462 UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable
1463 UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable
1464 BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable
1465 UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
1466 BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable
1467 BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable
1468 BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2
1469 UINT8 SataClkMode; ///< SATA reference clock selector and divider
1470 UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA
1471 BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF
1472 UINT8 SpiSpeed; ///< SPI NormSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
1473// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
1474// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
1475// UINT8 SpiProtectEn0_1d_34; ///
1476 UINT8 SPI100_Enable; ///
1477 BOOLEAN EcChannel0; ///< Enable EC channel 0
1478 FCH_GPP Gpp; ///< GPP subsystem
1479 FCH_SPI Spi; ///< SPI subsystem
1480 BOOLEAN QeEnabled; /// Quad Mode Enabled
1481 BOOLEAN FchOscout1ClkContinous; ///< FCH OSCOUT1_CLK Continous
1482 UINT8 LpcClockDriveStrength; ///< Lpc Clock Drive Strength
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]1483 FCH_PT Promontory; ///< Promontory structure
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]1484 const VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]1485// VOID* OemSpiDeviceTable; /// Pointer of OEM Spi Device table
1486} FCH_RESET_DATA_BLOCK;
1487
1488
1489/// Private: FCH_DATA_BLOCK
1490typedef struct _FCH_DATA_BLOCK {
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]1491 AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]1492 FCH_RUNTIME FchRunTime; ///< FCH Run Time Parameters
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]1493
1494 FCH_ACPI HwAcpi; ///< ACPI structure
1495 FCH_AB Ab; ///< AB structure
1496 FCH_GPP Gpp; ///< GPP structure
1497 FCH_USB Usb; ///< USB structure
1498 FCH_SATA Sata; ///< SATA structure
1499 FCH_SMBUS Smbus; ///< SMBus structure
1500 FCH_IDE Ide; ///< IDE structure
1501 FCH_AZALIA Azalia; ///< Azalia structure
1502 FCH_SPI Spi; ///< SPI structure
1503 FCH_PCIB Pcib; ///< PCIB structure
1504 FCH_GEC Gec; ///< GEC structure
1505 FCH_SD Sd; ///< SD structure
1506 FCH_HWM Hwm; ///< Hardware Moniter structure
1507 FCH_IR Ir; ///< IR structure
1508 FCH_HPET Hpet; ///< HPET structure
1509 FCH_GCPU Gcpu; ///< GCPU structure
1510 FCH_IMC Imc; ///< IMC structure
1511 FCH_MISC Misc; ///< MISC structure
1512 FCH_IOMUX IoMux; ///< MISC structure
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]1513 FCH_PT Promontory; ///< Promontory structure
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame]1514 const VOID* PostOemGpioTable; /// Pointer of Post OEM GPIO table
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]1515} FCH_DATA_BLOCK;
1516
1517#pragma pack (pop)
1518
1519#endif