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review.coreboot.org / coreboot / 7687e7767f2d2321b57fa8eab68b7e954e57ad42 / . / src / vendorcode / amd / pi / 00670F00 / Proc / CPU / heapManager.h
blob: 80b6977cfbd7ab478abce64f1c78afc16a1787c6 [file] [log] [blame]
Martin Roth7687e772023-08-22 16:32:20 -0600[diff] [blame^]1/* SPDX-License-Identifier: BSD-3-Clause */
2
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]3/* $NoKeywords:$ */
4/**
5 * @file
6 *
7 * AMD Heap Manager and Heap Allocation APIs, and related functions.
8 *
9 * Contains code that initialize, maintain, and allocate the heap space.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: CPU
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]14 * @e \$Revision$ @e \$Date$
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]15 *
16 */
17 /*****************************************************************************
18 *
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]19 * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *
44 ***************************************************************************/
45
Martin Rothae016342017-11-16 22:46:56 -0700[diff] [blame]46#include <check_for_wrapper.h>
47
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]48#ifndef _HEAP_MANAGER_H_
49#define _HEAP_MANAGER_H_
50
51/*---------------------------------------------------------------------------------------
52 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
53 *---------------------------------------------------------------------------------------
54 */
55
56
57/*---------------------------------------------------------------------------------------
58 * D E F I N I T I O N S A N D M A C R O S
59 *---------------------------------------------------------------------------------------
60 */
61#define AMD_MTRR_VARIABLE_BASE0 0x200
62#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
63#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
64
65#define AMD_HEAP_START_ADDRESS 0x400000ul
66#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul
67#define AMD_HEAP_SIZE_PER_CORE 0x010000ul
68#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul
69#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800)
70#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
71
72#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value)
73#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20
74
75#define AMD_HEAP_RAM_ADDRESS 0xB0000ul
76
77#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP'
78#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared
79
80///Heap Manager Life cycle
81#define HEAP_DO_NOT_EXIST_YET 1
82#define HEAP_LOCAL_CACHE 2
83#define HEAP_TEMP_MEM 3
84#define HEAP_SYSTEM_MEM 4
85#define HEAP_DO_NOT_EXIST_ANYMORE 5
86#define HEAP_S3_RESUME 6
87#define HEAP_RUNTIME_SYSTEM_MEM 7
88
89///Heap callout
90#define HEAP_CALLOUT_BOOTTIME 0
91#define HEAP_CALLOUT_RUNTIME 1
92
93/*---------------------------------------------------------------------------------------
94 * T Y P E D E F S, S T R U C T U R E S, E N U M S
95 *---------------------------------------------------------------------------------------
96 */
97/// Allocate Heap Parameters
98typedef struct _ALLOCATE_HEAP_PARAMS {
99 UINT32 RequestedBufferSize; ///< Size of buffer.
100 UINT32 BufferHandle; ///< An unique ID of buffer.
101 UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
102 UINT8 *BufferPtr; ///< Pointer to buffer.
103} ALLOCATE_HEAP_PARAMS;
104
105/// Locate Heap Parameters
106typedef struct _LOCATE_HEAP_PTR {
107 UINT32 BufferHandle; ///< An unique ID of buffer.
108 UINT32 BufferSize; ///< Data buffer size.
109 UINT8 *BufferPtr; ///< Pointer to buffer.
110} LOCATE_HEAP_PTR;
111
112/// Heap Node Header
113typedef struct _BUFFER_NODE {
114 UINT32 BufferHandle; ///< An unique ID of buffer.
115 UINT32 BufferSize; ///< Size of buffer.
116 UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
117 UINT8 PadSize; ///< Size of pad.
118 UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
119} BUFFER_NODE;
120
121/// Heap Manager
122typedef struct _HEAP_MANAGER {
123 UINT32 Signature; ///< a signature to indicate if the heap is valid.
124 UINT32 UsedSize; ///< Used size of heap.
125 UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
126 UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
127} HEAP_MANAGER;
128
129/// AGESA Buffer Handles (These are reserved)
130typedef enum {
131 AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
132 AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
133 AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
134 AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
135 AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
136 AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
137 AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
138 AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
139 AMD_INIT_RTB_HANDLE, ///< Assign 0x000A008 buffer handle to AmdInitRtb routine.
140 AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
141 AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
142 AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
143 AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
144 AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
145 AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
146 AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
147 AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
148 AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
149 AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
150 AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
151 AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3
152 AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information
153 AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information
154 EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A017 buffer handle to Event Log
155 IDS_CONTROL_HANDLE, ///< Assign 0x000A018 buffer handle to AmdIds routine.
156 IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to be used for HDTOUT support.
157 IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01A buffer handle to Performance analysis
158 AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to be used for PCIe support
159 AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01C buffer handle to be used for memory data structure
160 AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GNB SMU configuration
161 AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A01E buffer handle to be used for TT fuse table
162 AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for Gfx platform configuration
163 AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A020 buffer handle for GNB general purpose data block
164 AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A021 buffer handle for 2D training
165 AMD_MEM_2D_RD_WR_HANDLE, ///< Assign 0x000A022 buffer handle for 2D Read/Write training
166 AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A023 buffer handle to be used for GNB IOMMU scratch memory
167 AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A024 buffer handle for memory data saved right after memory init
168 AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training Eye RIM Search
169 AMD_MEM_2D_RD_WR_RIM_HANDLE, ///< Assign 0x000A026 buffer handle for 2D Read/Write training Eye RIM Search
170 AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A027 buffer handle for an NB P-state workaround
171 AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A028 buffer handle for CRAT Memory affinity component structure
172 AMD_SKIP_MEM_S3_SAVE, ///< Assign 0x000A029 buffer handle for the flag to skip memory S3 save
173 AMD_IS_FEATURE_ENABLED, ///< Assign 0x000A02A buffer handle for keeping the result of IsFeatureEnabled
174 AMD_MEM_DATAEYE_WORK_AREA_HANDLE, ///< Assign 0x000A02B buffer handle for Composite Data Eye Compression Work Area
175 AMD_GNB_SAMU_PATCH_HANDLE, ///< Assign 0x000A02C buffer handle for Samu patch buffer
176 AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, ///< Assign 0x000A02D buffer handle for Samu boot control buffer
177 AMD_GNB_ACP_ENGINE_HANDLE, ///< Assign 0x000A02E buffer handle for GNB ACP engine buffer
178 AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE, ///< Assign 0x000A02F buffer handle for PMU SRAM Message Block buffer
179 AMD_MEM_DRAM_CAD_BUS_CONFIG_HANDLE, ///< Assign 0x000A030 buffer handle for DRAM CAD Bus Configuration
180 AMD_GNB_SMU_TABLE_HANDLE, ///< Assign 0x000A031 buffer handle for GNB SMU table buffer
181 AMD_GNB_CRAT_HSA_TABLE_HANDLE, ///< Assign 0x000A032 buffer handle for GNB CRAT HSA unit table
182 AMD_GNB_BUILD_OPTIONS_HANDLE, ///< Assign 0x000A033 buffer handle for GNB build options
183 AMD_S3_FINAL_RESTORE_HANDLE, ///< Assign 0x000A034 buffer handle to AmdS3FinalRestore routine.
184 AMD_GNB_PCIE_AER_CONFIG_HANDLE, ///< Assign 0x000A035 buffer handle for GNB PCIE AER configuration.
185 AMD_BTC_SCRATCH_HANDLE, ///< Assign 0x000A036 buffer handle for boot time calibration workloads
186 AMD_BTC_XMM_SAVE_HANDLE, ///< Assign 0x000A037 buffer handle for boot time calibration xmm register save
187 AMD_S3_SAVE_HANDLE, ///< Assign 0x000A038 buffer handle to memory context data
188 AMD_MEM_DDR_MAX_RATE_HANDLE, ///< Assign 0x000A039 buffer handle to memory DDR max rate
189 AMD_GNB_TDP_HANDLE, ///< Assign 0x000A03A buffer handle to GNB TDP
190 AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
191 AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
192 AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
193 SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
194 NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
195 HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
196 AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset
197 AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv
198 IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table
199 IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR'
200 IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table
201 IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save
202 IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save
203 IDS_EXTEND_HANDLE = 0x54584549, ///< 'IEXT' Handle for IDS extend module
204 IDS_TEMP_DATA_HANDLE = 0x504D5459, ///< 'ITMP' Handle for IDS temp data
205} AGESA_BUFFER_HANDLE;
206
207
208/*---------------------------------------------------------------------------------------
209 * F U N C T I O N P R O T O T Y P E
210 *---------------------------------------------------------------------------------------
211 */
212
213AGESA_STATUS
214HeapManagerInit (
215 IN AMD_CONFIG_PARAMS *StdHeader
216 );
217
218AGESA_STATUS
219HeapAllocateBuffer (
220 IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
221 IN OUT AMD_CONFIG_PARAMS *StdHeader
222 );
223
224AGESA_STATUS
225HeapDeallocateBuffer (
226 IN UINT32 BufferHandle,
227 IN AMD_CONFIG_PARAMS *StdHeader
228 );
229
230AGESA_STATUS
231HeapLocateBuffer (
232 IN OUT LOCATE_HEAP_PTR *LocateHeap,
233 IN AMD_CONFIG_PARAMS *StdHeader
234 );
235
236UINT64
237HeapGetBaseAddress (
238 IN AMD_CONFIG_PARAMS *StdHeader
239 );
240
241AGESA_STATUS
242EventLogInitialization (
243 IN AMD_CONFIG_PARAMS *StdHeader
244 );
245#endif // _HEAP_MANAGER_H_