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review.coreboot.org / coreboot / 7687e7767f2d2321b57fa8eab68b7e954e57ad42 / . / src / vendorcode / amd / pi / 00670F00 / Proc / CPU / cpuRegisters.h
blob: 54e06c28dc21923cfb24d56cf5906f5a75f7681e [file] [log] [blame]
Martin Roth7687e772023-08-22 16:32:20 -0600[diff] [blame^]1/* SPDX-License-Identifier: BSD-3-Clause */
2
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]3/* $NoKeywords:$ */
4/**
5 * @file
6 *
7 * AMD CPU Register Table Related Functions
8 *
9 * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: CPU
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]14 * @e \$Revision$ @e \$Date$
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]15 *
16 */
17 /*****************************************************************************
18 *
Marc Jones823dbde2018-01-25 17:05:46 -0700[diff] [blame]19 * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *
44 ***************************************************************************/
45
Martin Rothae016342017-11-16 22:46:56 -0700[diff] [blame]46#include <check_for_wrapper.h>
47
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]48#ifndef _CPU_REGISTERS_H_
49#define _CPU_REGISTERS_H_
50
51#include "cpuFamRegisters.h"
52/*
53 *--------------------------------------------------------------
54 *
55 * M O D U L E S U S E D
56 *
57 *---------------------------------------------------------------
58 */
59
60/*
61 *--------------------------------------------------------------
62 *
63 * D E F I N I T I O N S / M A C R O S
64 *
65 *---------------------------------------------------------------
66 */
67
68#undef BIT0
69#undef BIT1
70#undef BIT2
71#undef BIT3
72#undef BIT4
73#undef BIT5
74#undef BIT6
75#undef BIT7
76#undef BIT8
77#undef BIT9
78#undef BIT10
79#undef BIT10
80#undef BIT11
81#undef BIT12
82#undef BIT13
83#undef BIT14
84#undef BIT15
85#undef BIT16
86#undef BIT17
87#undef BIT18
88#undef BIT19
89#undef BIT20
90#undef BIT21
91#undef BIT22
92#undef BIT23
93#undef BIT24
94#undef BIT25
95#undef BIT26
96#undef BIT27
97#undef BIT28
98#undef BIT29
99#undef BIT30
100#undef BIT31
101#undef BIT32
102#undef BIT33
103#undef BIT34
104#undef BIT35
105#undef BIT36
106#undef BIT37
107#undef BIT38
108#undef BIT39
109#undef BIT40
110#undef BIT41
111#undef BIT42
112#undef BIT43
113#undef BIT44
114#undef BIT45
115#undef BIT46
116#undef BIT47
117#undef BIT48
118#undef BIT49
119#undef BIT40
120#undef BIT41
121#undef BIT42
122#undef BIT43
123#undef BIT44
124#undef BIT45
125#undef BIT46
126#undef BIT47
127#undef BIT48
128#undef BIT49
129#undef BIT50
130#undef BIT51
131#undef BIT52
132#undef BIT53
133#undef BIT54
134#undef BIT55
135#undef BIT56
136#undef BIT57
137#undef BIT58
138#undef BIT59
139#undef BIT60
140#undef BIT61
141#undef BIT62
142#undef BIT63
143
144#define BIT0 0x0000000000000001ull
145#define BIT1 0x0000000000000002ull
146#define BIT2 0x0000000000000004ull
147#define BIT3 0x0000000000000008ull
148#define BIT4 0x0000000000000010ull
149#define BIT5 0x0000000000000020ull
150#define BIT6 0x0000000000000040ull
151#define BIT7 0x0000000000000080ull
152#define BIT8 0x0000000000000100ull
153#define BIT9 0x0000000000000200ull
154#define BIT10 0x0000000000000400ull
155#define BIT11 0x0000000000000800ull
156#define BIT12 0x0000000000001000ull
157#define BIT13 0x0000000000002000ull
158#define BIT14 0x0000000000004000ull
159#define BIT15 0x0000000000008000ull
160#define BIT16 0x0000000000010000ull
161#define BIT17 0x0000000000020000ull
162#define BIT18 0x0000000000040000ull
163#define BIT19 0x0000000000080000ull
164#define BIT20 0x0000000000100000ull
165#define BIT21 0x0000000000200000ull
166#define BIT22 0x0000000000400000ull
167#define BIT23 0x0000000000800000ull
168#define BIT24 0x0000000001000000ull
169#define BIT25 0x0000000002000000ull
170#define BIT26 0x0000000004000000ull
171#define BIT27 0x0000000008000000ull
172#define BIT28 0x0000000010000000ull
173#define BIT29 0x0000000020000000ull
174#define BIT30 0x0000000040000000ull
175#define BIT31 0x0000000080000000ull
176#define BIT32 0x0000000100000000ull
177#define BIT33 0x0000000200000000ull
178#define BIT34 0x0000000400000000ull
179#define BIT35 0x0000000800000000ull
180#define BIT36 0x0000001000000000ull
181#define BIT37 0x0000002000000000ull
182#define BIT38 0x0000004000000000ull
183#define BIT39 0x0000008000000000ull
184#define BIT40 0x0000010000000000ull
185#define BIT41 0x0000020000000000ull
186#define BIT42 0x0000040000000000ull
187#define BIT43 0x0000080000000000ull
188#define BIT44 0x0000100000000000ull
189#define BIT45 0x0000200000000000ull
190#define BIT46 0x0000400000000000ull
191#define BIT47 0x0000800000000000ull
192#define BIT48 0x0001000000000000ull
193#define BIT49 0x0002000000000000ull
194#define BIT50 0x0004000000000000ull
195#define BIT51 0x0008000000000000ull
196#define BIT52 0x0010000000000000ull
197#define BIT53 0x0020000000000000ull
198#define BIT54 0x0040000000000000ull
199#define BIT55 0x0080000000000000ull
200#define BIT56 0x0100000000000000ull
201#define BIT57 0x0200000000000000ull
202#define BIT58 0x0400000000000000ull
203#define BIT59 0x0800000000000000ull
204#define BIT60 0x1000000000000000ull
205#define BIT61 0x2000000000000000ull
206#define BIT62 0x4000000000000000ull
207#define BIT63 0x8000000000000000ull
208
209/// CPUID related registers
210#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information
211#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
212#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul
213#define CPUID_ASSOCIATIVITY_DISABLED 0x00
214#define CPUID_ASSOCIATIVITY_1_WAY 0x01
215#define CPUID_ASSOCIATIVITY_2_WAY 0x02
216#define CPUID_ASSOCIATIVITY_4_WAY 0x04
217#define CPUID_ASSOCIATIVITY_8_WAY 0x06
218#define CPUID_ASSOCIATIVITY_16_WAY 0x08
219#define CPUID_ASSOCIATIVITY_32_WAY 0x0A
220#define CPUID_ASSOCIATIVITY_48_WAY 0x0B
221#define CPUID_ASSOCIATIVITY_64_WAY 0x0C
222#define CPUID_ASSOCIATIVITY_96_WAY 0x0D
223#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
224#define CPUID_ASSOCIATIVITY_FULLY 0x0F
225#define AMD_CPUID_TLB_L1Cache 0x80000005ul
226#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul
227#define AMD_CPUID_APM 0x80000007ul
228#define LOCAL_APIC_ID 24
229#define LOGICAL_PROCESSOR_COUNT 16
230#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count
231
232/// CPU Logical ID Transfer
233typedef struct {
234 UINT32 RawId; ///< RawID
235 UINT16 LogicalId; ///< LogicalID
236} CPU_LOGICAL_ID_XLAT;
237
238/// Logical CPU ID Table
239typedef struct {
240 IN UINT32 Elements; ///< Number of Elements
Marc Jones823dbde2018-01-25 17:05:46 -0700[diff] [blame]241 IN CONST CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]242} LOGICAL_ID_TABLE;
243
244// MSRs
245// ------------------------
246#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR
247#define MSR_MCG_CAP 0x00000179ul
248#define DBG_CTL_MSR 0x000001D9ul
249#define MSR_MC0_CTL 0x00000400ul
250#define MSR_MC0_STATUS 0x00000401ul
251#define MSR_MC0_MISC 0x00000403ul
252#define MSR_MC1_MISC 0x00000407ul
253#define MSR_MC2_MISC 0x0000040Bul
254#define MSR_MC4_MISC0 0x00000413ul
255#define MSR_MC5_MISC 0x00000417ul
256#define MSR_MC4_MISC1 0xC0000408ul
257#define MSR_MC5_STATUS 0x00000415ul
258#define MSR_MC6_STATUS 0x00000419ul
259
260#define MSR_APIC_BAR 0x0000001Bul
261#define MSR_PATCH_LEVEL 0x0000008Bul
262
263#define CPUID_LONG_MODE_ADDR 0x80000008ul
264
265#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul
266#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul
267#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul
268#define MSR_PATCH_LOADER 0xC0010020ul
269
270/// Patch Loader Register
271typedef struct {
272 UINT64 PatchBase:32; ///< Linear address of patch header address block
273 UINT64 SBZ:32; ///< Should be zero
274} PATCH_LOADER_MSR;
275
276#define AMD_MTRR_VARIABLE_BASE0 0x200
277#define AMD_MTRR_VARIABLE_BASE6 0x20C
278#define AMD_MTRR_FIX64k_00000 0x250
279#define AMD_MTRR_FIX16k_80000 0x258
280#define AMD_MTRR_FIX16k_A0000 0x259
281#define AMD_MTRR_FIX4k_C0000 0x268
282#define AMD_MTRR_FIX4k_C8000 0x269
283#define AMD_MTRR_FIX4k_D0000 0x26A
284#define AMD_MTRR_FIX4k_D8000 0x26B
285#define AMD_MTRR_FIX4k_E0000 0x26C
286#define AMD_MTRR_FIX4k_E8000 0x26D
287#define AMD_MTRR_FIX4k_F0000 0x26E
288#define AMD_MTRR_FIX4k_F8000 0x26F
289
290#define AMD_MTRR_FIX64K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
291#define AMD_MTRR_FIX64K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
292#define AMD_MTRR_FIX64K_UC_DRAM 0x1818181818181818ull
293#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
294#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
295#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull
296#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
297#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
298#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull
299
300
301#define MSR_SYS_CFG 0xC0010010ul // SYSCFG
302#define MSR_TOM 0xC001001Aul // TOP_MEM
303#define MSR_TOM2 0xC001001Dul // TOP_MEM2
304#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask
305#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask
306#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask
307#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask
308
309#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features
310#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features
311#define MSR_HDT_CFG 0xC001100Aul
312#define MSR_HWCR 0xC0010015ul
313#define MSR_NB_CFG 0xC001001Ful // NB Config
314#define MSR_HTC 0xC001003Eul
315#define CPU_WDT_CFG 0xC0010074ul
316#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46]
317#define INIT_APIC_CPUID_LO 0x00400000ul // [54]
318#define MSR_CU_SPMCTL 0xC0010281ul
319#define MSR_LS_CFG 0xC0011020ul
320#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared
321#define MSR_DC_CFG 0xC0011022ul
322#define MSR_ME_CFG 0xC0011029ul
323#define MSR_BU_CFG 0xC0011023ul
324#define MSR_CU_CFG 0xC0011023ul // F15 Shared
325#define MSR_DE_CFG 0xC0011029ul // F15 Shared
326#define MSR_BU_CFG2 0xC001102Aul
327#define MSR_CU_CFG2 0xC001102Aul // F15 Shared
328#define MSR_BU_CFG3 0xC001102Bul
329#define MSR_CU_CFG3 0xC001102Bul // F15 Shared
330#define MSR_LS_CFG2 0xC001102Dul
331#define MSR_CU_PFTCFG 0xC001102Ful
332#define MSR_IBS_OP_DATA3 0xC0011037ul
333#define MSR_C001_1070 0xC0011070ul // F15 Shared
334#define MSR_CU_CBBCFG 0xC00110A1ul // F15 CZ
335
336
337#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register
338#define MSR_CPUID_NAME_STRING1 0xC0010031ul
Subrata Banik8e6d5f22020-08-30 13:51:44 +0530[diff] [blame]339#define MSR_CPUID_NAME_STRING2 0xC0010032ul
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]340#define MSR_CPUID_NAME_STRING3 0xC0010033ul
341#define MSR_CPUID_NAME_STRING4 0xC0010034ul
342#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register
343#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register
344#define MSR_BIST 0xC0010060ul // BIST Results register
345#define MSR_OSVW_ID_Length 0xC0010140ul
346#define MSR_OSVW_Status 0xC0010141ul
347#define MSR_NB_PERF_CTL0 0xC0010240ul
348#define MSR_NB_PERF_CTR0 0xC0010241ul
349#define MSR_NB_PERF_CTL1 0xC0010242ul
350#define MSR_NB_PERF_CTR1 0xC0010243ul
351#define MSR_NB_PERF_CTL2 0xC0010244ul
352#define MSR_NB_PERF_CTR2 0xC0010245ul
353#define MSR_NB_PERF_CTL3 0xC0010246ul
354#define MSR_NB_PERF_CTR3 0xC0010247ul
355#define CU_SPMCTL 0xC0010281ul // Streaming Performance Monitor Control
356#define MSR_PERF_CONTROL3 0xC0010003ul // Performance control register number 3
357#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3
358#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits
359#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the
360 // CAR Corruption
361// FUNC_0 registers
362// ----------------
363#define LINK_INIT_CTRL 0x6C
364#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
365#define LINK_INIT_COLD_RST_DET BIT4
366#define LINK_INIT_BIOS_RST_DET_0 BIT5
367#define LINK_INIT_BIOS_RST_DET_1 BIT9
368#define LINK_INIT_BIOS_RST_DET_2 BIT10
369#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10
370#define EXTENDED_NODE_ID 0x160
371
372#define CORE_CTRL 0x1DC
373#define CORE_CTRL_CORE1_EN 0x00000002ul
374#define CORE_CTRL_CORE2_EN 0x00000004ul
375#define CORE_CTRL_CORE3_EN 0x00000008ul
376#define CORE_CTRL_CORE4_EN 0x00000010ul
377#define CORE_CTRL_CORE5_EN 0x00000020ul
378#define CORE_CTRL_CORE6_EN 0x00000040ul
379#define CORE_CTRL_CORE7_EN 0x00000080ul
380#define CORE_CTRL_CORE8_EN 0x00000100ul
381#define CORE_CTRL_CORE9_EN 0x00000200ul
382
383// FUNC_3 registers
384// ----------------
385#define HARDWARE_THERMAL_CTRL_REG 0x64
386#define SOFTWARE_THERMAL_CTRL_REG 0x68
387
388#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
389#define ACPI_PSC_4_REG 0x84
390
391#define NB_CFG_HIGH_REG 0x8C
392#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
393#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
394#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
395#define MULTI_NODE_CPU 29
396#define CPUID_FMR 0xFC // Family / Model registers
397#define DOWNCORE_CTRL 0x190 // Downcore Control Register
398
399#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
400#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
401#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
402
403// FUNC_4 registers
404// ----------------
405/* Native Die CPUID Register F4x160 */
406#define NATIVE_DIE_CPUID_REG 0x160
407#define NATIVE_DIE_CPUID_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, NATIVE_DIE_CPUID_REG))
408
409/// Native Die CPUID PCI Register
410typedef struct {
411 UINT32 Stepping:4; ///< Stepping
412 UINT32 BaseModel:4; ///< Base Model
413 UINT32 BaseFamily:4; ///< Base Family
414 UINT32 :4; ///< Reserved
415 UINT32 ExtModel:4; ///< Extended Model
416 UINT32 ExtFamily:8; ///< Extended Family
417 UINT32 :4; ///< Reserved
418} NATIVE_DIE_CPUID_REGISTER;
419
420// FUNC_5 registers
421// ----------------
422#define COMPUTE_UNIT_STATUS 0x80
423#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
424
425
426// Misc. defines.
427#define PCI_DEV_BASE 24
428
429#define CPUID_STEPPING_MASK 0x0000000Ful
430#define CPUID_BASE_MODEL_MASK 0x000000F0ul
431#define CPUID_BASE_FAMILY_MASK 0x00000F00ul
432#define CPUID_EXT_MODEL_MASK 0x000F0000ul
433#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
434
435#define CZ_SOCKET_FP4 0
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]436#define CZ_SOCKET_AM4 2
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]437#define ST_SOCKET_FP4 0
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]438#define ST_SOCKET_FT4 4
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]439#define SOCKET_IGNORE 0xF
440
441#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
442#define APIC_EXT_BRDCST_MASK 0x000E0000ul
443#define APIC_ENABLE_BIT 0x00000800ul
444#define LOCAL_APIC_ADDR 0xFEE00000ul
445#define INT_CMD_REG_LO 0x300
446#define INT_CMD_REG_HI 0x310
447#define REMOTE_MSG_REG 0x380
448#define REMOTE_READ_REG 0xC0
449#define APIC_ID_REG 0x20
450#define APIC20_ApicId 24
451#define CMD_REG_TO_READ_DATA 0x338
452
453#define MAX_CORE_ID_SIZE 8
454#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
455
456/*-------------------------
457 * Default definitions
458 *-------------------------
459 */
460#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul
461#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul
462#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul
463#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul
464#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul
465#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul
466#define DOWNCORE_MASK_SEVEN 0xFFFFFF80ul
467#define DOWNCORE_MASK_EIGHT 0xFFFFFF00ul
468#define DOWNCORE_MASK_TEN 0xFFFFFC00ul
469#define DOWNCORE_MASK_TWELVE 0xFFFFF000ul
470#define DOWNCORE_MASK_FOURTEEN 0xFFFFC000ul
471#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul
472#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul
473#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul
474#define DOWNCORE_MASK_FIVE_COMPUTE_UNIT 0xFFFFFEAAul
475#define DOWNCORE_MASK_SIX_COMPUTE_UNIT 0xFFFFFAAAul
476#define DOWNCORE_MASK_SEVEN_COMPUTE_UNIT 0xFFFFEAAAul
477#define DOWNCORE_MASK_EIGHT_COMPUTE_UNIT 0xFFFFAAAAul
478
479#define DELIVERY_STATUS BIT13
480#define REMOTE_READ_STAT_MASK 0x00030000ul
481#define REMOTE_DELIVERY_PENDING 0x00010000ul
482#define REMOTE_DELIVERY_DONE 0x00020000ul
483
484/*
485 * --------------------------------------------------------------------------------------
486 *
487 * D E F I N E S / T Y P E D E F S / S T R U C T U R E S
488 *
489 * --------------------------------------------------------------------------------------
490 */
491
492/// CpuEarly param type
493typedef struct {
494 IN UINT8 MemInitPState; ///< Pstate value during memory initial
495 IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options
496} AMD_CPU_EARLY_PARAMS;
497
498/// CPUID
499typedef enum {
500 REG_EAX, ///< EAX
501 REG_EBX, ///< EBX
502 REG_ECX, ///< ECX
503 REG_EDX ///< EDX
504} CPUID_REG;
505
506#endif // _CPU_REGISTERS_H_
507