| Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Vladimir Serbinenko |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include "pch.h" |
| 23 | #include "cpu/intel/model_206ax/model_206ax.h" |
| 24 | #include <cpu/x86/msr.h> |
| 25 | |
| 26 | /* Early thermal init, must be done prior to giving ME its memory |
| 27 | which is done at the end of raminit. */ |
| 28 | void early_thermal_init(void) |
| 29 | { |
| 30 | device_t dev; |
| 31 | msr_t msr; |
| 32 | |
| 33 | dev = PCI_DEV(0x0, 0x1f, 0x6); |
| 34 | |
| 35 | /* Program address for temporary BAR. */ |
| 36 | pci_write_config32(dev, 0x40, 0x40000000); |
| 37 | pci_write_config32(dev, 0x44, 0x0); |
| 38 | |
| 39 | /* Activate temporary BAR. */ |
| 40 | pci_write_config32(dev, 0x40, |
| 41 | pci_read_config32(dev, 0x40) | 5); |
| 42 | |
| 43 | |
| 44 | write16 (0x40000004, 0x3a2b); |
| 45 | write8 (0x4000000c, 0xff); |
| 46 | write8 (0x4000000d, 0x00); |
| 47 | write8 (0x4000000e, 0x40); |
| 48 | write8 (0x40000082, 0x00); |
| 49 | write8 (0x40000001, 0xba); |
| 50 | |
| 51 | /* Perform init. */ |
| 52 | /* Configure TJmax. */ |
| 53 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 54 | write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6); |
| 55 | /* Northbridge temperature slope and offset. */ |
| 56 | write16(0x40000016, 0x808c); |
| 57 | |
| 58 | write16 (0x40000014, 0xde87); |
| 59 | |
| 60 | /* Enable thermal data reporting, processor, PCH and northbridge. */ |
| 61 | write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0); |
| 62 | |
| 63 | /* Disable temporary BAR. */ |
| 64 | pci_write_config32(dev, 0x40, |
| 65 | pci_read_config32(dev, 0x40) & ~1); |
| 66 | pci_write_config32(dev, 0x40, 0); |
| 67 | |
| 68 | write32 (DEFAULT_RCBA | 0x38b0, |
| 69 | (read32 (DEFAULT_RCBA | 0x38b0) & 0xffff8003) | 0x403c); |
| 70 | } |