Ran Bi | 47d46d0 | 2018-10-26 15:18:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2018 MediaTek Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Elyes HAOUAS | 74aa99a | 2019-03-16 08:40:06 +0100 | [diff] [blame^] | 16 | #include <halt.h> |
Ran Bi | 47d46d0 | 2018-10-26 15:18:09 +0800 | [diff] [blame] | 17 | #include <soc/rtc_common.h> |
| 18 | #include <soc/rtc.h> |
| 19 | #include <soc/mt6358.h> |
| 20 | #include <soc/pmic_wrap.h> |
| 21 | |
| 22 | #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) |
| 23 | |
| 24 | /* initialize rtc setting of using dcxo clock */ |
| 25 | static void rtc_enable_dcxo(void) |
| 26 | { |
| 27 | u16 bbpu, con, osc32con, sec; |
| 28 | |
| 29 | pwrap_read(RTC_BBPU, &bbpu); |
| 30 | pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); |
| 31 | rtc_write_trigger(); |
| 32 | |
| 33 | mdelay(1); |
| 34 | if (!rtc_writeif_unlock()) /* Unlock for reload */ |
| 35 | printk(BIOS_INFO, |
| 36 | "[RTC] %s rtc_writeif_unlock() fail\n", __func__); |
| 37 | |
| 38 | pwrap_read(RTC_OSC32CON, &osc32con); |
| 39 | rtc_xosc_write((osc32con & ~RTC_EMBCK_SRC_SEL) |
| 40 | | RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB); |
| 41 | pwrap_read(RTC_BBPU, &bbpu); |
| 42 | pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); |
| 43 | rtc_write_trigger(); |
| 44 | |
| 45 | pwrap_read(RTC_CON, &con); |
| 46 | pwrap_read(RTC_OSC32CON, &osc32con); |
| 47 | pwrap_read(RTC_AL_SEC, &sec); |
| 48 | printk(BIOS_INFO, "[RTC] %s con = 0x%x, osc32con = 0x%x, sec = 0x%x\n", |
| 49 | __func__, con, osc32con, sec); |
| 50 | } |
| 51 | |
| 52 | /* initialize rtc related gpio */ |
| 53 | static int rtc_gpio_init(void) |
| 54 | { |
| 55 | u16 con; |
| 56 | |
| 57 | /* RTC_32K1V8 clock change from 128k div 4 source |
| 58 | * to RTC 32k source |
| 59 | */ |
| 60 | pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3); |
| 61 | |
| 62 | /* Export 32K clock RTC_32K1V8_1 */ |
| 63 | pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1); |
| 64 | |
| 65 | /* Export 32K clock RTC_32K2V8 */ |
| 66 | pwrap_read(RTC_CON, &con); |
| 67 | con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN); |
| 68 | con |= (RTC_CON_GPEN | RTC_CON_GOE); |
| 69 | con &= ~(RTC_CON_F32KOB); |
| 70 | pwrap_write(RTC_CON, con); |
| 71 | return rtc_write_trigger(); |
| 72 | } |
| 73 | |
| 74 | /* set xosc mode */ |
| 75 | void rtc_osc_init(void) |
| 76 | { |
| 77 | /* enable 32K export */ |
| 78 | rtc_gpio_init(); |
| 79 | } |
| 80 | |
| 81 | /* low power detect setting */ |
| 82 | static int rtc_lpd_init(void) |
| 83 | { |
| 84 | u16 con; |
| 85 | |
| 86 | con = pwrap_read(RTC_CON, &con) | RTC_CON_XOSC32_LPEN; |
| 87 | con &= ~RTC_CON_LPRST; |
| 88 | pwrap_write(RTC_CON, con); |
| 89 | if (!rtc_write_trigger()) |
| 90 | return 0; |
| 91 | |
| 92 | con |= RTC_CON_LPRST; |
| 93 | pwrap_write(RTC_CON, con); |
| 94 | if (!rtc_write_trigger()) |
| 95 | return 0; |
| 96 | |
| 97 | con &= ~RTC_CON_LPRST; |
| 98 | pwrap_write(RTC_CON, con); |
| 99 | if (!rtc_write_trigger()) |
| 100 | return 0; |
| 101 | |
| 102 | con = pwrap_read(RTC_CON, &con) | RTC_CON_EOSC32_LPEN; |
| 103 | con &= ~RTC_CON_LPRST; |
| 104 | pwrap_write(RTC_CON, con); |
| 105 | if (!rtc_write_trigger()) |
| 106 | return 0; |
| 107 | |
| 108 | con |= RTC_CON_LPRST; |
| 109 | pwrap_write(RTC_CON, con); |
| 110 | if (!rtc_write_trigger()) |
| 111 | return 0; |
| 112 | |
| 113 | con &= ~RTC_CON_LPRST; |
| 114 | pwrap_write(RTC_CON, con); |
| 115 | if (!rtc_write_trigger()) |
| 116 | return 0; |
| 117 | |
| 118 | return 1; |
| 119 | } |
| 120 | |
| 121 | static bool rtc_hw_init(void) |
| 122 | { |
| 123 | u16 bbpu; |
| 124 | |
| 125 | pwrap_read(RTC_BBPU, &bbpu); |
| 126 | pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT); |
| 127 | rtc_write_trigger(); |
| 128 | |
| 129 | udelay(500); |
| 130 | |
| 131 | pwrap_read(RTC_BBPU, &bbpu); |
| 132 | pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); |
| 133 | rtc_write_trigger(); |
| 134 | |
| 135 | pwrap_read(RTC_BBPU, &bbpu); |
| 136 | if (bbpu & RTC_BBPU_INIT) { |
| 137 | printk(BIOS_INFO, "[RTC] %s:%d timeout\n", __func__, __LINE__); |
| 138 | return false; |
| 139 | } |
| 140 | |
| 141 | return true; |
| 142 | } |
| 143 | |
| 144 | /* rtc init check */ |
| 145 | int rtc_init(u8 recover) |
| 146 | { |
| 147 | printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); |
| 148 | |
| 149 | if (!rtc_writeif_unlock()) |
| 150 | return 0; |
| 151 | |
| 152 | if (!rtc_gpio_init()) |
| 153 | return 0; |
| 154 | |
| 155 | /* using dcxo 32K clock */ |
| 156 | rtc_enable_dcxo(); |
| 157 | |
| 158 | if (recover) |
| 159 | mdelay(20); |
| 160 | |
| 161 | /* write powerkeys */ |
| 162 | pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); |
| 163 | pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); |
| 164 | if (!rtc_write_trigger()) |
| 165 | return 0; |
| 166 | |
| 167 | if (!rtc_reg_init()) |
| 168 | return 0; |
| 169 | if (!rtc_lpd_init()) |
| 170 | return 0; |
| 171 | if (!rtc_hw_init()) |
| 172 | return 0; |
| 173 | |
| 174 | return 1; |
| 175 | } |
| 176 | |
| 177 | /* enable rtc bbpu */ |
| 178 | void rtc_bbpu_power_on(void) |
| 179 | { |
| 180 | u16 bbpu; |
| 181 | int ret; |
| 182 | |
| 183 | /* pull powerhold high, control by pmic */ |
| 184 | pmic_set_power_hold(true); |
| 185 | |
| 186 | /* pull PWRBB high */ |
| 187 | bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; |
| 188 | pwrap_write(RTC_BBPU, bbpu); |
| 189 | ret = rtc_write_trigger(); |
| 190 | printk(BIOS_INFO, "[RTC] %s rtc_write_trigger=%d\n", __func__, ret); |
| 191 | |
| 192 | pwrap_read(RTC_BBPU, &bbpu); |
| 193 | printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu); |
| 194 | } |
| 195 | |
| 196 | void poweroff(void) |
| 197 | { |
| 198 | u16 bbpu; |
| 199 | |
| 200 | if (!rtc_writeif_unlock()) |
| 201 | printk(BIOS_INFO, |
| 202 | "[RTC] %s rtc_writeif_unlock() fail\n", __func__); |
| 203 | /* pull PWRBB low */ |
| 204 | bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; |
| 205 | pwrap_write(RTC_BBPU, bbpu); |
| 206 | |
| 207 | pmic_set_power_hold(false); |
| 208 | halt(); |
| 209 | } |
| 210 | |
| 211 | static void dcxo_init(void) |
| 212 | { |
| 213 | /* Buffer setting */ |
| 214 | pwrap_write(PMIC_RG_DCXO_CW15, 0xA2AA); |
| 215 | pwrap_write(PMIC_RG_DCXO_CW13, 0x98E9); |
| 216 | pwrap_write(PMIC_RG_DCXO_CW16, 0x9855); |
| 217 | |
| 218 | /* 26M enable control */ |
| 219 | /* Enable clock buffer XO_SOC, XO_CEL */ |
| 220 | pwrap_write(PMIC_RG_DCXO_CW00, 0x4805); |
| 221 | pwrap_write(PMIC_RG_DCXO_CW11, 0x8000); |
| 222 | |
| 223 | /* Load thermal coefficient */ |
| 224 | pwrap_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); |
| 225 | pwrap_write(PMIC_RG_DCXO_CW21, 0x12A7); |
| 226 | pwrap_write(PMIC_RG_DCXO_ELR0, 0xD004); |
| 227 | pwrap_write(PMIC_RG_TOP_TMA_KEY, 0x0000); |
| 228 | |
| 229 | /* Adjust OSC FPM setting */ |
| 230 | pwrap_write(PMIC_RG_DCXO_CW07, 0x8FFE); |
| 231 | |
| 232 | /* Re-Calibrate OSC current */ |
| 233 | pwrap_write(PMIC_RG_DCXO_CW09, 0x008F); |
| 234 | udelay(100); |
| 235 | pwrap_write(PMIC_RG_DCXO_CW09, 0x408F); |
| 236 | mdelay(5); |
| 237 | } |
| 238 | |
| 239 | /* the rtc boot flow entry */ |
| 240 | void rtc_boot(void) |
| 241 | { |
| 242 | /* dcxo clock init settings */ |
| 243 | dcxo_init(); |
| 244 | |
| 245 | /* dcxo 32k init settings */ |
| 246 | pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); |
| 247 | pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); |
| 248 | |
| 249 | rtc_boot_common(); |
| 250 | rtc_bbpu_power_on(); |
| 251 | } |