| Werner Zeh | 97c0979 | 2017-04-06 10:01:24 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2017 Siemens AG |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <delay.h> |
| 19 | #include <types.h> |
| Werner Zeh | 97c0979 | 2017-04-06 10:01:24 +0200 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <cpu/x86/cache.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <cpu/x86/smm.h> |
| 24 | #include <spi-generic.h> |
| 25 | #include <elog.h> |
| Werner Zeh | 97c0979 | 2017-04-06 10:01:24 +0200 | [diff] [blame] | 26 | #include <soc/lpc.h> |
| 27 | #include <soc/iomap.h> |
| 28 | #include <soc/pci_devs.h> |
| 29 | #include <soc/smm.h> |
| 30 | |
| Werner Zeh | 97c0979 | 2017-04-06 10:01:24 +0200 | [diff] [blame] | 31 | /** |
| 32 | * @brief Set the EOS bit |
| 33 | */ |
| 34 | void southbridge_smi_set_eos(void) |
| 35 | { |
| 36 | enable_smi(EOS); |
| 37 | } |
| 38 | |
| 39 | static void southbridge_smi_serirq(void) |
| 40 | { |
| 41 | |
| 42 | } |
| 43 | |
| 44 | typedef void (*smi_handler_t)(void); |
| 45 | |
| 46 | static smi_handler_t southbridge_smi[32] = { |
| 47 | NULL, // [0] reserved |
| 48 | NULL, // [1] reserved |
| 49 | NULL, // [2] BIOS_STS |
| 50 | NULL, // [3] LEGACY_USB_STS |
| 51 | NULL, // [4] SLP_SMI_STS |
| 52 | NULL, // [5] APM_STS |
| 53 | NULL, // [6] SWSMI_TMR_STS |
| 54 | NULL, // [7] reserved |
| 55 | NULL, // [8] PM1_STS |
| 56 | NULL, // [9] GPE0_STS |
| 57 | NULL, // [10] GPI_STS |
| 58 | NULL, // [11] MCSMI_STS |
| 59 | NULL, // [12] DEVMON_STS |
| 60 | NULL, // [13] TCO_STS |
| 61 | NULL, // [14] PERIODIC_STS |
| 62 | southbridge_smi_serirq, // [15] SERIRQ_SMI_STS |
| 63 | NULL, // [16] SMBUS_SMI_STS |
| 64 | NULL, // [17] LEGACY_USB2_STS |
| 65 | NULL, // [18] INTEL_USB2_STS |
| 66 | NULL, // [19] reserved |
| 67 | NULL, // [20] PCI_EXP_SMI_STS |
| 68 | NULL, // [21] MONITOR_STS |
| 69 | NULL, // [22] reserved |
| 70 | NULL, // [23] reserved |
| 71 | NULL, // [24] reserved |
| 72 | NULL, // [25] EL_SMI_STS |
| 73 | NULL, // [26] SPI_STS |
| 74 | NULL, // [27] reserved |
| 75 | NULL, // [28] reserved |
| 76 | NULL, // [29] reserved |
| 77 | NULL, // [30] reserved |
| 78 | NULL // [31] reserved |
| 79 | }; |
| 80 | |
| 81 | /** |
| 82 | * @brief Interrupt handler for SMI# |
| 83 | * |
| 84 | * @param smm_revision revision of the smm state save map |
| 85 | */ |
| 86 | |
| 87 | void southbridge_smi_handler(void) |
| 88 | { |
| 89 | int i; |
| 90 | u32 smi_sts; |
| 91 | |
| 92 | /* We need to clear the SMI status registers, or we won't see what's |
| 93 | happening in the following calls. */ |
| 94 | smi_sts = clear_smi_status(); |
| 95 | |
| 96 | /* Call SMI sub handler for each of the status bits */ |
| 97 | for (i = 0; i < 31; i++) { |
| 98 | if (smi_sts & (1 << i)) { |
| 99 | if (southbridge_smi[i]) { |
| 100 | southbridge_smi[i](); |
| 101 | } else { |
| 102 | printk(BIOS_DEBUG, |
| 103 | "SMI_STS[%d] occurred, but no " |
| 104 | "handler available.\n", i); |
| 105 | } |
| 106 | } |
| 107 | } |
| 108 | } |