Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * Helper functions for dealing with power management registers |
| 19 | * and the differences between PCH variants. |
| 20 | */ |
| 21 | |
| 22 | #define __SIMPLE_DEVICE__ |
| 23 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 24 | #include <device/mmio.h> |
Aaron Durbin | bcd0bda | 2017-09-15 12:33:24 -0600 | [diff] [blame] | 25 | #include <cbmem.h> |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <console/console.h> |
| 30 | #include <intelblocks/pmclib.h> |
Aaron Durbin | bcd0bda | 2017-09-15 12:33:24 -0600 | [diff] [blame] | 31 | #include <intelblocks/rtc.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 32 | #include <intelblocks/tco.h> |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 33 | #include <stdlib.h> |
| 34 | #include <soc/gpe.h> |
| 35 | #include <soc/gpio.h> |
| 36 | #include <soc/iomap.h> |
| 37 | #include <soc/lpc.h> |
| 38 | #include <soc/pci_devs.h> |
| 39 | #include <soc/pm.h> |
| 40 | #include <soc/smbus.h> |
| 41 | #include <timer.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 42 | #include <security/vboot/vbnv.h> |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 43 | #include "chip.h" |
| 44 | |
| 45 | /* |
| 46 | * SMI |
| 47 | */ |
| 48 | |
| 49 | const char *const *soc_smi_sts_array(size_t *a) |
| 50 | { |
| 51 | static const char *const smi_sts_bits[] = { |
| 52 | [BIOS_STS_BIT] = "BIOS", |
| 53 | [LEGACY_USB_STS_BIT] = "LEGACY_USB", |
| 54 | [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", |
| 55 | [APM_STS_BIT] = "APM", |
| 56 | [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", |
| 57 | [PM1_STS_BIT] = "PM1", |
| 58 | [GPE0_STS_BIT] = "GPE0", |
| 59 | [GPIO_STS_BIT] = "GPI", |
| 60 | [MCSMI_STS_BIT] = "MCSMI", |
| 61 | [DEVMON_STS_BIT] = "DEVMON", |
| 62 | [TCO_STS_BIT] = "TCO", |
| 63 | [PERIODIC_STS_BIT] = "PERIODIC", |
| 64 | [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", |
| 65 | [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", |
| 66 | [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", |
| 67 | [MONITOR_STS_BIT] = "MONITOR", |
| 68 | [SPI_SMI_STS_BIT] = "SPI", |
| 69 | [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", |
| 70 | [ESPI_SMI_STS_BIT] = "ESPI_SMI", |
| 71 | }; |
| 72 | |
| 73 | *a = ARRAY_SIZE(smi_sts_bits); |
| 74 | return smi_sts_bits; |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * TCO |
| 79 | */ |
| 80 | |
| 81 | const char *const *soc_tco_sts_array(size_t *a) |
| 82 | { |
| 83 | static const char *const tco_sts_bits[] = { |
| 84 | [0] = "NMI2SMI", |
| 85 | [1] = "SW_TCO", |
| 86 | [2] = "TCO_INT", |
| 87 | [3] = "TIMEOUT", |
| 88 | [7] = "NEWCENTURY", |
| 89 | [8] = "BIOSWR", |
| 90 | [9] = "DMISCI", |
| 91 | [10] = "DMISMI", |
| 92 | [12] = "DMISERR", |
| 93 | [13] = "SLVSEL", |
| 94 | [16] = "INTRD_DET", |
| 95 | [17] = "SECOND_TO", |
| 96 | [18] = "BOOT", |
| 97 | [20] = "SMLINK_SLV" |
| 98 | }; |
| 99 | |
| 100 | *a = ARRAY_SIZE(tco_sts_bits); |
| 101 | return tco_sts_bits; |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * GPE0 |
| 106 | */ |
| 107 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 108 | const char *const *soc_std_gpe_sts_array(size_t *a) |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 109 | { |
| 110 | static const char *const gpe_sts_bits[] = { |
| 111 | [1] = "HOTPLUG", |
| 112 | [2] = "SWGPE", |
| 113 | [6] = "TCO_SCI", |
| 114 | [7] = "SMB_WAK", |
| 115 | [9] = "PCI_EXP", |
| 116 | [10] = "BATLOW", |
| 117 | [11] = "PME", |
| 118 | [12] = "ME", |
| 119 | [13] = "PME_B0", |
| 120 | [14] = "eSPI", |
| 121 | [15] = "GPIO Tier-2", |
| 122 | [16] = "LAN_WAKE", |
| 123 | [18] = "WADT" |
| 124 | }; |
| 125 | |
| 126 | *a = ARRAY_SIZE(gpe_sts_bits); |
| 127 | return gpe_sts_bits; |
| 128 | } |
| 129 | |
Lijian Zhao | 26be35a | 2018-04-17 16:13:39 -0700 | [diff] [blame] | 130 | void pmc_set_disb(void) |
| 131 | { |
| 132 | /* Set the DISB after DRAM init */ |
| 133 | uint8_t disb_val; |
| 134 | /* Only care about bits [23:16] of register GEN_PMCON_A */ |
| 135 | uint8_t *addr = (void *)(pmc_mmio_regs() + GEN_PMCON_A + 2); |
| 136 | |
| 137 | disb_val = read8(addr); |
| 138 | disb_val |= (DISB >> 16); |
| 139 | |
| 140 | /* Don't clear bits that are write-1-to-clear */ |
| 141 | disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); |
| 142 | write8(addr, disb_val); |
| 143 | } |
| 144 | |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 145 | /* |
| 146 | * PMC controller gets hidden from PCI bus |
| 147 | * during FSP-Silicon init call. Hence PWRMBASE |
| 148 | * can't be accessible using PCI configuration space |
| 149 | * read/write. |
| 150 | */ |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 151 | uint8_t *pmc_mmio_regs(void) |
| 152 | { |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 153 | return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 154 | } |
| 155 | |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 156 | uintptr_t soc_read_pmc_base(void) |
| 157 | { |
| 158 | return (uintptr_t)pmc_mmio_regs(); |
| 159 | } |
| 160 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 161 | void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 162 | { |
| 163 | DEVTREE_CONST struct soc_intel_cannonlake_config *config; |
| 164 | |
| 165 | /* Look up the device in devicetree */ |
| 166 | DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); |
| 167 | if (!dev || !dev->chip_info) { |
| 168 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
Lijian Zhao | feefbd7 | 2017-08-22 17:40:00 -0700 | [diff] [blame] | 169 | return; |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 170 | } |
| 171 | config = dev->chip_info; |
| 172 | |
| 173 | /* Assign to out variable */ |
| 174 | *dw0 = config->gpe0_dw0; |
| 175 | *dw1 = config->gpe0_dw1; |
| 176 | *dw2 = config->gpe0_dw2; |
| 177 | } |
Aaron Durbin | bcd0bda | 2017-09-15 12:33:24 -0600 | [diff] [blame] | 178 | |
| 179 | static int rtc_failed(uint32_t gen_pmcon_b) |
| 180 | { |
| 181 | return !!(gen_pmcon_b & RTC_BATTERY_DEAD); |
| 182 | } |
| 183 | |
| 184 | int soc_get_rtc_failed(void) |
| 185 | { |
| 186 | const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 187 | |
| 188 | if (!ps) { |
| 189 | printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); |
| 190 | return 1; |
| 191 | } |
| 192 | |
| 193 | return rtc_failed(ps->gen_pmcon_b); |
| 194 | } |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 195 | |
| 196 | int vbnv_cmos_failed(void) |
| 197 | { |
| 198 | return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); |
| 199 | } |
V Sowmya | 5fe77af | 2019-03-06 16:52:57 +0530 | [diff] [blame] | 200 | |
| 201 | static inline int deep_s3_enabled(void) |
| 202 | { |
| 203 | uint32_t deep_s3_pol; |
| 204 | |
| 205 | deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); |
| 206 | return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); |
| 207 | } |
| 208 | |
| 209 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 210 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 211 | int prev_sleep_state) |
| 212 | { |
| 213 | |
| 214 | /* |
| 215 | * Check for any power failure to determine if this a wake from |
| 216 | * S5 because the PCH does not set the WAK_STS bit when waking |
| 217 | * from a true G3 state. |
| 218 | */ |
Furquan Shaikh | 6e401cf | 2019-03-14 15:44:19 -0700 | [diff] [blame] | 219 | if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) |
V Sowmya | 5fe77af | 2019-03-06 16:52:57 +0530 | [diff] [blame] | 220 | prev_sleep_state = ACPI_S5; |
| 221 | |
| 222 | /* |
| 223 | * If waking from S3 determine if deep S3 is enabled. If not, |
| 224 | * need to check both deep sleep well and normal suspend well. |
| 225 | * Otherwise just check deep sleep well. |
| 226 | */ |
| 227 | if (prev_sleep_state == ACPI_S3) { |
| 228 | /* PWR_FLR represents deep sleep power well loss. */ |
| 229 | uint32_t mask = PWR_FLR; |
| 230 | |
| 231 | /* If deep s3 isn't enabled check the suspend well too. */ |
| 232 | if (!deep_s3_enabled()) |
| 233 | mask |= SUS_PWR_FLR; |
| 234 | |
Furquan Shaikh | 6e401cf | 2019-03-14 15:44:19 -0700 | [diff] [blame] | 235 | if (ps->gen_pmcon_a & mask) |
V Sowmya | 5fe77af | 2019-03-06 16:52:57 +0530 | [diff] [blame] | 236 | prev_sleep_state = ACPI_S5; |
| 237 | } |
| 238 | |
| 239 | return prev_sleep_state; |
| 240 | } |
| 241 | |
| 242 | void soc_fill_power_state(struct chipset_power_state *ps) |
| 243 | { |
| 244 | uint8_t *pmc; |
| 245 | |
| 246 | ps->tco1_sts = tco_read_reg(TCO1_STS); |
| 247 | ps->tco2_sts = tco_read_reg(TCO2_STS); |
| 248 | |
| 249 | printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", |
| 250 | ps->tco1_sts, ps->tco2_sts); |
| 251 | |
| 252 | pmc = pmc_mmio_regs(); |
| 253 | ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); |
| 254 | ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); |
| 255 | ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); |
| 256 | ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); |
| 257 | |
| 258 | printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", |
| 259 | ps->gen_pmcon_a, ps->gen_pmcon_b); |
| 260 | |
| 261 | printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", |
| 262 | ps->gblrst_cause[0], ps->gblrst_cause[1]); |
| 263 | } |