Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Angel Pons | 05df108 | 2023-02-08 21:33:44 +0100 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 4 | #include <acpi/acpigen.h> |
Angel Pons | 0b697a24 | 2021-11-25 13:34:11 +0100 | [diff] [blame] | 5 | #include <bootstate.h> |
Patrick Rudolph | 35f0a8f | 2020-11-12 16:41:57 +0100 | [diff] [blame] | 6 | #include <cbmem.h> |
| 7 | #include <console/console.h> |
Elyes Haouas | 1bd23e3 | 2022-10-31 13:13:37 +0100 | [diff] [blame] | 8 | #include <cpu/cpu.h> |
Patrick Rudolph | 35f0a8f | 2020-11-12 16:41:57 +0100 | [diff] [blame] | 9 | #include <crc_byte.h> |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 10 | #include <device/device.h> |
Patrick Rudolph | 35f0a8f | 2020-11-12 16:41:57 +0100 | [diff] [blame] | 11 | #include <device/dram/spd.h> |
Arthur Heymans | f557531 | 2022-03-07 17:39:53 +0100 | [diff] [blame] | 12 | #include <device/pci_ids.h> |
Angel Pons | 4a0dee2 | 2021-12-02 11:45:50 +0100 | [diff] [blame] | 13 | #include <drivers/intel/gma/opregion.h> |
Angel Pons | e81560c | 2021-11-25 13:15:07 +0100 | [diff] [blame] | 14 | #include <gpio.h> |
Angel Pons | 0b697a24 | 2021-11-25 13:34:11 +0100 | [diff] [blame] | 15 | #include <intelblocks/gpio.h> |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 16 | #include <intelblocks/pmclib.h> |
Angel Pons | 0b697a24 | 2021-11-25 13:34:11 +0100 | [diff] [blame] | 17 | #include <smbios.h> |
Angel Pons | 373517c | 2022-09-09 15:15:22 +0200 | [diff] [blame] | 18 | #include <soc/pm.h> |
Angel Pons | c960564 | 2022-09-21 13:30:34 +0200 | [diff] [blame] | 19 | #include <string.h> |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 20 | #include <types.h> |
Angel Pons | e81560c | 2021-11-25 13:15:07 +0100 | [diff] [blame] | 21 | |
| 22 | #include "eeprom.h" |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 23 | #include "gpio.h" |
| 24 | |
Angel Pons | 4a0dee2 | 2021-12-02 11:45:50 +0100 | [diff] [blame] | 25 | const char *mainboard_vbt_filename(void) |
| 26 | { |
| 27 | const struct eeprom_bmc_settings *bmc_cfg = get_bmc_settings(); |
| 28 | |
| 29 | if (bmc_cfg && bmc_cfg->efp3_displayport) |
| 30 | return "vbt-avalanche.bin"; |
| 31 | else |
| 32 | return "vbt.bin"; /* Poseidon */ |
| 33 | } |
| 34 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 35 | /* FIXME: Example code below */ |
| 36 | |
| 37 | static void mb_configure_dp1_pwr(bool enable) |
| 38 | { |
| 39 | gpio_output(GPP_K3, enable); |
| 40 | } |
| 41 | |
| 42 | static void mb_configure_dp2_pwr(bool enable) |
| 43 | { |
| 44 | gpio_output(GPP_K4, enable); |
| 45 | } |
| 46 | |
| 47 | static void mb_configure_dp3_pwr(bool enable) |
| 48 | { |
| 49 | gpio_output(GPP_K5, enable); |
| 50 | } |
| 51 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 52 | static void mb_hda_amp_enable(bool enable) |
| 53 | { |
| 54 | gpio_output(GPP_C19, enable); |
| 55 | } |
| 56 | |
| 57 | static void mb_usb31_rp1_pwr_enable(bool enable) |
| 58 | { |
| 59 | gpio_output(GPP_G0, enable); |
| 60 | } |
| 61 | |
| 62 | static void mb_usb31_rp2_pwr_enable(bool enable) |
| 63 | { |
| 64 | gpio_output(GPP_G1, enable); |
| 65 | } |
| 66 | |
| 67 | static void mb_usb31_fp_pwr_enable(bool enable) |
| 68 | { |
| 69 | gpio_output(GPP_G2, enable); |
| 70 | } |
| 71 | |
| 72 | static void mb_usb2_fp1_pwr_enable(bool enable) |
| 73 | { |
| 74 | gpio_output(GPP_G3, enable); |
| 75 | } |
| 76 | |
| 77 | static void mb_usb2_fp2_pwr_enable(bool enable) |
| 78 | { |
| 79 | gpio_output(GPP_G4, enable); |
| 80 | } |
| 81 | |
Patrick Rudolph | 35f0a8f | 2020-11-12 16:41:57 +0100 | [diff] [blame] | 82 | static void copy_meminfo(const struct dimm_info *dimm, union eeprom_dimm_layout *l) |
| 83 | { |
| 84 | memset(l, 0, sizeof(*l)); |
| 85 | if (dimm->dimm_size == 0) |
| 86 | return; |
| 87 | |
| 88 | strncpy(l->name, (char *)dimm->module_part_number, sizeof(l->name) - 1); |
| 89 | l->capacity_mib = dimm->dimm_size; |
| 90 | l->data_width_bits = 8 * (1 << (dimm->bus_width & 0x7)); |
| 91 | l->bus_width_bits = l->data_width_bits + 8 * ((dimm->bus_width >> 3) & 0x3); |
| 92 | l->ranks = dimm->rank_per_dimm; |
| 93 | l->controller_id = 0; |
| 94 | strncpy(l->manufacturer, spd_manufacturer_name(dimm->mod_id), |
| 95 | sizeof(l->manufacturer) - 1); |
| 96 | } |
| 97 | |
| 98 | /* |
| 99 | * Collect board specific settings and update the CFG EEPROM if necessary. |
| 100 | * This allows the BMC webui to display the current hardware configuration. |
| 101 | */ |
| 102 | static void update_board_layout(void) |
| 103 | { |
| 104 | struct eeprom_board_layout layout = {0}; |
| 105 | |
| 106 | printk(BIOS_INFO, "MB: Collecting Board Layout information\n"); |
| 107 | |
| 108 | /* Update CPU fields */ |
| 109 | for (struct device *cpu = all_devices; cpu; cpu = cpu->next) { |
Fabio Aiuto | 45aae7f | 2022-09-23 16:51:34 +0200 | [diff] [blame] | 110 | if (!is_enabled_cpu(cpu)) |
Patrick Rudolph | 35f0a8f | 2020-11-12 16:41:57 +0100 | [diff] [blame] | 111 | continue; |
| 112 | layout.cpu_count++; |
| 113 | if (!layout.cpu_name[0]) |
| 114 | strcpy(layout.cpu_name, cpu->name); |
| 115 | } |
| 116 | |
| 117 | if (cpuid_get_max_func() >= 0x16) |
| 118 | layout.cpu_max_non_turbo_frequency = cpuid_eax(0x16); |
| 119 | |
| 120 | /* PCH */ |
| 121 | strcpy(layout.pch_name, "Cannonlake-H C246"); |
| 122 | |
| 123 | /* DRAM */ |
| 124 | struct memory_info *meminfo = cbmem_find(CBMEM_ID_MEMINFO); |
| 125 | if (meminfo) { |
| 126 | const size_t meminfo_max = MIN(meminfo->dimm_cnt, ARRAY_SIZE(meminfo->dimm)); |
| 127 | for (size_t i = 0; i < MIN(meminfo_max, ARRAY_SIZE(layout.dimm)); i++) |
| 128 | copy_meminfo(&meminfo->dimm[i], &layout.dimm[i]); |
| 129 | } |
| 130 | |
| 131 | /* Update CRC */ |
| 132 | layout.signature = CRC(layout.raw_layout, sizeof(layout.raw_layout), crc32_byte); |
| 133 | |
| 134 | printk(BIOS_DEBUG, "BOARD LAYOUT:\n"); |
| 135 | printk(BIOS_DEBUG, " Signature : 0x%x\n", layout.signature); |
| 136 | printk(BIOS_DEBUG, " CPU name : %s\n", layout.cpu_name); |
| 137 | printk(BIOS_DEBUG, " CPU count : %u\n", layout.cpu_count); |
| 138 | printk(BIOS_DEBUG, " CPU freq : %u\n", layout.cpu_max_non_turbo_frequency); |
| 139 | printk(BIOS_DEBUG, " PCH name : %s\n", layout.pch_name); |
| 140 | for (size_t i = 0; i < ARRAY_SIZE(layout.dimm); i++) |
| 141 | printk(BIOS_DEBUG, " DRAM SIZE : %u\n", layout.dimm[i].capacity_mib); |
| 142 | |
| 143 | if (write_board_settings(&layout)) |
| 144 | printk(BIOS_ERR, "MB: Failed to update Board Layout\n"); |
| 145 | } |
| 146 | |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 147 | static void mainboard_init(void *chip_info) |
| 148 | { |
Patrick Rudolph | 082f0b9 | 2021-02-08 08:50:46 +0100 | [diff] [blame] | 149 | /* Enable internal speaker amplifier */ |
Angel Pons | 73e6318 | 2023-05-11 15:38:04 +0200 | [diff] [blame^] | 150 | if (get_board_settings()->front_panel_audio == 2) |
Patrick Rudolph | 082f0b9 | 2021-02-08 08:50:46 +0100 | [diff] [blame] | 151 | mb_hda_amp_enable(1); |
| 152 | else |
| 153 | mb_hda_amp_enable(0); |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static void mainboard_final(struct device *dev) |
| 157 | { |
Patrick Rudolph | 35f0a8f | 2020-11-12 16:41:57 +0100 | [diff] [blame] | 158 | update_board_layout(); |
| 159 | |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 160 | /* Encoding: 0 -> S0, 1 -> S5 */ |
Angel Pons | 73e6318 | 2023-05-11 15:38:04 +0200 | [diff] [blame^] | 161 | const bool on = !get_board_settings()->power_state_after_g3; |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 162 | |
| 163 | pmc_soc_set_afterg3_en(on); |
| 164 | } |
| 165 | |
Angel Pons | c960564 | 2022-09-21 13:30:34 +0200 | [diff] [blame] | 166 | static const char *format_pn(const char *prefix, size_t offset) |
| 167 | { |
| 168 | static char buffer[32 + HERMES_SN_PN_LENGTH] = { 0 }; |
| 169 | |
| 170 | const char *part_num = eeprom_read_serial(offset, "N/A"); |
| 171 | |
Angel Pons | bf54142 | 2022-10-11 21:45:30 +0200 | [diff] [blame] | 172 | snprintf(buffer, sizeof(buffer), "%s%s", prefix, part_num); |
Angel Pons | c960564 | 2022-09-21 13:30:34 +0200 | [diff] [blame] | 173 | |
| 174 | return buffer; |
| 175 | } |
| 176 | |
| 177 | static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) |
| 178 | { |
| 179 | const size_t board_offset = offsetof(struct eeprom_layout, board_part_number); |
| 180 | const size_t product_offset = offsetof(struct eeprom_layout, product_part_number); |
| 181 | t->count = smbios_add_string(t->eos, format_pn("Board P/N: ", board_offset)); |
| 182 | t->count = smbios_add_string(t->eos, format_pn("Product P/N: ", product_offset)); |
| 183 | } |
| 184 | |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 185 | #if CONFIG(HAVE_ACPI_TABLES) |
| 186 | static void mainboard_acpi_fill_ssdt(const struct device *dev) |
| 187 | { |
| 188 | const struct eeprom_board_settings *const board_cfg = get_board_settings(); |
| 189 | |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 190 | const unsigned int usb_power_gpios[] = { GPP_G0, GPP_G1, GPP_G2, GPP_G3, GPP_G4 }; |
| 191 | |
| 192 | /* Function pointer to write STXS or CTXS according to EEPROM board setting */ |
| 193 | int (*acpigen_write_soc_gpio_op)(unsigned int gpio_num); |
| 194 | |
| 195 | if (board_cfg->usb_powered_in_s5) |
| 196 | acpigen_write_soc_gpio_op = acpigen_soc_set_tx_gpio; |
| 197 | else |
| 198 | acpigen_write_soc_gpio_op = acpigen_soc_clear_tx_gpio; |
| 199 | |
Patrick Rudolph | 4b29c4a | 2021-04-15 16:28:57 +0200 | [diff] [blame] | 200 | acpigen_write_method("\\_SB.MPTS", 1); |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 201 | { |
Patrick Rudolph | 4b29c4a | 2021-04-15 16:28:57 +0200 | [diff] [blame] | 202 | acpigen_write_if_lequal_op_int(ARG0_OP, 5); |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 203 | { |
Patrick Rudolph | 4b29c4a | 2021-04-15 16:28:57 +0200 | [diff] [blame] | 204 | for (size_t i = 0; i < ARRAY_SIZE(usb_power_gpios); i++) |
| 205 | acpigen_write_soc_gpio_op(usb_power_gpios[i]); |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 206 | } |
| 207 | acpigen_pop_len(); |
Angel Pons | 05df108 | 2023-02-08 21:33:44 +0100 | [diff] [blame] | 208 | |
| 209 | if (!board_cfg->wake_on_usb) { |
| 210 | acpigen_write_if(); |
| 211 | acpigen_emit_byte(LNOT_OP); |
| 212 | acpigen_emit_byte(LLESS_OP); |
| 213 | acpigen_emit_byte(ARG0_OP); |
| 214 | acpigen_write_integer(ACPI_S3); |
| 215 | { |
| 216 | acpigen_write_store_int_to_namestr(0, "\\_SB.PCI0.XHCI.PMEE"); |
| 217 | } |
| 218 | acpigen_pop_len(); |
| 219 | } |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 220 | } |
| 221 | acpigen_pop_len(); |
| 222 | } |
| 223 | #endif |
| 224 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 225 | static void mainboard_enable(struct device *dev) |
| 226 | { |
| 227 | /* FIXME: Do runtime configuration once the board is production ready */ |
| 228 | mb_configure_dp1_pwr(1); |
| 229 | mb_configure_dp2_pwr(1); |
| 230 | mb_configure_dp3_pwr(1); |
Patrick Rudolph | 6c2f34a | 2021-02-08 08:49:06 +0100 | [diff] [blame] | 231 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 232 | mb_usb31_rp1_pwr_enable(1); |
| 233 | mb_usb31_rp2_pwr_enable(1); |
| 234 | mb_usb31_fp_pwr_enable(1); |
| 235 | mb_usb2_fp1_pwr_enable(1); |
| 236 | mb_usb2_fp2_pwr_enable(1); |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 237 | |
| 238 | dev->ops->final = mainboard_final; |
Angel Pons | c960564 | 2022-09-21 13:30:34 +0200 | [diff] [blame] | 239 | dev->ops->get_smbios_strings = mainboard_smbios_strings; |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 240 | |
| 241 | #if CONFIG(HAVE_ACPI_TABLES) |
| 242 | dev->ops->acpi_fill_ssdt = mainboard_acpi_fill_ssdt; |
| 243 | #endif |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 244 | } |
| 245 | |
| 246 | struct chip_operations mainboard_ops = { |
Angel Pons | 20ca7eb | 2020-12-21 18:59:09 +0100 | [diff] [blame] | 247 | .init = mainboard_init, |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 248 | .enable_dev = mainboard_enable, |
| 249 | }; |
Patrick Rudolph | 52ef869 | 2021-02-16 13:16:25 +0100 | [diff] [blame] | 250 | |
Angel Pons | 373517c | 2022-09-09 15:15:22 +0200 | [diff] [blame] | 251 | static void log_reset_causes(void) |
| 252 | { |
| 253 | struct chipset_power_state *ps = pmc_get_power_state(); |
| 254 | |
| 255 | if (!ps) { |
| 256 | printk(BIOS_ERR, "chipset_power_state not found!\n"); |
| 257 | return; |
| 258 | } |
| 259 | |
| 260 | union { |
| 261 | struct eeprom_reset_cause_regs regs; |
| 262 | uint8_t raw[sizeof(struct eeprom_reset_cause_regs)]; |
| 263 | } reset_cause = { |
| 264 | .regs = { |
| 265 | .gblrst_cause0 = ps->gblrst_cause[0], |
| 266 | .gblrst_cause1 = ps->gblrst_cause[1], |
| 267 | .hpr_cause0 = ps->hpr_cause0, |
| 268 | }, |
| 269 | }; |
| 270 | |
| 271 | const size_t base = offsetof(struct eeprom_layout, reset_cause_regs); |
| 272 | for (size_t i = 0; i < ARRAY_SIZE(reset_cause.raw); i++) |
| 273 | eeprom_write_byte(reset_cause.raw[i], base + i); |
| 274 | } |
| 275 | |
Patrick Rudolph | 52ef869 | 2021-02-16 13:16:25 +0100 | [diff] [blame] | 276 | /* Must happen before MPinit */ |
| 277 | static void mainboard_early(void *unused) |
| 278 | { |
| 279 | const struct eeprom_board_settings *const board_cfg = get_board_settings(); |
| 280 | config_t *config = config_of_soc(); |
| 281 | |
Angel Pons | 73e6318 | 2023-05-11 15:38:04 +0200 | [diff] [blame^] | 282 | /* Set Deep Sx */ |
| 283 | config->deep_s5_enable_ac = board_cfg->deep_sx_enabled; |
| 284 | config->deep_s5_enable_dc = board_cfg->deep_sx_enabled; |
Angel Pons | 7a3c416 | 2022-01-31 17:45:04 +0100 | [diff] [blame] | 285 | |
Angel Pons | 73e6318 | 2023-05-11 15:38:04 +0200 | [diff] [blame^] | 286 | config->disable_vmx = board_cfg->vtx_disabled; |
Patrick Rudolph | 52ef869 | 2021-02-16 13:16:25 +0100 | [diff] [blame] | 287 | |
| 288 | if (check_signature(offsetof(struct eeprom_layout, supd), FSPS_UPD_SIGNATURE)) { |
| 289 | struct { |
| 290 | struct { |
| 291 | u8 TurboMode; |
| 292 | } FspsConfig; |
| 293 | } supd = {0}; |
| 294 | |
| 295 | READ_EEPROM_FSP_S((&supd), FspsConfig.TurboMode); |
| 296 | config->cpu_turbo_disable = !supd.FspsConfig.TurboMode; |
| 297 | } |
Angel Pons | 373517c | 2022-09-09 15:15:22 +0200 | [diff] [blame] | 298 | |
| 299 | log_reset_causes(); |
Patrick Rudolph | 52ef869 | 2021-02-16 13:16:25 +0100 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL); |
Arthur Heymans | f557531 | 2022-03-07 17:39:53 +0100 | [diff] [blame] | 303 | |
| 304 | /* |
| 305 | * coreboot only exposes the last framebuffer that is set up. |
| 306 | * The ASPEED BMC will always be initialized after the IGD due to its higher |
| 307 | * bus number. To have coreboot only expose the IGD framebuffer skip the init |
| 308 | * function on the ASPEED. |
| 309 | */ |
| 310 | static void mainboard_configure_internal_gfx(void *unused) |
| 311 | { |
| 312 | struct device *dev; |
Arthur Heymans | f557531 | 2022-03-07 17:39:53 +0100 | [diff] [blame] | 313 | |
Angel Pons | 73e6318 | 2023-05-11 15:38:04 +0200 | [diff] [blame^] | 314 | if (get_board_settings()->primary_video == PRIMARY_VIDEO_INTEL) { |
Arthur Heymans | f557531 | 2022-03-07 17:39:53 +0100 | [diff] [blame] | 315 | dev = dev_find_device(PCI_VID_ASPEED, PCI_DID_ASPEED_AST2050_VGA, NULL); |
| 316 | dev->on_mainboard = false; |
| 317 | dev->enabled = false; |
| 318 | dev->ops->init = NULL; |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, mainboard_configure_internal_gfx, NULL) |