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Vadim Bendebury0b341b32014-04-23 11:09:44 -07001##
2## This file is part of the coreboot project.
3##
4## Copyright 2014 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
20bootblock-y += bootblock.c
Vadim Bendeburydb3e2f02014-04-09 19:23:54 -070021bootblock-y += clock.c
Furquan Shaikh9d91aba2014-04-10 20:35:05 -070022bootblock-y += gpio.c
Vadim Bendebury0e2d9b62014-05-01 19:37:18 -070023bootblock-$(CONFIG_SPI_FLASH) += spi.c
Marc Jones017287a2014-12-29 16:52:59 -070024bootblock-y += timer.c
Vadim Bendebury11c4c922014-04-23 14:26:01 -070025bootblock-$(CONFIG_DRIVERS_UART) += uart.c
Furquan Shaikh76570572014-03-19 14:29:48 -070026
Vadim Bendeburydb3e2f02014-04-09 19:23:54 -070027romstage-y += clock.c
Furquan Shaikh9d91aba2014-04-10 20:35:05 -070028romstage-y += gpio.c
Vadim Bendebury0e2d9b62014-05-01 19:37:18 -070029romstage-$(CONFIG_SPI_FLASH) += spi.c
Marc Jones017287a2014-12-29 16:52:59 -070030romstage-y += timer.c
Vadim Bendebury11c4c922014-04-23 14:26:01 -070031romstage-$(CONFIG_DRIVERS_UART) += uart.c
Vadim Bendebury15c98b02014-05-01 14:45:56 -070032romstage-y += cbmem.c
Furquan Shaikh76570572014-03-19 14:29:48 -070033
Vadim Bendebury15c98b02014-05-01 14:45:56 -070034ramstage-y += cbmem.c
Vadim Bendeburydb3e2f02014-04-09 19:23:54 -070035ramstage-y += clock.c
Furquan Shaikh9d91aba2014-04-10 20:35:05 -070036ramstage-y += gpio.c
Vadim Bendebury41a5d0d2014-05-13 17:47:57 -070037ramstage-y += soc.c
Vadim Bendebury0e2d9b62014-05-01 19:37:18 -070038ramstage-$(CONFIG_SPI_FLASH) += spi.c
Vadim Bendeburyf4b209f2014-04-09 19:23:04 -070039ramstage-y += timer.c
Vadim Bendebury11c4c922014-04-23 14:26:01 -070040ramstage-$(CONFIG_DRIVERS_UART) += uart.c
Julius Werner028cba92014-05-30 18:01:44 -070041ramstage-y += usb.c
Vadim Bendeburyb1709bd2014-04-07 15:26:39 -070042
Julius Werner73d1ed62014-10-20 13:20:49 -070043INCLUDES += -Isrc/soc/qualcomm/ipq806x/include/
44
Vadim Bendebury9cb70ae2014-04-07 18:59:53 -070045ifeq ($(CONFIG_USE_BLOBS),y)
Vadim Bendeburyb1709bd2014-04-07 15:26:39 -070046
Vadim Bendebury9cb70ae2014-04-07 18:59:53 -070047# Generate the actual coreboot bootblock code
48$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
Vadim Bendeburyb1709bd2014-04-07 15:26:39 -070049 @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
Vadim Bendebury9cb70ae2014-04-07 18:59:53 -070050 $(OBJCOPY_bootblock) -O binary $< $@.tmp
Vadim Bendeburyb1709bd2014-04-07 15:26:39 -070051 @mv $@.tmp $@
Vadim Bendebury9cb70ae2014-04-07 18:59:53 -070052
53# Add MBN header to allow SBL3 to start coreboot bootblock
54$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
55 @printf " ADD MBN $(subst $(obj)/,,$(@))\n"
Julius Wernerec5e5e02014-08-20 15:29:56 -070056 ./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
Vadim Bendebury9cb70ae2014-04-07 18:59:53 -070057 @mv $@.tmp $@
58
59# Create a complete bootblock which will start up the system
Vadim Bendeburye83c80c2014-04-15 14:42:30 -070060$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \
Vadim Bendebury9cb70ae2014-04-07 18:59:53 -070061 $(objcbfs)/bootblock.mbn
62 @printf " CAT $(subst $(obj)/,,$(@))\n"
63 @cat $^ > $@.tmp
64 @mv $@.tmp $@
65
Vadim Bendeburyb1709bd2014-04-07 15:26:39 -070066endif
Furquan Shaikh75b4beb2014-04-10 20:53:32 -070067
Furquan Shaikh9d91aba2014-04-10 20:35:05 -070068CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include