Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
Timothy Pearson | b8a355d | 2015-09-05 17:55:58 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Zheng Bao | 69436e1 | 2011-01-06 02:18:12 +0000 | [diff] [blame] | 17 | /* mct_SetDramConfigMisc2_Cx & mct_SetDramConfigMisc2_Dx */ |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 18 | u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2) |
| 19 | { |
| 20 | u32 val; |
| 21 | |
| 22 | if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { |
| 23 | if (pDCTstat->Status & (1 << SB_Registered)) { |
| 24 | misc2 |= 1 << SubMemclkRegDly; |
| 25 | if (mctGet_NVbits(NV_MAX_DIMMS) == 8) |
| 26 | misc2 |= 1 << Ddr3FourSocketCh; |
| 27 | else |
| 28 | misc2 &= ~(1 << Ddr3FourSocketCh); |
| 29 | } |
| 30 | |
| 31 | if (pDCTstat->LogicalCPUID & AMD_DR_Cx) |
| 32 | misc2 |= 1 << OdtSwizzle; |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 33 | val = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x78); |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 34 | |
| 35 | val &= 7; |
Timothy Pearson | b8a355d | 2015-09-05 17:55:58 -0500 | [diff] [blame] | 36 | val = ((~val) & 0xff) + 1; |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 37 | val += 6; |
Timothy Pearson | b8a355d | 2015-09-05 17:55:58 -0500 | [diff] [blame] | 38 | val &= 0x7; |
| 39 | misc2 &= 0xfff8ffff; |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 40 | misc2 |= val << 16; /* DataTxFifoWrDly */ |
Zheng Bao | 69436e1 | 2011-01-06 02:18:12 +0000 | [diff] [blame] | 41 | if (pDCTstat->LogicalCPUID & AMD_DR_Dx) |
| 42 | misc2 |= 1 << 7; /* ProgOdtEn */ |
Zheng Bao | eb75f65 | 2010-04-23 17:32:48 +0000 | [diff] [blame] | 43 | } |
| 44 | return misc2; |
| 45 | } |
Zheng Bao | 69436e1 | 2011-01-06 02:18:12 +0000 | [diff] [blame] | 46 | |
| 47 | void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat) |
| 48 | { |
| 49 | u32 val; |
| 50 | |
| 51 | if (pDCTstat->LogicalCPUID & (AMD_DR_Cx)) { |
Timothy Pearson | b8a355d | 2015-09-05 17:55:58 -0500 | [diff] [blame] | 52 | /* Revision C */ |
| 53 | Set_NB32(pDCTstat->dev_dct, 0x11c, 0x0ce00fc0 | 1 << 29/* FlushWrOnStpGnt */); |
Zheng Bao | 69436e1 | 2011-01-06 02:18:12 +0000 | [diff] [blame] | 54 | |
Timothy Pearson | b8a355d | 2015-09-05 17:55:58 -0500 | [diff] [blame] | 55 | val = Get_NB32(pDCTstat->dev_dct, 0x1b0); |
| 56 | val &= ~0x73f; |
Zheng Bao | 69436e1 | 2011-01-06 02:18:12 +0000 | [diff] [blame] | 57 | val |= 0x101; /* BKDG recommended settings */ |
Timothy Pearson | b8a355d | 2015-09-05 17:55:58 -0500 | [diff] [blame] | 58 | |
| 59 | Set_NB32(pDCTstat->dev_dct, 0x1b0, val); |
Zheng Bao | 69436e1 | 2011-01-06 02:18:12 +0000 | [diff] [blame] | 60 | } |
| 61 | } |