Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 3 | * |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 16 | /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ |
| 17 | |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 18 | /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 19 | #define AMD_SAFEMODE 0x8000000000000000 /* Unknown future revision - SAFE MODE */ |
| 20 | #define AMD_NPT_F0 0x0000000000000001 /* F0 stepping */ |
| 21 | #define AMD_NPT_F1 0x0000000000000002 /* F1 stepping */ |
| 22 | #define AMD_NPT_F2C 0x0000000000000004 |
| 23 | #define AMD_NPT_F2D 0x0000000000000008 |
| 24 | #define AMD_NPT_F2E 0x0000000000000010 /* F2 stepping E */ |
| 25 | #define AMD_NPT_F2G 0x0000000000000020 /* F2 stepping G */ |
| 26 | #define AMD_NPT_F2J 0x0000000000000040 |
| 27 | #define AMD_NPT_F2K 0x0000000000000080 |
| 28 | #define AMD_NPT_F3L 0x0000000000000100 /* F3 Stepping */ |
| 29 | #define AMD_NPT_G0A 0x0000000000000200 /* G0 stepping */ |
| 30 | #define AMD_NPT_G1B 0x0000000000000400 /* G1 stepping */ |
| 31 | #define AMD_DR_A0A 0x0000000000010000 /* Barcelona A0 */ |
| 32 | #define AMD_DR_A1B 0x0000000000020000 /* Barcelona A1 */ |
| 33 | #define AMD_DR_A2 0x0000000000040000 /* Barcelona A2 */ |
| 34 | #define AMD_DR_B0 0x0000000000080000 /* Barcelona B0 */ |
| 35 | #define AMD_DR_B1 0x0000000000100000 /* Barcelona B1 */ |
| 36 | #define AMD_DR_B2 0x0000000000200000 /* Barcelona B2 */ |
| 37 | #define AMD_DR_BA 0x0000000000400000 /* Barcelona BA */ |
| 38 | #define AMD_DR_B3 0x0000000000800000 /* Barcelona B3 */ |
| 39 | #define AMD_RB_C2 0x0000000001000000 /* Shanghai C2 */ |
| 40 | #define AMD_DA_C2 0x0000000002000000 /* XXXX C2 */ |
| 41 | #define AMD_HY_D0 0x0000000004000000 /* Istanbul D0 */ |
| 42 | #define AMD_RB_C3 0x0000000008000000 /* ??? C3 */ |
| 43 | #define AMD_DA_C3 0x0000000010000000 /* XXXX C3 */ |
| 44 | #define AMD_HY_D1 0x0000000020000000 /* Istanbul D1 */ |
| 45 | #define AMD_PH_E0 0x0000000040000000 /* Phenom II X4 X6 */ |
| 46 | #define AMD_OR_B2 0x0000000080000000 /* Interlagos */ |
| 47 | #define AMD_OR_C0 0x0000000100000000 /* Abu Dhabi */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 48 | |
| 49 | /* |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 50 | * Groups - Create as many as you wish, from the above public values |
| 51 | */ |
| 52 | #define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 53 | #define AMD_NPT_F3 (AMD_NPT_F3L) |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 54 | #define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3) |
| 55 | #define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B) |
| 56 | #define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx) |
| 57 | #define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2) |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 58 | #define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 59 | #define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) |
| 60 | #define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) |
Marc Jones | c3ec1ac | 2008-07-23 21:04:03 +0000 | [diff] [blame] | 61 | #define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA) |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 62 | #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) |
| 63 | #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 64 | #define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 65 | #define AMD_DR_ALL (AMD_DR_Bx) |
QingPei Wang | 8eb4273 | 2011-09-13 18:04:22 +0800 | [diff] [blame] | 66 | #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) |
Xavi Drudis Ferran | e485aa4 | 2011-02-28 02:33:59 +0000 | [diff] [blame] | 67 | #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) |
Marc Jones | 99fd2a3 | 2009-05-14 23:42:41 +0000 | [diff] [blame] | 68 | #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) |
Timothy Pearson | 226fc94 | 2015-02-20 17:00:50 -0600 | [diff] [blame] | 69 | #define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) |
Xavi Drudis Ferran | 0e5d3e1 | 2011-02-28 00:18:43 +0000 | [diff] [blame] | 70 | #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) |
| 71 | #define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) |
| 72 | #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) |
Zheng Bao | 2ca2f17 | 2011-03-28 04:29:14 +0000 | [diff] [blame] | 73 | #define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1) |
| 74 | #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) |
| 75 | #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) |
| 76 | #define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3) |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 77 | #define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0) |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 78 | |
| 79 | /* |
| 80 | * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE |
| 81 | */ |
| 82 | #define AMD_PTYPE_DSK 0x001 /* Desktop/DTR/UP */ |
| 83 | #define AMD_PTYPE_MOB 0x002 /* Mobile/Cool-n-quiet */ |
| 84 | #define AMD_PTYPE_SVR 0x004 /* Workstation/Server/Multicore DT */ |
| 85 | #define AMD_PTYPE_UC 0x008 /* Single Core */ |
| 86 | #define AMD_PTYPE_DC 0x010 /* Dual Core */ |
| 87 | #define AMD_PTYPE_MC 0x020 /* Multi Core (>2) */ |
| 88 | #define AMD_PTYPE_UMA 0x040 /* UMA required */ |
| 89 | |
| 90 | /* |
| 91 | * Groups - Create as many as you wish, from the above public values |
| 92 | */ |
| 93 | #define AMD_PTYPE_ALL 0xFFFFFFFF /* A mask for all */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 94 | |
| 95 | |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 96 | /* |
| 97 | * CPU PCI HT PHY REGISTER, LINK TYPES - PRIVATE |
| 98 | */ |
| 99 | #define HTPHY_LINKTYPE_HT3 0x00000001 |
| 100 | #define HTPHY_LINKTYPE_HT1 0x00000002 |
| 101 | #define HTPHY_LINKTYPE_COHERENT 0x00000004 |
| 102 | #define HTPHY_LINKTYPE_NONCOHERENT 0x00000008 |
| 103 | #define HTPHY_LINKTYPE_CONNECTED (HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT) |
| 104 | #define HTPHY_LINKTYPE_GANGED 0x00000010 |
| 105 | #define HTPHY_LINKTYPE_UNGANGED 0x00000020 |
| 106 | #define HTPHY_LINKTYPE_ALL 0x7FFFFFFF |
| 107 | |
| 108 | |
| 109 | /* |
| 110 | * CPU HT PHY REGISTERS, FIELDS, AND MASKS |
| 111 | */ |
| 112 | #define HTPHY_OFFSET_MASK 0xE00001FF |
| 113 | #define HTPHY_WRITE_CMD 0x40000000 |
| 114 | #define HTPHY_IS_COMPLETE_MASK 0x80000000 |
| 115 | #define HTPHY_DIRECT_MAP 0x20000000 |
| 116 | #define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF |
| 117 | |
| 118 | |
| 119 | /* |
| 120 | * Various AMD MSRs |
| 121 | */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 122 | #define CPUID_EXT_PM 0x80000007 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 123 | #define CPUID_MODEL 1 |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 124 | #define MCG_CAP 0x00000179 |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 125 | #define MCG_CTL_P 8 |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 126 | #define MC0_CTL 0x00000400 |
| 127 | #define MC0_STA (MC0_CTL + 1) |
| 128 | #define MC4_MISC0 0x00000413 |
| 129 | #define MC4_MISC1 0xC0000408 |
| 130 | #define MC4_MISC2 0xC0000409 |
| 131 | #define FS_Base 0xC0000100 |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 132 | #define SYSCFG 0xC0010010 |
| 133 | #define HWCR 0xC0010015 |
| 134 | #define NB_CFG 0xC001001F |
| 135 | #define FidVidStatus 0xC0010042 |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 136 | #define MC1_CTL_MASK 0xC0010045 |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 137 | #define MC4_CTL_MASK 0xC0010048 |
| 138 | #define OSVW_ID_Length 0xC0010140 |
| 139 | #define OSVW_Status 0xC0010141 |
| 140 | #define CPUIDFEATURES 0xC0011004 |
| 141 | #define LS_CFG 0xC0011020 |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 142 | #define IC_CFG 0xC0011021 |
Marc Jones | da4ce6b | 2008-04-22 22:11:31 +0000 | [diff] [blame] | 143 | #define DC_CFG 0xC0011022 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 144 | #define BU_CFG 0xC0011023 |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 145 | #define FP_CFG 0xC0011028 |
| 146 | #define DE_CFG 0xC0011029 |
| 147 | #define BU_CFG2 0xC001102A |
| 148 | #define BU_CFG3 0xC001102B |
| 149 | #define EX_CFG 0xC001102C |
| 150 | #define LS_CFG2 0xC001102D |
| 151 | #define IBS_OP_DATA3 0xC0011037 |
Xavi Drudis Ferran | adb23a5 | 2011-02-28 00:10:37 +0000 | [diff] [blame] | 152 | |
| 153 | /* |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 154 | * Processor package types |
Xavi Drudis Ferran | adb23a5 | 2011-02-28 00:10:37 +0000 | [diff] [blame] | 155 | */ |
| 156 | #define AMD_PKGTYPE_FrX_1207 0 |
| 157 | #define AMD_PKGTYPE_AM3_2r2 1 |
| 158 | #define AMD_PKGTYPE_S1gX 2 |
| 159 | #define AMD_PKGTYPE_G34 3 |
| 160 | #define AMD_PKGTYPE_ASB2 4 |
| 161 | #define AMD_PKGTYPE_C32 5 |