| Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /* Configure various power control registers, including processor boost |
| 21 | * and TDP monitoring support. |
| 22 | */ |
| 23 | |
| 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <device/pci_ops.h> |
| 29 | #include <pc80/mc146818rtc.h> |
| 30 | #include <lib.h> |
| 31 | #include <cpu/amd/model_10xxx_rev.h> |
| 32 | |
| 33 | #include "amdfam10.h" |
| 34 | |
| 35 | static void nb_control_init(struct device *dev) |
| 36 | { |
| 37 | uint32_t dword; |
| 38 | uint32_t f5x80; |
| 39 | uint8_t cu_enabled; |
| 40 | uint8_t compute_unit_count = 0; |
| 41 | |
| 42 | printk(BIOS_DEBUG, "NB: Function 5 Northbridge Control.. "); |
| 43 | |
| 44 | /* Determine the number of active compute units on this node */ |
| 45 | f5x80 = pci_read_config32(dev, 0x80); |
| 46 | cu_enabled = f5x80 & 0xf; |
| 47 | if (cu_enabled == 0x1) |
| 48 | compute_unit_count = 1; |
| 49 | if (cu_enabled == 0x3) |
| 50 | compute_unit_count = 2; |
| 51 | if (cu_enabled == 0x7) |
| 52 | compute_unit_count = 3; |
| 53 | if (cu_enabled == 0xf) |
| 54 | compute_unit_count = 4; |
| 55 | |
| 56 | /* Configure Processor TDP Running Average */ |
| 57 | dword = pci_read_config32(dev, 0xe0); |
| 58 | dword &= ~0xf; /* RunAvgRange = 0x9 */ |
| 59 | dword |= 0x9; |
| 60 | pci_write_config32(dev, 0xe0, dword); |
| 61 | |
| 62 | /* Configure northbridge P-states */ |
| 63 | dword = pci_read_config32(dev, 0xe0); |
| 64 | dword &= ~(0x7 << 9); /* NbPstateThreshold = compute_unit_count */ |
| 65 | dword |= (compute_unit_count & 0x7) << 9; |
| 66 | pci_write_config32(dev, 0xe0, dword); |
| 67 | |
| 68 | printk(BIOS_DEBUG, "done.\n"); |
| 69 | } |
| 70 | |
| 71 | |
| 72 | static struct device_operations mcf5_ops = { |
| 73 | .read_resources = pci_dev_read_resources, |
| 74 | .set_resources = pci_dev_set_resources, |
| 75 | .enable_resources = pci_dev_enable_resources, |
| 76 | .init = nb_control_init, |
| 77 | .scan_bus = 0, |
| 78 | .ops_pci = 0, |
| 79 | }; |
| 80 | |
| 81 | static const struct pci_driver mcf5_driver_fam15 __pci_driver = { |
| 82 | .ops = &mcf5_ops, |
| 83 | .vendor = PCI_VENDOR_ID_AMD, |
| 84 | .device = 0x1605, |
| 85 | }; |