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review.coreboot.org / coreboot / 730a043fb6cb4dd3cb5af8f8640365727b598648 / . / src / northbridge / amd / amdfam10 / amdfam10_util.c
blob: 0ef6c92b491bb3ac3399b85455ce613ed0df8912 [file] [log] [blame]
Timothy Pearsonead87512015-02-20 12:47:52 -0600[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
5 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Timothy Pearsonead87512015-02-20 12:47:52 -0600[diff] [blame]15 */
16
17#include <console/console.h>
18
19#include <arch/cpu.h>
Timothy Pearson620fa5f2015-03-27 22:50:09 -0500[diff] [blame]20#include <northbridge/amd/amdmct/wrappers/mcti.h>
Timothy Pearsonead87512015-02-20 12:47:52 -0600[diff] [blame]21#include <northbridge/amd/amdmct/mct/mct_d.h>
22#include <northbridge/amd/amdmct/amddefs.h>
23
24#ifndef __PRE_RAM__
25#include <include/device/pci_ops.h>
26#include <include/device/pci_def.h>
27u32 Get_NB32(u32 dev, u32 reg)
28{
29 return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
30}
31#endif
32
Timothy Pearson730a0432015-10-16 13:51:51 -0500[diff] [blame^]33uint64_t mctGetLogicalCPUID(u32 Node)
Timothy Pearsonead87512015-02-20 12:47:52 -0600[diff] [blame]34{
35 /* Converts the CPUID to a logical ID MASK that is used to check
36 CPU version support versions */
37 u32 dev;
38 u32 val, valx;
39 u32 family, model, stepping;
Timothy Pearson730a0432015-10-16 13:51:51 -0500[diff] [blame^]40 uint64_t ret;
Timothy Pearsonead87512015-02-20 12:47:52 -0600[diff] [blame]41
42 if (Node == 0xFF) { /* current node */
43 val = cpuid_eax(0x80000001);
44 } else {
45 dev = PA_NBMISC(Node);
46 val = Get_NB32(dev, 0xfc);
47 }
48
49 family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
50 model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
51 stepping = val & 0x0f;
52
53 valx = (family << 12) | (model << 4) | (stepping);
54
55 switch (valx) {
56 case 0x10000:
57 ret = AMD_DR_A0A;
58 break;
59 case 0x10001:
60 ret = AMD_DR_A1B;
61 break;
62 case 0x10002:
63 ret = AMD_DR_A2;
64 break;
65 case 0x10020:
66 ret = AMD_DR_B0;
67 break;
68 case 0x10021:
69 ret = AMD_DR_B1;
70 break;
71 case 0x10022:
72 ret = AMD_DR_B2;
73 break;
74 case 0x10023:
75 ret = AMD_DR_B3;
76 break;
77 case 0x10042:
78 ret = AMD_RB_C2;
79 break;
80 case 0x10043:
81 ret = AMD_RB_C3;
82 break;
83 case 0x10062:
84 ret = AMD_DA_C2;
85 break;
86 case 0x10063:
87 ret = AMD_DA_C3;
88 break;
89 case 0x10080:
90 ret = AMD_HY_D0;
91 break;
92 case 0x10081:
93 case 0x10091:
94 ret = AMD_HY_D1;
95 break;
96 case 0x100a0:
97 ret = AMD_PH_E0;
98 break;
Timothy Pearson730a0432015-10-16 13:51:51 -0500[diff] [blame^]99 case 0x15012:
100 case 0x1501f:
101 ret = AMD_OR_B2;
102 break;
103 case 0x15020:
104 ret = AMD_OR_C0;
105 break;
Timothy Pearsonead87512015-02-20 12:47:52 -0600[diff] [blame]106 default:
107 /* FIXME: mabe we should die() here. */
Timothy Pearson730a0432015-10-16 13:51:51 -0500[diff] [blame^]108 printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! %08x\n", valx);
Timothy Pearsonead87512015-02-20 12:47:52 -0600[diff] [blame]109 ret = 0;
110 }
111
112 return ret;
113}