| Kyösti Mälkki | 717b6e3 | 2018-05-17 14:16:03 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | // Use simple device model for this file even in ramstage |
| 15 | #define __SIMPLE_DEVICE__ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <arch/cpu.h> |
| 19 | #include <cbmem.h> |
| 20 | #include <console/console.h> |
| 21 | #include <cpu/intel/romstage.h> |
| 22 | #include <cpu/x86/mtrr.h> |
| 23 | #include <program_loading.h> |
| 24 | #include "e7505.h" |
| 25 | |
| 26 | void *cbmem_top(void) |
| 27 | { |
| 28 | pci_devfn_t mch = PCI_DEV(0, 0, 0); |
| 29 | uintptr_t tolm; |
| 30 | |
| 31 | /* This is at 128 MiB boundary. */ |
| 32 | tolm = pci_read_config16(mch, TOLM) >> 11; |
| 33 | tolm <<= 27; |
| 34 | |
| 35 | return (void *)tolm; |
| 36 | } |
| 37 | |
| 38 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
| 39 | |
| 40 | /* setup_stack_and_mtrrs() determines the stack to use after |
| 41 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
| 42 | void *setup_stack_and_mtrrs(void) |
| 43 | { |
| 44 | struct postcar_frame pcf; |
| 45 | uintptr_t top_of_ram; |
| 46 | |
| 47 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 48 | die("Unable to initialize postcar frame.\n"); |
| 49 | |
| 50 | /* Cache the ROM as WP just below 4GiB. */ |
| 51 | postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, |
| 52 | MTRR_TYPE_WRPROT); |
| 53 | |
| 54 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 55 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 56 | |
| 57 | /* Cache CBMEM region as WB. */ |
| 58 | top_of_ram = (uintptr_t)cbmem_top(); |
| 59 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, |
| 60 | MTRR_TYPE_WRBACK); |
| 61 | |
| 62 | /* Save the number of MTRRs to setup. Return the stack location |
| 63 | * pointing to the number of MTRRs. |
| 64 | */ |
| 65 | return postcar_commit_mtrrs(&pcf); |
| 66 | } |