Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stddef.h> |
| 18 | #include <arch/cpu.h> |
| 19 | #include <lib.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <arch/cbfs.h> |
| 22 | #include <arch/stages.h> |
| 23 | #include <console/console.h> |
| 24 | #include <cbmem.h> |
| 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <romstage_handoff.h> |
| 27 | #include <timestamp.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 28 | #include <soc/gpio.h> |
| 29 | #include <soc/iomap.h> |
| 30 | #include <soc/lpc.h> |
| 31 | #include <soc/pci_devs.h> |
| 32 | #include <soc/romstage.h> |
| 33 | #include <soc/acpi.h> |
| 34 | #include <soc/baytrail.h> |
Marc Jones | 7868797 | 2015-04-22 23:16:31 -0600 | [diff] [blame] | 35 | #include <drivers/intel/fsp1_0/fsp_util.h> |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 36 | #include "modhwinfo.h" |
| 37 | |
| 38 | /** |
| 39 | * /brief mainboard call for setup that needs to be done before fsp init |
| 40 | * |
| 41 | */ |
| 42 | void early_mainboard_romstage_entry() |
| 43 | { |
| 44 | |
| 45 | } |
| 46 | |
| 47 | /** |
| 48 | * Get function disables - most of these will be done automatically |
| 49 | * @param fd_mask |
| 50 | * @param fd2_mask |
| 51 | */ |
| 52 | void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) |
| 53 | { |
| 54 | |
| 55 | } |
| 56 | |
| 57 | /** |
| 58 | * /brief mainboard call for setup that needs to be done after fsp init |
| 59 | * |
| 60 | */ |
| 61 | void late_mainboard_romstage_entry() |
| 62 | { |
| 63 | |
| 64 | } |
| 65 | |
| 66 | const uint32_t mAzaliaVerbTableData13[] = { |
| 67 | /* |
| 68 | *ALC262 Verb Table - 10EC0262 |
| 69 | */ |
| 70 | /* Pin Complex (NID 0x11 ) */ |
| 71 | 0x01171CF0, |
| 72 | 0x01171D11, |
| 73 | 0x01171E11, |
| 74 | 0x01171F41, |
| 75 | /* Pin Complex (NID 0x12 ) */ |
| 76 | 0x01271CF0, |
| 77 | 0x01271D11, |
| 78 | 0x01271E11, |
| 79 | 0x01271F41, |
| 80 | /* Pin Complex (NID 0x14 ) */ |
| 81 | 0x01471C10, |
| 82 | 0x01471D40, |
| 83 | 0x01471E01, |
| 84 | 0x01471F01, |
| 85 | /* Pin Complex (NID 0x15 ) */ |
| 86 | 0x01571CF0, |
| 87 | 0x01571D11, |
| 88 | 0x01571E11, |
| 89 | 0x01571F41, |
| 90 | /* Pin Complex (NID 0x16 ) */ |
| 91 | 0x01671CF0, |
| 92 | 0x01671D11, |
| 93 | 0x01671E11, |
| 94 | 0x01671F41, |
| 95 | /* Pin Complex (NID 0x18 ) */ |
| 96 | 0x01871C20, |
| 97 | 0x01871D98, |
| 98 | 0x01871EA1, |
| 99 | 0x01871F01, |
| 100 | /* Pin Complex (NID 0x19 ) */ |
| 101 | 0x01971C21, |
| 102 | 0x01971D98, |
| 103 | 0x01971EA1, |
| 104 | 0x01971F02, |
| 105 | /* Pin Complex (NID 0x1A ) */ |
| 106 | 0x01A71C2F, |
| 107 | 0x01A71D30, |
| 108 | 0x01A71E81, |
| 109 | 0x01A71F01, |
| 110 | /* Pin Complex (NID 0x1B ) */ |
| 111 | 0x01B71C1F, |
| 112 | 0x01B71D40, |
| 113 | 0x01B71E21, |
| 114 | 0x01B71F02, |
| 115 | /* Pin Complex (NID 0x1C ) */ |
| 116 | 0x01C71CF0, |
| 117 | 0x01C71D11, |
| 118 | 0x01C71E11, |
| 119 | 0x01C71F41, |
| 120 | /* Pin Complex (NID 0x1D ) */ |
| 121 | 0x01D71C01, |
| 122 | 0x01D71DC6, |
| 123 | 0x01D71E14, |
| 124 | 0x01D71F40, |
| 125 | /* Pin Complex (NID 0x1E ) */ |
| 126 | 0x01E71CF0, |
| 127 | 0x01E71D11, |
| 128 | 0x01E71E11, |
| 129 | 0x01E71F41, |
| 130 | /* Pin Complex (NID 0x1F ) */ |
| 131 | 0x01F71CF0, |
| 132 | 0x01F71D11, |
| 133 | 0x01F71E11, |
| 134 | 0x01F71F41 }; |
| 135 | |
| 136 | const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { |
| 137 | /* |
| 138 | * VerbTable: (RealTek ALC262) |
| 139 | * Revision ID = 0xFF, support all steps |
| 140 | * Codec Verb Table For AZALIA |
| 141 | * Codec Address: CAd value (0/1/2) |
| 142 | * Codec Vendor: 0x10EC0262 |
| 143 | */ |
| 144 | { |
| 145 | 0x10EC0262, /* Vendor ID/Device IDA */ |
| 146 | 0x0000, /* SubSystem ID */ |
| 147 | 0xFF, /* Revision IDA */ |
| 148 | 0x01, /* Front panel support (1=yes, 2=no) */ |
| 149 | 0x000B, /* Number of Rear Jacks = 11 */ |
| 150 | 0x0002 /* Number of Front Jacks = 2 */ |
| 151 | }, |
| 152 | (uint32_t *)mAzaliaVerbTableData13 } }; |
| 153 | |
| 154 | const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { |
| 155 | .Pme = 1, |
| 156 | .DS = 1, |
| 157 | .DA = 0, |
| 158 | .HdmiCodec = 1, |
| 159 | .AzaliaVCi = 1, |
| 160 | .Rsvdbits = 0, |
| 161 | .AzaliaVerbTableNum = 1, |
| 162 | .AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable, |
| 163 | .ResetWaitTimer = 300 }; |
| 164 | |
| 165 | /** /brief customize fsp parameters here if needed |
| 166 | */ |
| 167 | void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) |
| 168 | { |
| 169 | struct hwinfo *hwi_main; |
| 170 | UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; |
| 171 | |
| 172 | /* Initialize the Azalia Verb Tables to mainboard specific version */ |
| 173 | UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; |
| 174 | |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 175 | /* Get SPD data from hardware information block and setup memory down */ |
| 176 | /* parameters for FSP accordingly */ |
| 177 | hwi_main = get_hwinfo((char*)"hwinfo.hex"); |
| 178 | if (hwi_main) { |
| 179 | UpdData->PcdMemoryParameters.EnableMemoryDown = 1; |
| 180 | UpdData->PcdMemoryParameters.DRAMType = hwi_main->SPD[2]; |
| 181 | UpdData->PcdMemoryParameters.DIMM0Enable = hwi_main->SPD[3] & 0x01; |
| 182 | UpdData->PcdMemoryParameters.DIMM1Enable = (hwi_main->SPD[3] >> 1) & 0x01; |
| 183 | UpdData->PcdMemoryParameters.DIMMDensity = hwi_main->SPD[4]; |
| 184 | UpdData->PcdMemoryParameters.DIMMDWidth = hwi_main->SPD[5]; |
| 185 | UpdData->PcdMemoryParameters.DIMMSides = hwi_main->SPD[7]; |
| 186 | UpdData->PcdMemoryParameters.DIMMBusWidth = hwi_main->SPD[8]; |
| 187 | UpdData->PcdMemoryParameters.DRAMSpeed = hwi_main->SPD[12]; |
| 188 | UpdData->PcdMemoryParameters.DIMMtCL = hwi_main->SPD[14]; |
| 189 | UpdData->PcdMemoryParameters.DIMMtWR = hwi_main->SPD[17]; |
| 190 | UpdData->PcdMemoryParameters.DIMMtRPtRCD = hwi_main->SPD[18]; |
| 191 | UpdData->PcdMemoryParameters.DIMMtRRD = hwi_main->SPD[19]; |
| 192 | UpdData->PcdMemoryParameters.DIMMtWTR = hwi_main->SPD[26]; |
| 193 | UpdData->PcdMemoryParameters.DIMMtRTP = hwi_main->SPD[27]; |
| 194 | UpdData->PcdMemoryParameters.DIMMtFAW = hwi_main->SPD[28]; |
| 195 | /*If one need output from MRC to be used in Intel RMT, simply */ |
| 196 | /*enable the following line */ |
| 197 | //UpdData->PcdMrcDebugMsg = 1; |
| 198 | } else |
| 199 | printk(BIOS_ERR, "HWInfo not found, leave default timings for DDR3.\n"); |
| 200 | } |