Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 5 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | |
| 18 | #ifndef _PLATFORM_CFG_H_ |
| 19 | #define _PLATFORM_CFG_H_ |
| 20 | |
| 21 | /** |
Martin Roth | 15b6325 | 2014-12-29 22:08:15 -0700 | [diff] [blame] | 22 | * @def BIOS_SIZE |
| 23 | * BIOS_SIZE_{1,2,4,8,16}M |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 24 | * |
| 25 | * In SB800, default ROM size is 1M Bytes, if your platform ROM |
| 26 | * bigger than 1M you have to set the ROM size outside CIMx module and |
| 27 | * before AGESA module get call. |
| 28 | */ |
| 29 | #ifndef BIOS_SIZE |
| 30 | #define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) |
| 31 | #endif /* BIOS_SIZE */ |
| 32 | |
| 33 | /** |
| 34 | * @def SPREAD_SPECTRUM |
| 35 | * @brief |
| 36 | * 0 - Disable Spread Spectrum function |
| 37 | * 1 - Enable Spread Spectrum function |
| 38 | */ |
| 39 | #define SPREAD_SPECTRUM 0 |
| 40 | |
| 41 | /** |
| 42 | * @def SB_HPET_TIMER |
| 43 | * @brief |
| 44 | * 0 - Disable hpet |
| 45 | * 1 - Enable hpet |
| 46 | */ |
| 47 | #define HPET_TIMER 1 |
| 48 | |
| 49 | /** |
| 50 | * @def USB_CONFIG |
| 51 | * @brief bit[0-6] used to control USB |
| 52 | * 0 - Disable |
| 53 | * 1 - Enable |
Kyösti Mälkki | 6533b83 | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 54 | * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 |
| 55 | * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 |
| 56 | * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 |
| 57 | * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 |
| 58 | * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 |
| 59 | * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 |
| 60 | * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 61 | */ |
| 62 | #define USB_CONFIG 0x7F |
| 63 | |
| 64 | /** |
| 65 | * @def PCI_CLOCK_CTRL |
| 66 | * @brief bit[0-4] used for PCI Slots Clock Control, |
| 67 | * 0 - disable |
| 68 | * 1 - enable |
| 69 | * PCI SLOT 0 define at BIT0 |
| 70 | * PCI SLOT 1 define at BIT1 |
| 71 | * PCI SLOT 2 define at BIT2 |
| 72 | * PCI SLOT 3 define at BIT3 |
| 73 | * PCI SLOT 4 define at BIT4 |
| 74 | */ |
| 75 | #define PCI_CLOCK_CTRL 0x07 |
| 76 | |
| 77 | /** |
| 78 | * @def SATA_CONTROLLER |
| 79 | * @brief INCHIP Sata Controller |
| 80 | */ |
| 81 | #define SATA_CONTROLLER CIMX_OPTION_ENABLED |
| 82 | |
| 83 | /** |
| 84 | * @def SATA_MODE |
| 85 | * @brief INCHIP Sata Controller Mode |
| 86 | * NOTE: DO NOT ALLOW SATA & IDE use same mode |
| 87 | */ |
| 88 | #define SATA_MODE CONFIG_SB800_SATA_MODE |
| 89 | |
| 90 | /** |
| 91 | * @brief INCHIP Sata IDE Controller Mode |
| 92 | */ |
| 93 | #define IDE_LEGACY_MODE 0 |
| 94 | #define IDE_NATIVE_MODE 1 |
| 95 | |
| 96 | /** |
| 97 | * @def SATA_IDE_MODE |
| 98 | * @brief INCHIP Sata IDE Controller Mode |
| 99 | * NOTE: DO NOT ALLOW SATA & IDE use same mode |
| 100 | */ |
| 101 | #define SATA_IDE_MODE IDE_LEGACY_MODE |
| 102 | |
| 103 | /** |
| 104 | * @def EXTERNAL_CLOCK |
| 105 | * @brief 00/10: Reference clock from crystal oscillator via |
| 106 | * PAD_XTALI and PAD_XTALO |
| 107 | * |
| 108 | * @def INTERNAL_CLOCK |
| 109 | * @brief 01/11: Reference clock from internal clock through |
| 110 | * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL |
| 111 | */ |
| 112 | #define EXTERNAL_CLOCK 0x00 |
| 113 | #define INTERNAL_CLOCK 0x01 |
| 114 | |
| 115 | /* NOTE: inagua have to using internal clock, |
| 116 | * otherwise can not detect sata drive |
| 117 | */ |
| 118 | #define SATA_CLOCK_SOURCE INTERNAL_CLOCK |
| 119 | |
| 120 | /** |
| 121 | * @def SATA_PORT_MULT_CAP_RESERVED |
| 122 | * @brief 1 ON, 0 0FF |
| 123 | */ |
| 124 | #define SATA_PORT_MULT_CAP_RESERVED 1 |
| 125 | |
| 126 | |
| 127 | /** |
| 128 | * @def AZALIA_AUTO |
| 129 | * @brief Detect Azalia controller automatically. |
| 130 | * |
| 131 | * @def AZALIA_DISABLE |
| 132 | * @brief Disable Azalia controller. |
| 133 | |
| 134 | * @def AZALIA_ENABLE |
| 135 | * @brief Enable Azalia controller. |
| 136 | */ |
| 137 | #define AZALIA_AUTO 0 |
| 138 | #define AZALIA_DISABLE 1 |
| 139 | #define AZALIA_ENABLE 2 |
| 140 | |
| 141 | /** |
| 142 | * @brief INCHIP HDA controller |
| 143 | */ |
| 144 | #define AZALIA_CONTROLLER AZALIA_AUTO |
| 145 | |
| 146 | /** |
| 147 | * @def AZALIA_PIN_CONFIG |
| 148 | * @brief |
| 149 | * 0 - disable |
| 150 | * 1 - enable |
| 151 | */ |
| 152 | #define AZALIA_PIN_CONFIG 1 |
| 153 | |
| 154 | /** |
| 155 | * @def AZALIA_SDIN_PIN |
| 156 | * @brief |
| 157 | * SDIN0 is define at BIT0 & BIT1 |
| 158 | * 00 - GPIO PIN |
| 159 | * 01 - Reserved |
| 160 | * 10 - As a Azalia SDIN pin |
| 161 | * SDIN1 is define at BIT2 & BIT3 |
| 162 | * SDIN2 is define at BIT4 & BIT5 |
| 163 | * SDIN3 is define at BIT6 & BIT7 |
| 164 | */ |
| 165 | //#define AZALIA_SDIN_PIN 0xAA |
| 166 | #define AZALIA_SDIN_PIN 0x2A |
| 167 | |
| 168 | /** |
| 169 | * @def GPP_CONTROLLER |
| 170 | */ |
| 171 | #define GPP_CONTROLLER CIMX_OPTION_ENABLED |
| 172 | |
| 173 | /** |
| 174 | * @def GPP_CFGMODE |
| 175 | * @brief GPP Link Configuration |
| 176 | * four possible configuration: |
| 177 | * GPP_CFGMODE_X4000 |
| 178 | * GPP_CFGMODE_X2200 |
| 179 | * GPP_CFGMODE_X2110 |
| 180 | * GPP_CFGMODE_X1111 |
| 181 | */ |
| 182 | #define GPP_CFGMODE GPP_CFGMODE_X1111 |
| 183 | |
| 184 | /** |
| 185 | * @def NB_SB_GEN2 |
| 186 | * 0 - Disable |
| 187 | * 1 - Enable |
| 188 | */ |
| 189 | #define NB_SB_GEN2 TRUE |
| 190 | |
| 191 | /** |
Martin Roth | 15b6325 | 2014-12-29 22:08:15 -0700 | [diff] [blame] | 192 | * @def SB_GPP_GEN2 |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 193 | * 0 - Disable |
| 194 | * 1 - Enable |
| 195 | */ |
| 196 | #define SB_GPP_GEN2 TRUE |
| 197 | |
| 198 | /** |
| 199 | * @def SB_GPP_UNHIDE_PORTS |
Kyösti Mälkki | efa8a9d | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 200 | * TRUE - ports visible always, even port empty |
| 201 | * FALSE - ports invisible if port empty |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 202 | */ |
| 203 | #define SB_GPP_UNHIDE_PORTS FALSE |
| 204 | |
| 205 | /** |
| 206 | * @def GEC_CONFIG |
| 207 | * 0 - Enable |
| 208 | * 1 - Disable |
| 209 | */ |
| 210 | #define GEC_CONFIG 0 |
| 211 | |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 212 | /* FIXME: Verify this for sound to work! */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 213 | static const CODECENTRY persimmon_codec_alc269[] = |
| 214 | { |
| 215 | /* NID, PinConfig */ |
| 216 | {0x12, 0x411111F0}, |
| 217 | {0x14, 0x99130110}, |
| 218 | {0x21, 0x0121401F}, |
| 219 | {0x17, 0x411111F0}, |
| 220 | {0x18, 0x01A19820}, |
| 221 | {0x19, 0x411111F0}, |
| 222 | {0x1A, 0x0181302F}, |
| 223 | {0x1B, 0x411111F0}, |
| 224 | {0x1D, 0x40069E05}, |
| 225 | {0x1E, 0x411111F0}, |
| 226 | {0x20, 0x0001FFFF}, |
| 227 | {0xff, 0xffffffff} /* end of table */ |
| 228 | }; |
| 229 | |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 230 | /* FIXME: Verify this for sound to work! */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 231 | static const CODECTBLLIST codec_tablelist[] = |
| 232 | { |
| 233 | {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, |
| 234 | {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} |
| 235 | }; |
| 236 | |
| 237 | /** |
| 238 | * @def AZALIA_OEM_VERB_TABLE |
| 239 | * Mainboard specific codec verb table list |
| 240 | */ |
| 241 | #define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) |
| 242 | |
Kyösti Mälkki | 8f87c3f | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 243 | /* set up an ACPI preferred power management profile */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 244 | /* from acpi.h |
| 245 | * PM_UNSPECIFIED = 0, |
| 246 | * PM_DESKTOP = 1, |
| 247 | * PM_MOBILE = 2, |
| 248 | * PM_WORKSTATION = 3, |
| 249 | * PM_ENTERPRISE_SERVER = 4, |
| 250 | * PM_SOHO_SERVER = 5, |
| 251 | * PM_APPLIANCE_PC = 6, |
| 252 | * PM_PERFORMANCE_SERVER = 7, |
| 253 | * PM_TABLET = 8 |
| 254 | */ |
| 255 | #define FADT_PM_PROFILE 1 |
| 256 | |
| 257 | #endif /* _PLATFORM_CFG_H_ */ |