Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 6 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 19 | #include <arch/io.h> |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 20 | #include <arch/ioapic.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 21 | #include <arch/smp/mpspec.h> |
| 22 | #include <console/console.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 23 | #include <cpu/amd/amdfam14.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 24 | #include <device/pci.h> |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 25 | #include <drivers/generic/ioapic/chip.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 26 | #include <stdint.h> |
| 27 | #include <string.h> |
| 28 | |
Stefan Reinauer | 13e4182 | 2015-04-27 14:02:36 -0700 | [diff] [blame] | 29 | #include <southbridge/amd/common/amd_pci_util.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 30 | #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 31 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 32 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 33 | static void *smp_write_config_table(void *v) |
| 34 | { |
| 35 | struct mp_config_table *mc; |
| 36 | int bus_isa; |
| 37 | |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 38 | /* |
| 39 | * By the time this function gets called, the IOAPIC registers |
| 40 | * have been written so they can be read to get the correct |
| 41 | * APIC ID and Version |
| 42 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 43 | u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); |
| 44 | u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 45 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 46 | /* Intialize the MP_Table */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 47 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 48 | |
| 49 | mptable_init(mc, LOCAL_APIC_ADDR); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 50 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 51 | /* |
| 52 | * Type 0: Processor Entries: |
| 53 | * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, |
| 54 | * CPU Signature (Stepping, Model, Family), |
| 55 | * Feature Flags |
| 56 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 57 | smp_write_processors(mc); |
| 58 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 59 | /* |
| 60 | * Type 1: Bus Entries: |
| 61 | * Bus ID, Bus Type |
| 62 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 63 | mptable_write_buses(mc, NULL, &bus_isa); |
| 64 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 65 | /* |
| 66 | * Type 2: I/O APICs: |
| 67 | * APIC ID, Version, APIC Flags:EN, Address |
| 68 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 69 | smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 70 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 71 | /* |
| 72 | * Type 3: I/O Interrupt Table Entries: |
| 73 | * Int Type, Int Polarity, Int Level, Source Bus ID, |
| 74 | * Source Bus IRQ, Dest APIC ID, Dest PIN# |
| 75 | */ |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 76 | mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 77 | |
| 78 | /* PCI interrupts are level triggered, and are |
| 79 | * associated with a specific bus/device/function tuple. |
| 80 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 81 | #define PCI_INT(bus, dev, fn, pin) \ |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 82 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 83 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 84 | /* APU Internal Graphic Device */ |
| 85 | PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); |
| 86 | PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 87 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 88 | /* SMBUS / ACPI */ |
| 89 | PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 90 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 91 | /* Southbridge HD Audio */ |
| 92 | PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); |
| 93 | |
| 94 | /* LPC */ |
| 95 | PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); |
| 96 | |
| 97 | /* USB */ |
| 98 | PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); |
| 99 | PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); |
| 100 | PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); |
| 101 | PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); |
| 102 | PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]); |
| 103 | |
| 104 | /* IDE */ |
| 105 | PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 106 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 107 | /* SATA */ |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 108 | PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 109 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 110 | /* On-board NIC & Slot PCIE. */ |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 111 | PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ |
| 112 | PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 113 | |
| 114 | /* PCI slots */ |
Kyösti Mälkki | cdfb462 | 2014-07-22 15:24:15 +0300 | [diff] [blame] | 115 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); |
| 116 | if (dev && dev->enabled) { |
| 117 | u8 bus_pci = dev->link_list->secondary; |
| 118 | /* PCI_SLOT 0 */ |
| 119 | PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ |
| 120 | PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ |
| 121 | PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ |
| 122 | PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ |
| 123 | } |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 124 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 125 | /* On-board Realtek NIC 2. (PCIe PortA) */ |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 126 | PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 127 | /* PCIe PortB */ |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 128 | PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 129 | /* PCIe PortC */ |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 130 | PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 131 | /* PCIe PortD */ |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 132 | PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 133 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 134 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 135 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 136 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 137 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 138 | IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); |
| 139 | IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); |
| 140 | /* There is no extension information... */ |
| 141 | |
| 142 | /* Compute the checksums */ |
| 143 | return mptable_finalize(mc); |
| 144 | } |
| 145 | |
| 146 | unsigned long write_smp_table(unsigned long addr) |
| 147 | { |
| 148 | void *v; |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 149 | v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 150 | return (unsigned long)smp_write_config_table(v); |
| 151 | } |