Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 6 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 16 | */ |
| 17 | |
Kyösti Mälkki | 26f297e | 2014-05-26 11:27:54 +0300 | [diff] [blame] | 18 | #include <northbridge/amd/agesa/BiosCallOuts.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 19 | |
| 20 | #include <arch/acpi.h> |
| 21 | #include <arch/io.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 22 | #include <console/console.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 23 | #include <cpu/x86/msr.h> |
| 24 | #include <cpu/amd/agesa/s3_resume.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 27 | #include <device/pci_def.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 28 | |
Stefan Reinauer | 13e4182 | 2015-04-27 14:02:36 -0700 | [diff] [blame] | 29 | #include <southbridge/amd/common/amd_pci_util.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 30 | #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 31 | #include <southbridge/amd/cimx/sb800/pci_devs.h> |
| 32 | #include <southbridge/amd/cimx/cimx_util.h> |
| 33 | #include <northbridge/amd/agesa/family14/pci_devs.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 34 | |
| 35 | void set_pcie_reset(void); |
| 36 | void set_pcie_dereset(void); |
| 37 | |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 38 | /*********************************************************** |
| 39 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 40 | * This table is responsible for physically routing the PIC and |
| 41 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 42 | * is read and written via registers 0xC00/0xC01 as an |
| 43 | * Index/Data pair. These values are chipset and mainboard |
| 44 | * dependent and should be updated accordingly. |
| 45 | * |
| 46 | * These values are used by the PCI configuration space, |
| 47 | * MP Tables. TODO: Make ACPI use these values too. |
| 48 | * |
| 49 | * The Persimmon PCI INTA/B/C/D pins are connected to |
| 50 | * FCH pins INTE/F/G/H on the schematic so these need |
| 51 | * to be routed as well. |
| 52 | */ |
| 53 | static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { |
| 54 | /* INTA# - INTH# */ |
| 55 | [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, |
| 56 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 57 | [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 58 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ |
| 59 | [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, |
| 60 | /* IMC INT0 - 5 */ |
| 61 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 62 | /* USB Devs 18/19/20/22 INTA-C */ |
| 63 | [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, |
| 64 | /* IDE, SATA */ |
| 65 | [0x40] = 0x0B,0x0B, |
| 66 | /* GPPInt0 - 3 */ |
| 67 | [0x50] = 0x0A,0x0B,0x0A,0x0B |
| 68 | }; |
| 69 | |
| 70 | static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { |
| 71 | /* INTA# - INTH# */ |
| 72 | [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, |
| 73 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 74 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 75 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */ |
| 76 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F, |
| 77 | /* IMC INT0 - 5 */ |
| 78 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 79 | /* USB Devs 18/19/22/20 INTA-C */ |
| 80 | [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, |
| 81 | /* IDE, SATA */ |
| 82 | [0x40] = 0x11,0x13, |
| 83 | /* GPPInt0 - 3 */ |
| 84 | [0x50] = 0x10,0x11,0x12,0x13 |
| 85 | }; |
| 86 | |
| 87 | /* |
| 88 | * This table defines the index into the picr/intr_data |
| 89 | * tables for each device. Any enabled device and slot |
| 90 | * that uses hardware interrupts should have an entry |
| 91 | * in this table to define its index into the FCH |
| 92 | * PCI_INTR register 0xC00/0xC01. This index will define |
| 93 | * the interrupt that it should use. Putting PIRQ_A into |
| 94 | * the PIN A index for a device will tell that device to |
| 95 | * use PIC IRQ 10 if it uses PIN A for its hardware INT. |
| 96 | */ |
| 97 | /* |
| 98 | * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H |
| 99 | * but because PCI INT_PIN swizzling isnt implemented to match |
| 100 | * the IDSEL (dev 3) of the slot, the table is adjusted for the |
| 101 | * swizzle and INTA is connected to PIRQH so PINA/B/C/D on |
| 102 | * off-chip devices should get mapped to PIRQH/E/F/G. |
| 103 | */ |
| 104 | static const struct pirq_struct mainboard_pirq_data[] = { |
Kyösti Mälkki | faaa253 | 2014-06-26 07:11:22 +0300 | [diff] [blame] | 105 | /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ |
| 106 | {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ |
| 107 | {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ |
| 108 | {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ |
| 109 | {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ |
| 110 | {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ |
| 111 | {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ |
| 112 | {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ |
| 113 | {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ |
| 114 | {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ |
| 115 | {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ |
| 116 | {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ |
| 117 | {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ |
| 118 | {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ |
| 119 | {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ |
| 120 | {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 121 | }; |
| 122 | |
| 123 | /* PIRQ Setup */ |
| 124 | static void pirq_setup(void) |
| 125 | { |
| 126 | pirq_data_ptr = mainboard_pirq_data; |
| 127 | pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); |
| 128 | intr_data_ptr = mainboard_intr_data; |
| 129 | picr_data_ptr = mainboard_picr_data; |
| 130 | } |
| 131 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 132 | /** |
| 133 | * TODO |
| 134 | * SB CIMx callback |
| 135 | */ |
| 136 | void set_pcie_reset(void) |
| 137 | { |
| 138 | } |
| 139 | |
| 140 | /** |
| 141 | * TODO |
| 142 | * mainboard specific SB CIMx callback |
| 143 | */ |
| 144 | void set_pcie_dereset(void) |
| 145 | { |
| 146 | } |
| 147 | |
| 148 | |
| 149 | /********************************************** |
| 150 | * Enable the dedicated functions of the board. |
| 151 | **********************************************/ |
| 152 | static void mainboard_enable(device_t dev) |
| 153 | { |
| 154 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 155 | |
Edward O'Callaghan | bfa29dc | 2014-03-09 17:46:39 +1100 | [diff] [blame] | 156 | /* enable GPP CLK0 thru CLK3 (interleaved) */ |
| 157 | /* disable GPP CLK4 thru SLT_GFX_CLK */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 158 | u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); |
Felix Held | 421b47e | 2015-10-17 13:16:27 +0200 | [diff] [blame] | 159 | write8(misc_mem_clk_cntrl + 0, 0xFF); |
| 160 | write8(misc_mem_clk_cntrl + 1, 0xFF); |
| 161 | write8(misc_mem_clk_cntrl + 2, 0x00); |
| 162 | write8(misc_mem_clk_cntrl + 3, 0x00); |
| 163 | write8(misc_mem_clk_cntrl + 4, 0x00); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 164 | |
| 165 | /* |
| 166 | * Initialize ASF registers to an arbitrary address because someone |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 167 | * long ago set things up this way inside the SPD read code. The |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 168 | * SPD read code has been made generic and moved out of the board |
| 169 | * directory, so the ASF init is being done here. |
| 170 | */ |
| 171 | pm_iowrite(0x29, 0x80); |
| 172 | pm_iowrite(0x28, 0x61); |
Edward O'Callaghan | d309eb1 | 2014-05-30 11:35:33 +1000 | [diff] [blame] | 173 | |
| 174 | /* Initialize the PIRQ data structures for consumption */ |
| 175 | pirq_setup(); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | struct chip_operations mainboard_ops = { |
| 179 | .enable_dev = mainboard_enable, |
| 180 | }; |