Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /** |
| 17 | * @file |
| 18 | * |
| 19 | * AMD User options selection for a Brazos platform solution system |
| 20 | * |
| 21 | * This file is placed in the user's platform directory and contains the |
| 22 | * build option selections desired for that platform. |
| 23 | * |
| 24 | * For Information about this file, see @ref platforminstall. |
| 25 | * |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 26 | */ |
| 27 | |
Edward O'Callaghan | d5339ae | 2014-07-07 19:58:53 +1000 | [diff] [blame] | 28 | #include <stdlib.h> |
| 29 | |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 30 | #include <vendorcode/amd/agesa/f14/AGESA.h> |
| 31 | |
| 32 | /* Include the files that instantiate the configuration definitions. */ |
| 33 | #include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> |
| 34 | #include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> |
| 35 | #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> |
| 36 | #include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> |
| 37 | #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> |
| 38 | /* AGESA nonesense: the next two headers depend on heapManager.h */ |
| 39 | #include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h> |
| 40 | #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h> |
| 41 | /* These tables are optional and may be used to adjust memory timing settings */ |
| 42 | #include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> |
| 43 | #include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> |
| 44 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 45 | #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE |
| 46 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 47 | /* Select the cpu family. */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 48 | #define INSTALL_FAMILY_10_SUPPORT FALSE |
| 49 | #define INSTALL_FAMILY_12_SUPPORT FALSE |
| 50 | #define INSTALL_FAMILY_14_SUPPORT TRUE |
| 51 | #define INSTALL_FAMILY_15_SUPPORT FALSE |
| 52 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 53 | /* Select the cpu socket type. */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 54 | #define INSTALL_G34_SOCKET_SUPPORT FALSE |
| 55 | #define INSTALL_C32_SOCKET_SUPPORT FALSE |
| 56 | #define INSTALL_S1G3_SOCKET_SUPPORT FALSE |
| 57 | #define INSTALL_S1G4_SOCKET_SUPPORT FALSE |
| 58 | #define INSTALL_ASB2_SOCKET_SUPPORT FALSE |
| 59 | #define INSTALL_FS1_SOCKET_SUPPORT FALSE |
| 60 | #define INSTALL_FM1_SOCKET_SUPPORT FALSE |
| 61 | #define INSTALL_FP1_SOCKET_SUPPORT FALSE |
| 62 | #define INSTALL_FT1_SOCKET_SUPPORT TRUE |
| 63 | #define INSTALL_AM3_SOCKET_SUPPORT FALSE |
| 64 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 65 | /** |
| 66 | * AGESA optional capabilities selection. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 67 | * Uncomment and mark FALSE those features you wish to include in the build. |
| 68 | * Comment out or mark TRUE those features you want to REMOVE from the build. |
| 69 | */ |
| 70 | |
| 71 | #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE |
| 72 | #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE |
| 73 | #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE |
| 74 | #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE |
| 75 | |
| 76 | #define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE |
| 77 | #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE |
| 78 | #define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE |
| 79 | #define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE |
| 80 | #define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE |
| 81 | #define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE |
| 82 | #define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE |
| 83 | #define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE |
| 84 | #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE |
| 85 | #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE |
| 86 | |
| 87 | #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE |
| 88 | #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE |
| 89 | #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE |
| 90 | #define BLDOPT_REMOVE_ECC_SUPPORT FALSE |
| 91 | //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE |
| 92 | #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE |
| 93 | #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE |
| 94 | #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE |
| 95 | #define BLDOPT_REMOVE_DQS_TRAINING FALSE |
| 96 | #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE |
| 97 | #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 98 | #define BLDOPT_REMOVE_ACPI_PSTATES FALSE |
| 99 | #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE |
| 100 | #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE |
| 101 | #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE |
| 102 | #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE |
| 103 | #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE |
| 104 | #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 105 | #define BLDOPT_REMOVE_SRAT FALSE |
| 106 | #define BLDOPT_REMOVE_SLIT FALSE |
| 107 | #define BLDOPT_REMOVE_WHEA FALSE |
| 108 | #define BLDOPT_REMOVE_DMI TRUE |
| 109 | #define BLDOPT_REMOVE_HT_ASSIST TRUE |
| 110 | #define BLDOPT_REMOVE_ATM_MODE TRUE |
| 111 | //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE |
| 112 | //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE |
| 113 | #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE |
| 114 | //#define BLDOPT_REMOVE_C6_STATE TRUE |
| 115 | #define BLDOPT_REMOVE_GFX_RECOVERY TRUE |
| 116 | #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE |
| 117 | |
| 118 | /* |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 119 | * AGESA entry points used in this implementation. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 120 | */ |
| 121 | #define AGESA_ENTRY_INIT_RESET TRUE |
| 122 | #define AGESA_ENTRY_INIT_RECOVERY FALSE |
| 123 | #define AGESA_ENTRY_INIT_EARLY TRUE |
| 124 | #define AGESA_ENTRY_INIT_POST TRUE |
| 125 | #define AGESA_ENTRY_INIT_ENV TRUE |
| 126 | #define AGESA_ENTRY_INIT_MID TRUE |
| 127 | #define AGESA_ENTRY_INIT_LATE TRUE |
| 128 | #define AGESA_ENTRY_INIT_S3SAVE TRUE |
| 129 | #define AGESA_ENTRY_INIT_RESUME TRUE |
| 130 | #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE |
| 131 | #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE |
| 132 | |
| 133 | #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS |
| 134 | #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER |
| 135 | |
| 136 | #define BLDCFG_VRM_CURRENT_LIMIT 24000 |
| 137 | //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 |
| 138 | #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 |
| 139 | #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 |
| 140 | #define BLDCFG_VRM_SLEW_RATE 5000 |
| 141 | //#define BLDCFG_VRM_NB_SLEW_RATE 5000 |
| 142 | //#define BLDCFG_VRM_ADDITIONAL_DELAY 0 |
| 143 | //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 |
| 144 | #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE |
| 145 | //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE |
| 146 | #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 |
| 147 | //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 |
| 148 | |
| 149 | //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' |
| 150 | //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' |
| 151 | //#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE |
| 152 | #define BLDCFG_PLAT_NUM_IO_APICS 3 |
| 153 | //#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled |
| 154 | //#define BLDCFG_PLATFORM_C1E_OPDATA 0 |
| 155 | //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 |
| 156 | //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 |
| 157 | #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 |
| 158 | #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 |
| 159 | #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 |
| 160 | //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto |
| 161 | #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST |
| 162 | #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList |
| 163 | #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE |
| 164 | //#define BLDCFG_STARTING_BUSNUM 0 |
| 165 | //#define BLDCFG_MAXIMUM_BUSNUM 0xf8 |
| 166 | //#define BLDCFG_ALLOCATED_BUSNUMS 0x20 |
| 167 | //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 |
| 168 | //#define BLDCFG_BUID_SWAP_LIST 0 |
| 169 | //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 |
| 170 | //#define BLDCFG_HTFABRIC_LIMITS_LIST 0 |
| 171 | //#define BLDCFG_HTCHAIN_LIMITS_LIST 0 |
| 172 | //#define BLDCFG_BUS_NUMBERS_LIST 0 |
| 173 | //#define BLDCFG_IGNORE_LINK_LIST 0 |
| 174 | //#define BLDCFG_LINK_SKIP_REGANG_LIST 0 |
| 175 | //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 |
| 176 | //#define BLDCFG_USE_HT_ASSIST TRUE |
| 177 | //#define BLDCFG_USE_ATM_MODE TRUE |
| 178 | //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm |
| 179 | #define BLDCFG_S3_LATE_RESTORE TRUE |
| 180 | //#define BLDCFG_USE_32_BYTE_REFRESH FALSE |
| 181 | //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE |
| 182 | //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance |
| 183 | //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE |
| 184 | //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE |
| 185 | //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 |
| 186 | #define BLDCFG_CFG_GNB_HD_AUDIO FALSE |
| 187 | //#define BLDCFG_CFG_ABM_SUPPORT FALSE |
| 188 | //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 |
| 189 | //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 |
| 190 | //#define BLDCFG_MEM_INIT_PSTATE 0 |
| 191 | //#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 |
| 192 | #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY |
| 193 | #define BLDCFG_MEMORY_MODE_UNGANGED TRUE |
| 194 | //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE |
| 195 | //#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 196 | #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE |
| 197 | #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE |
| 198 | #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE |
| 199 | #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE |
| 200 | #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE |
| 201 | #define BLDCFG_MEMORY_POWER_DOWN TRUE |
| 202 | #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT |
| 203 | //#define BLDCFG_ONLINE_SPARE FALSE |
| 204 | //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE |
| 205 | #define BLDCFG_BANK_SWIZZLE TRUE |
| 206 | #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO |
| 207 | #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY |
| 208 | #define BLDCFG_DQS_TRAINING_CONTROL TRUE |
| 209 | #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE |
| 210 | #define BLDCFG_USE_BURST_MODE FALSE |
| 211 | #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE |
| 212 | //#define BLDCFG_ENABLE_ECC_FEATURE TRUE |
| 213 | //#define BLDCFG_ECC_REDIRECTION FALSE |
| 214 | //#define BLDCFG_SCRUB_DRAM_RATE 0 |
| 215 | //#define BLDCFG_SCRUB_L2_RATE 0 |
| 216 | //#define BLDCFG_SCRUB_L3_RATE 0 |
| 217 | //#define BLDCFG_SCRUB_IC_RATE 0 |
| 218 | //#define BLDCFG_SCRUB_DC_RATE 0 |
| 219 | //#define BLDCFG_ECC_SYNC_FLOOD 0 |
| 220 | //#define BLDCFG_ECC_SYMBOL_SIZE 0 |
| 221 | //#define BLDCFG_1GB_ALIGN FALSE |
| 222 | #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO |
| 223 | #define BLDCFG_UMA_ALLOCATION_SIZE 0 |
| 224 | #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE |
| 225 | #define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED |
| 226 | #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 |
| 227 | #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 |
| 228 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 229 | /** |
| 230 | * AGESA configuration values selection. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 231 | * Uncomment and specify the value for the configuration options |
| 232 | * needed by the system. |
| 233 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 234 | |
| 235 | /* The fixed MTRR values to be set after memory initialization. */ |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 236 | const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 237 | { |
| 238 | { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, |
| 239 | { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, |
| 240 | { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, |
| 241 | { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, |
| 242 | { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, |
| 243 | { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, |
| 244 | { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, |
| 245 | { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, |
| 246 | { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, |
| 247 | { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, |
| 248 | { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, |
| 249 | { CPU_LIST_TERMINAL } |
| 250 | }; |
| 251 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 252 | /** |
| 253 | * @brief Define the RELEASE VERSION string |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 254 | * |
| 255 | * The Release Version string should identify the next planned release. |
| 256 | * When a branch is made in preparation for a release, the release manager |
| 257 | * should change/confirm that the branch version of this file contains the |
| 258 | * string matching the desired version for the release. The trunk version of |
| 259 | * the file should always contain a trailing 'X'. This will make sure that a |
| 260 | * development build from trunk will not be confused for a released version. |
| 261 | * The release manager will need to remove the trailing 'X' and update the |
| 262 | * version string as appropriate for the release. The trunk copy of this file |
| 263 | * should also be updated/incremented for the next expected version, + trailing 'X' |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 264 | */ |
| 265 | |
| 266 | /* |
| 267 | * This is the delivery package title, "BrazosPI" |
| 268 | * This string MUST be exactly 8 characters long |
| 269 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 270 | #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} |
| 271 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 272 | /* This is the release version number of the AGESA component |
| 273 | * This string MUST be exactly 12 characters long |
| 274 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 275 | #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} |
| 276 | |
| 277 | /* MEMORY_BUS_SPEED */ |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 278 | #define DDR400_FREQUENCY 200 /**< DDR 400 */ |
| 279 | #define DDR533_FREQUENCY 266 /**< DDR 533 */ |
| 280 | #define DDR667_FREQUENCY 333 /**< DDR 667 */ |
| 281 | #define DDR800_FREQUENCY 400 /**< DDR 800 */ |
| 282 | #define DDR1066_FREQUENCY 533 /**< DDR 1066 */ |
| 283 | #define DDR1333_FREQUENCY 667 /**< DDR 1333 */ |
| 284 | #define DDR1600_FREQUENCY 800 /**< DDR 1600 */ |
| 285 | #define DDR1866_FREQUENCY 933 /**< DDR 1866 */ |
| 286 | #define UNSUPPORTED_DDR_FREQUENCY 934 /**< Max limit of DDR frequency */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 287 | |
| 288 | /* QUANDRANK_TYPE*/ |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 289 | #define QUADRANK_REGISTERED 0 /**< Quadrank registered DIMM */ |
| 290 | #define QUADRANK_UNBUFFERED 1 /**< Quadrank unbuffered DIMM */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 291 | |
| 292 | /* USER_MEMORY_TIMING_MODE */ |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 293 | #define TIMING_MODE_AUTO 0 /**< Use best rate possible */ |
| 294 | #define TIMING_MODE_LIMITED 1 /**< Set user top limit */ |
| 295 | #define TIMING_MODE_SPECIFIC 2 /**< Set user specified speed */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 296 | |
| 297 | /* POWER_DOWN_MODE */ |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 298 | #define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */ |
| 299 | #define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 300 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 301 | /** |
| 302 | * The following definitions specify the default values for various parameters |
| 303 | * in which there are no clearly defined defaults to be used in the common |
| 304 | * file. The values below are based on product and BKDG content. |
| 305 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 306 | #define DFLT_SCRUB_DRAM_RATE (0) |
| 307 | #define DFLT_SCRUB_L2_RATE (0) |
| 308 | #define DFLT_SCRUB_L3_RATE (0) |
| 309 | #define DFLT_SCRUB_IC_RATE (0) |
| 310 | #define DFLT_SCRUB_DC_RATE (0) |
| 311 | #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 312 | #define DFLT_VRM_SLEW_RATE (5000) |
| 313 | |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 314 | /* AGESA nonsense: this header depends on the definitions above */ |
| 315 | /* Instantiate all solution relevant data. */ |
| 316 | #include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 317 | |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 318 | /** |
| 319 | * @brief Customer Overides Memory Table |
| 320 | * |
| 321 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform |
| 322 | * information to AGESA |
| 323 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). |
| 324 | * If PlatformSpecificTable is populated, AGESA will base its settings on the |
| 325 | * data from the table. Otherwise, it will use its default conservative settings. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 326 | */ |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 327 | const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 328 | NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), |
| 329 | NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), |
| 330 | PSO_END |
| 331 | }; |