blob: 038ad8b0ecd63df7d4be8ec942f40f49a6a49d29 [file] [log] [blame]
Edward O'Callaghan4726a872014-01-25 07:40:39 +11001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Edward O'Callaghan4726a872014-01-25 07:40:39 +110014 */
15
Kyösti Mälkki526c2fb2014-07-10 22:16:58 +030016#include "AGESA.h"
Kyösti Mälkki26f297e2014-05-26 11:27:54 +030017#include <northbridge/amd/agesa/BiosCallOuts.h>
Edward O'Callaghan5ff4b082014-03-29 17:54:26 +110018
19#include <Lib/amdlib.h>
Edward O'Callaghan5ff4b082014-03-29 17:54:26 +110020#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
21#include <vendorcode/amd/cimx/sb800/SB800.h>
Edward O'Callaghanc21bd882014-04-12 04:12:14 +100022#include <stdint.h>
Kyösti Mälkki6025efa2014-05-05 13:20:56 +030023#include <stdlib.h>
Edward O'Callaghan4726a872014-01-25 07:40:39 +110024
Stefan Reinauerdd132a52015-07-30 11:16:37 -070025static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
26static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
Kyösti Mälkkic0096012014-05-05 18:56:33 +030027
Kyösti Mälkki6025efa2014-05-05 13:20:56 +030028const BIOS_CALLOUT_STRUCT BiosCallouts[] =
Edward O'Callaghan4726a872014-01-25 07:40:39 +110029{
Kyösti Mälkki5e19fa42014-05-04 23:13:54 +030030 {AGESA_DO_RESET, agesa_Reset },
Kyösti Mälkkia1ebbc42014-10-17 22:33:22 +030031 {AGESA_READ_SPD, agesa_ReadSpd },
Kyösti Mälkkic459f962014-05-04 17:07:45 +030032 {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
Kyösti Mälkki6b4b1512014-05-05 12:05:53 +030033 {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
Kyösti Mälkkic0096012014-05-05 18:56:33 +030034 {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },
35 {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
Kyösti Mälkkic459f962014-05-04 17:07:45 +030036 {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
37 {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
38 {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
Edward O'Callaghan4726a872014-01-25 07:40:39 +110039};
Kyösti Mälkki6025efa2014-05-05 13:20:56 +030040const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
Edward O'Callaghan4726a872014-01-25 07:40:39 +110041
Edward O'Callaghanc21bd882014-04-12 04:12:14 +100042/* Call the host environment interface to provide a user hook opportunity. */
Stefan Reinauerdd132a52015-07-30 11:16:37 -070043static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
Edward O'Callaghan4726a872014-01-25 07:40:39 +110044{
Edward O'Callaghanfeebd862014-04-10 19:12:28 +100045 /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
46 * Make sure the right speed settings are selected.
47 */
Edward O'Callaghan4726a872014-01-25 07:40:39 +110048 ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
49 return AGESA_SUCCESS;
50}
51
Edward O'Callaghan4726a872014-01-25 07:40:39 +110052/* PCIE slot reset control */
Stefan Reinauerdd132a52015-07-30 11:16:37 -070053static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
Edward O'Callaghan4726a872014-01-25 07:40:39 +110054{
55 AGESA_STATUS Status;
Edward O'Callaghanc21bd882014-04-12 04:12:14 +100056 uint32_t FcnData;
Edward O'Callaghan4726a872014-01-25 07:40:39 +110057 PCIe_SLOT_RESET_INFO *ResetInfo;
58
Edward O'Callaghanc21bd882014-04-12 04:12:14 +100059 uint32_t GpioMmioAddr;
60 uint32_t AcpiMmioAddr;
61 uint8_t Data8;
62 uint16_t Data16;
Edward O'Callaghan4726a872014-01-25 07:40:39 +110063
64 FcnData = Data;
65 ResetInfo = ConfigPtr;
Edward O'Callaghanfeebd862014-04-10 19:12:28 +100066 /* Get SB800 MMIO Base (AcpiMmioAddr) */
Edward O'Callaghan4726a872014-01-25 07:40:39 +110067 WriteIo8(0xCD6, 0x27);
68 Data8 = ReadIo8(0xCD7);
69 Data16=Data8<<8;
70 WriteIo8(0xCD6, 0x26);
71 Data8 = ReadIo8(0xCD7);
72 Data16|=Data8;
Edward O'Callaghanc21bd882014-04-12 04:12:14 +100073 AcpiMmioAddr = (uint32_t)Data16 << 16;
Edward O'Callaghan4726a872014-01-25 07:40:39 +110074 Status = AGESA_UNSUPPORTED;
75 GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
76 switch (ResetInfo->ResetId)
77 {
Edward O'Callaghanfeebd862014-04-10 19:12:28 +100078 case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */
Edward O'Callaghan4726a872014-01-25 07:40:39 +110079 switch (ResetInfo->ResetControl) {
80 case AssertSlotReset:
81 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
Edward O'Callaghanc21bd882014-04-12 04:12:14 +100082 Data8 &= ~(uint8_t)BIT6 ;
Edward O'Callaghan4726a872014-01-25 07:40:39 +110083 Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
84 Status = AGESA_SUCCESS;
85 break;
86 case DeassertSlotReset:
87 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
88 Data8 |= BIT6 ;
89 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
90 Status = AGESA_SUCCESS;
91 break;
92 }
93 break;
94 }
95 return Status;
96}