Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 14 | */ |
| 15 | |
Kyösti Mälkki | 526c2fb | 2014-07-10 22:16:58 +0300 | [diff] [blame] | 16 | #include "AGESA.h" |
Kyösti Mälkki | 26f297e | 2014-05-26 11:27:54 +0300 | [diff] [blame] | 17 | #include <northbridge/amd/agesa/BiosCallOuts.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 18 | |
| 19 | #include <Lib/amdlib.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 20 | #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> |
| 21 | #include <vendorcode/amd/cimx/sb800/SB800.h> |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 22 | #include <stdint.h> |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 23 | #include <stdlib.h> |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 24 | |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 25 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); |
| 26 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 27 | |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 28 | const BIOS_CALLOUT_STRUCT BiosCallouts[] = |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 29 | { |
Kyösti Mälkki | 5e19fa4 | 2014-05-04 23:13:54 +0300 | [diff] [blame] | 30 | {AGESA_DO_RESET, agesa_Reset }, |
Kyösti Mälkki | a1ebbc4 | 2014-10-17 22:33:22 +0300 | [diff] [blame] | 31 | {AGESA_READ_SPD, agesa_ReadSpd }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 32 | {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, |
Kyösti Mälkki | 6b4b151 | 2014-05-05 12:05:53 +0300 | [diff] [blame] | 33 | {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 34 | {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, |
| 35 | {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 36 | {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, |
| 37 | {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, |
| 38 | {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 39 | }; |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 40 | const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 41 | |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 42 | /* Call the host environment interface to provide a user hook opportunity. */ |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 43 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 44 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 45 | /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. |
| 46 | * Make sure the right speed settings are selected. |
| 47 | */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 48 | ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; |
| 49 | return AGESA_SUCCESS; |
| 50 | } |
| 51 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 52 | /* PCIE slot reset control */ |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 53 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 54 | { |
| 55 | AGESA_STATUS Status; |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 56 | uint32_t FcnData; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 57 | PCIe_SLOT_RESET_INFO *ResetInfo; |
| 58 | |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 59 | uint32_t GpioMmioAddr; |
| 60 | uint32_t AcpiMmioAddr; |
| 61 | uint8_t Data8; |
| 62 | uint16_t Data16; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 63 | |
| 64 | FcnData = Data; |
| 65 | ResetInfo = ConfigPtr; |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 66 | /* Get SB800 MMIO Base (AcpiMmioAddr) */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 67 | WriteIo8(0xCD6, 0x27); |
| 68 | Data8 = ReadIo8(0xCD7); |
| 69 | Data16=Data8<<8; |
| 70 | WriteIo8(0xCD6, 0x26); |
| 71 | Data8 = ReadIo8(0xCD7); |
| 72 | Data16|=Data8; |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 73 | AcpiMmioAddr = (uint32_t)Data16 << 16; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 74 | Status = AGESA_UNSUPPORTED; |
| 75 | GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; |
| 76 | switch (ResetInfo->ResetId) |
| 77 | { |
Edward O'Callaghan | feebd86 | 2014-04-10 19:12:28 +1000 | [diff] [blame] | 78 | case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 79 | switch (ResetInfo->ResetControl) { |
| 80 | case AssertSlotReset: |
| 81 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); |
Edward O'Callaghan | c21bd88 | 2014-04-12 04:12:14 +1000 | [diff] [blame] | 82 | Data8 &= ~(uint8_t)BIT6 ; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 83 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); |
| 84 | Status = AGESA_SUCCESS; |
| 85 | break; |
| 86 | case DeassertSlotReset: |
| 87 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); |
| 88 | Data8 |= BIT6 ; |
| 89 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); |
| 90 | Status = AGESA_SUCCESS; |
| 91 | break; |
| 92 | } |
| 93 | break; |
| 94 | } |
| 95 | return Status; |
| 96 | } |