Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 1 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 2 | #include <string.h> |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 3 | #include <device/pci_def.h> |
| 4 | #include <device/pci_ids.h> |
| 5 | #include <arch/io.h> |
| 6 | #include <device/pnp_def.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 7 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 8 | #include <console/console.h> |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 9 | #include <cpu/amd/model_fxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 10 | #include "southbridge/amd/amd8111/early_smbus.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 11 | #include <northbridge/amd/amdk8/raminit.h> |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 12 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 13 | #include <cpu/x86/bist.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 14 | #include <delay.h> |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 15 | #include "northbridge/amd/amdk8/debug.c" |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 16 | #include <superio/winbond/common/winbond.h> |
| 17 | #include <superio/winbond/w83627hf/w83627hf.h> |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 18 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 19 | #include "southbridge/amd/amd8111/early_ctrl.c" |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 20 | |
| 21 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 22 | |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 23 | /* |
| 24 | * GPIO28 of 8111 will control H0_MEMRESET_L |
| 25 | * GPIO29 of 8111 will control H1_MEMRESET_L |
| 26 | */ |
| 27 | static void memreset_setup(void) |
| 28 | { |
| 29 | if (is_cpu_pre_c0()) { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 30 | /* Set the memreset low. */ |
| 31 | outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); |
| 32 | /* Ensure the BIOS has control of the memory lines. */ |
| 33 | outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 34 | } else { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 35 | /* Ensure the CPU has control of the memory lines. */ |
| 36 | outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 37 | } |
| 38 | } |
| 39 | |
| 40 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 41 | { |
| 42 | if (is_cpu_pre_c0()) { |
| 43 | udelay(800); |
| 44 | /* Set memreset_high */ |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 45 | outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 46 | udelay(90); |
| 47 | } |
| 48 | } |
| 49 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 50 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 51 | |
| 52 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 53 | { |
| 54 | return smbus_read_byte(device, address); |
| 55 | } |
| 56 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 57 | #include <northbridge/amd/amdk8/amdk8.h> |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 58 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 59 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 60 | #include "northbridge/amd/amdk8/raminit.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 61 | #include "lib/generic_sdram.c" |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 62 | #include "resourcemap.c" |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 63 | #include "cpu/amd/dualcore/dualcore.c" |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 64 | #include <spd.h> |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 65 | #include "cpu/amd/model_fxx/init_cpus.c" |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 66 | #include "cpu/amd/model_fxx/fidvid.c" |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 67 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 68 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 69 | { |
| 70 | static const uint16_t spd_addr[] = { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 71 | // first node |
| 72 | DIMM0, DIMM2, 0, 0, |
| 73 | DIMM1, DIMM3, 0, 0, |
| 74 | // second node |
| 75 | DIMM4, DIMM6, 0, 0, |
| 76 | DIMM5, DIMM7, 0, 0, |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 77 | }; |
| 78 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 79 | struct sys_info *sysinfo = &sysinfo_car; |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 80 | int needs_reset; |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 81 | unsigned bsp_apicid = 0; |
| 82 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 83 | if (bist == 0) |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 84 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 85 | |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 86 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 87 | console_init(); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 88 | |
| 89 | /* Halt if there was a built in self test failure */ |
| 90 | report_bist_failure(bist); |
| 91 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 92 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 93 | |
| 94 | setup_mb_resource_map(); |
| 95 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 96 | printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 97 | |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 98 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 99 | |
| 100 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 101 | #if CONFIG_LOGICAL_CPUS |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 102 | // It is said that we should start core1 after all core0 launched |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 103 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 104 | * So here need to make sure last core0 is started, esp for two way system, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 105 | * (there may be apic id conflicts in that case) |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 106 | */ |
| 107 | start_other_cores(); |
| 108 | wait_all_other_cores_started(bsp_apicid); |
| 109 | #endif |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 110 | |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 111 | /* it will set up chains and store link pair for optimization later */ |
| 112 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 113 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 114 | #if CONFIG_SET_FIDVID |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 115 | { |
| 116 | msr_t msr; |
| 117 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 118 | printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 119 | } |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 120 | enable_fid_change(); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 121 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 122 | init_fidvid_bsp(bsp_apicid); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 123 | // show final fid and vid |
| 124 | { |
| 125 | msr_t msr; |
| 126 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 127 | printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 128 | } |
| 129 | #endif |
| 130 | |
| 131 | needs_reset = optimize_link_coherent_ht(); |
| 132 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 133 | |
| 134 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 135 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 136 | printk(BIOS_INFO, "ht reset -\n"); |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 137 | soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 138 | } |
| 139 | |
| 140 | allow_all_aps_stop(bsp_apicid); |
| 141 | |
| 142 | //It's the time to set ctrl in sysinfo now; |
| 143 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 144 | |
| 145 | enable_smbus(); |
| 146 | |
| 147 | #if 0 |
| 148 | dump_smbus_registers(); |
| 149 | #endif |
| 150 | |
| 151 | memreset_setup(); |
| 152 | |
| 153 | //do we need apci timer, tsc...., only debug need it for better output |
| 154 | /* all ap stopped? */ |
Paul Menzel | 4549e5a | 2014-02-02 22:05:48 +0100 | [diff] [blame] | 155 | init_timer(); // Need to use TMICT to synchronize FID/VID |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 156 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 157 | |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 158 | #if 0 |
| 159 | dump_pci_devices(); |
| 160 | #endif |
| 161 | |
| 162 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Yinghai Lu | c34e3ab | 2006-10-12 00:58:20 +0000 | [diff] [blame] | 163 | } |