| Damien Zammit | 74d165b | 2015-05-04 10:41:21 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | /* This is board specific information: IRQ routing for pineview */ |
| 18 | /* FIXME: EHCI controller not working yet */ |
| 19 | |
| 20 | /* PCI Interrupt Routing */ |
| 21 | Method(_PRT) |
| 22 | { |
| 23 | If (PICM) { |
| 24 | Return (Package() { |
| 25 | /* Internal GFX */ |
| 26 | Package() { 0x0002ffff, 0, 0, 16 }, |
| 27 | /* High Definition Audio 0:1b.0 */ |
| 28 | Package() { 0x001bffff, 0, 0, 22 }, |
| 29 | /* PCIe Root Ports 0:1c.x */ |
| 30 | Package() { 0x001cffff, 0, 0, 17 }, |
| 31 | Package() { 0x001cffff, 1, 0, 16 }, |
| 32 | Package() { 0x001cffff, 2, 0, 18 }, |
| 33 | Package() { 0x001cffff, 3, 0, 19 }, |
| 34 | /* USB and EHCI 0:1d.x */ |
| 35 | Package() { 0x001dffff, 0, 0, 23 }, |
| 36 | Package() { 0x001dffff, 1, 0, 19 }, |
| 37 | Package() { 0x001dffff, 2, 0, 18 }, |
| 38 | Package() { 0x001dffff, 3, 0, 16 }, |
| 39 | Package() { 0x001dffff, 0, 0, 23 }, |
| 40 | /* PCI 0:1e.0 */ |
| 41 | Package() { 0x001effff, 0, 0, 22 }, |
| 42 | /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ |
| 43 | Package() { 0x001fffff, 1, 0, 19 }, |
| 44 | Package() { 0x001fffff, 1, 0, 19 }, |
| 45 | Package() { 0x001fffff, 1, 0, 19 }, |
| 46 | }) |
| 47 | } Else { |
| 48 | Return (Package() { |
| 49 | /* Internal GFX */ |
| 50 | Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, |
| 51 | /* High Definition Audio 0:1b.0 */ |
| 52 | Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, |
| 53 | /* PCIe Root Ports 0:1c.x */ |
| 54 | Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, |
| 55 | Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, |
| 56 | Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, |
| 57 | Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, |
| 58 | /* USB and EHCI 0:1d.x */ |
| 59 | Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, |
| 60 | Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, |
| 61 | Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, |
| 62 | Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, |
| 63 | Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, |
| 64 | /* PCI 0:1e.0 */ |
| 65 | Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, |
| 66 | /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ |
| 67 | Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, |
| 68 | Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, |
| 69 | Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, |
| 70 | }) |
| 71 | } |
| 72 | } |