Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 15 | |
| 16 | chip soc/intel/fsp_baytrail |
| 17 | |
| 18 | #### ACPI Register Settings #### |
| 19 | register "fadt_pm_profile" = "PM_MOBILE" |
| 20 | register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" |
| 21 | |
| 22 | #### FSP register settings #### |
Martin Roth | e55a7c5 | 2014-11-16 17:09:15 -0700 | [diff] [blame] | 23 | register "PcdSataMode" = "SATA_MODE_AHCI" |
| 24 | register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" |
| 25 | register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" |
Martin Roth | e55a7c5 | 2014-11-16 17:09:15 -0700 | [diff] [blame] | 26 | register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" |
| 27 | register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" |
| 28 | register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" |
| 29 | register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" |
| 30 | register "PcdGttSize" = "GTT_SIZE_DEFAULT" |
| 31 | register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 32 | register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" |
| 33 | register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" |
| 34 | |
| 35 | device cpu_cluster 0 on |
| 36 | device lapic 0 on end |
| 37 | end |
| 38 | |
| 39 | device domain 0 on |
| 40 | device pci 00.0 on end # 8086 0F00 - SoC router |
| 41 | device pci 02.0 on end # 8086 0F31 - GFX |
| 42 | device pci 03.0 off end # 8086 0F38 - MIPI - camera interface |
| 43 | |
Martin Roth | 2c28ee8 | 2014-06-20 21:10:09 -0600 | [diff] [blame] | 44 | device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time |
| 45 | device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins) |
| 46 | device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins) |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 47 | device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23) |
Martin Roth | 0b4b230 | 2014-06-25 10:13:22 -0600 | [diff] [blame] | 48 | device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 49 | device pci 15.0 off end # 8086 0F28 - LP Engine Audio |
| 50 | device pci 16.0 off end # 8086 0F37 - OTG controller |
Martin Roth | 2c28ee8 | 2014-06-20 21:10:09 -0600 | [diff] [blame] | 51 | device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 52 | device pci 18.0 on end # 8086 0F40 - SIO - DMA |
| 53 | device pci 18.1 on end # 8086 0F41 - I2C Port 1 |
| 54 | device pci 18.2 on end # 8086 0F42 - I2C Port 2 |
| 55 | device pci 18.3 on end # 8086 0F43 - I2C Port 3 |
| 56 | device pci 18.4 on end # 8086 0F44 - I2C Port 4 |
| 57 | device pci 18.5 on end # 8086 0F45 - I2C Port 5 |
| 58 | device pci 18.6 on end # 8086 0F46 - I2C Port 6 |
| 59 | device pci 18.7 on end # 8086 0F47 - I2C Port 7 |
| 60 | device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine |
| 61 | device pci 1b.0 on end # 8086 0F04 - HD Audio |
| 62 | device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (x4 slot) |
| 63 | device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot) |
| 64 | device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot) |
| 65 | device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot) |
Martin Roth | 0b4b230 | 2014-06-25 10:13:22 -0600 | [diff] [blame] | 66 | device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time |
Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 67 | device pci 1e.0 on end # 8086 0F06 - SIO - DMA |
| 68 | device pci 1e.1 on end # 8086 0F08 - PWM 1 |
| 69 | device pci 1e.2 on end # 8086 0F09 - PWM 2 |
| 70 | device pci 1e.3 on end # 8086 0F0A - HSUART 1 |
| 71 | device pci 1e.4 on end # 8086 0F0C - HSUART 2 |
| 72 | device pci 1e.5 on end # 8086 0F0E - SPI |
| 73 | device pci 1f.0 on end # 8086 0F1C - LPC bridge |
| 74 | device pci 1f.3 on end # 8086 0F12 - SMBus 0 |
| 75 | end |
| 76 | end |