Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This is a ramstage driver for the Intel Management Engine found in the |
| 24 | * 6-series chipset. It handles the required boot-time messages over the |
| 25 | * MMIO-based Management Engine Interface to tell the ME that the BIOS is |
| 26 | * finished with POST. Additional messages are defined for debug but are |
| 27 | * not used unless the console loglevel is high enough. |
| 28 | */ |
| 29 | |
| 30 | #include <arch/acpi.h> |
| 31 | #include <arch/hlt.h> |
| 32 | #include <arch/io.h> |
| 33 | #include <console/console.h> |
| 34 | #include <device/pci_ids.h> |
| 35 | #include <device/pci_def.h> |
| 36 | #include <string.h> |
| 37 | #include <delay.h> |
| 38 | |
| 39 | #ifdef __SMM__ |
| 40 | # include <arch/romcc_io.h> |
| 41 | # include <northbridge/intel/sandybridge/pcie_config.c> |
| 42 | #else |
| 43 | # include <device/device.h> |
| 44 | # include <device/pci.h> |
| 45 | #endif |
| 46 | |
| 47 | #include "me.h" |
| 48 | #include "pch.h" |
| 49 | |
| 50 | #if CONFIG_CHROMEOS |
| 51 | #include <vendorcode/google/chromeos/gnvs.h> |
| 52 | #endif |
| 53 | |
| 54 | #ifndef __SMM__ |
| 55 | /* Path that the BIOS should take based on ME state */ |
| 56 | static const char *me_bios_path_values[] = { |
| 57 | [ME_NORMAL_BIOS_PATH] = "Normal", |
| 58 | [ME_S3WAKE_BIOS_PATH] = "S3 Wake", |
| 59 | [ME_ERROR_BIOS_PATH] = "Error", |
| 60 | [ME_RECOVERY_BIOS_PATH] = "Recovery", |
| 61 | [ME_DISABLE_BIOS_PATH] = "Disable", |
| 62 | [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", |
| 63 | }; |
| 64 | #endif |
| 65 | |
| 66 | /* MMIO base address for MEI interface */ |
| 67 | static u32 mei_base_address; |
| 68 | |
| 69 | #if CONFIG_DEBUG_INTEL_ME |
| 70 | static void mei_dump(void *ptr, int dword, int offset, const char *type) |
| 71 | { |
| 72 | struct mei_csr *csr; |
| 73 | |
| 74 | printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); |
| 75 | |
| 76 | switch (offset) { |
| 77 | case MEI_H_CSR: |
| 78 | case MEI_ME_CSR_HA: |
| 79 | csr = ptr; |
| 80 | if (!csr) { |
| 81 | printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); |
| 82 | break; |
| 83 | } |
| 84 | printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " |
| 85 | "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, |
| 86 | csr->buffer_read_ptr, csr->buffer_write_ptr, |
| 87 | csr->ready, csr->reset, csr->interrupt_generate, |
| 88 | csr->interrupt_status, csr->interrupt_enable); |
| 89 | break; |
| 90 | case MEI_ME_CB_RW: |
| 91 | case MEI_H_CB_WW: |
| 92 | printk(BIOS_SPEW, "CB: 0x%08x\n", dword); |
| 93 | break; |
| 94 | default: |
| 95 | printk(BIOS_SPEW, "0x%08x\n", offset); |
| 96 | break; |
| 97 | } |
| 98 | } |
| 99 | #else |
| 100 | # define mei_dump(ptr,dword,offset,type) do {} while (0) |
| 101 | #endif |
| 102 | |
| 103 | /* |
| 104 | * ME/MEI access helpers using memcpy to avoid aliasing. |
| 105 | */ |
| 106 | |
| 107 | static inline void mei_read_dword_ptr(void *ptr, int offset) |
| 108 | { |
| 109 | u32 dword = read32(mei_base_address + offset); |
| 110 | memcpy(ptr, &dword, sizeof(dword)); |
| 111 | mei_dump(ptr, dword, offset, "READ"); |
| 112 | } |
| 113 | |
| 114 | static inline void mei_write_dword_ptr(void *ptr, int offset) |
| 115 | { |
| 116 | u32 dword = 0; |
| 117 | memcpy(&dword, ptr, sizeof(dword)); |
| 118 | write32(mei_base_address + offset, dword); |
| 119 | mei_dump(ptr, dword, offset, "WRITE"); |
| 120 | } |
| 121 | |
| 122 | #ifndef __SMM__ |
| 123 | static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) |
| 124 | { |
| 125 | u32 dword = pci_read_config32(dev, offset); |
| 126 | memcpy(ptr, &dword, sizeof(dword)); |
| 127 | mei_dump(ptr, dword, offset, "PCI READ"); |
| 128 | } |
| 129 | #endif |
| 130 | |
| 131 | static inline void read_host_csr(struct mei_csr *csr) |
| 132 | { |
| 133 | mei_read_dword_ptr(csr, MEI_H_CSR); |
| 134 | } |
| 135 | |
| 136 | static inline void write_host_csr(struct mei_csr *csr) |
| 137 | { |
| 138 | mei_write_dword_ptr(csr, MEI_H_CSR); |
| 139 | } |
| 140 | |
| 141 | static inline void read_me_csr(struct mei_csr *csr) |
| 142 | { |
| 143 | mei_read_dword_ptr(csr, MEI_ME_CSR_HA); |
| 144 | } |
| 145 | |
| 146 | static inline void write_cb(u32 dword) |
| 147 | { |
| 148 | write32(mei_base_address + MEI_H_CB_WW, dword); |
| 149 | mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); |
| 150 | } |
| 151 | |
| 152 | static inline u32 read_cb(void) |
| 153 | { |
| 154 | u32 dword = read32(mei_base_address + MEI_ME_CB_RW); |
| 155 | mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); |
| 156 | return dword; |
| 157 | } |
| 158 | |
| 159 | /* Wait for ME ready bit to be asserted */ |
| 160 | static int mei_wait_for_me_ready(void) |
| 161 | { |
| 162 | struct mei_csr me; |
| 163 | unsigned try = ME_RETRY; |
| 164 | |
| 165 | while (try--) { |
| 166 | read_me_csr(&me); |
| 167 | if (me.ready) |
| 168 | return 0; |
| 169 | udelay(ME_DELAY); |
| 170 | } |
| 171 | |
| 172 | printk(BIOS_ERR, "ME: failed to become ready\n"); |
| 173 | return -1; |
| 174 | } |
| 175 | |
| 176 | static void mei_reset(void) |
| 177 | { |
| 178 | struct mei_csr host; |
| 179 | |
| 180 | if (mei_wait_for_me_ready() < 0) |
| 181 | return; |
| 182 | |
| 183 | /* Reset host and ME circular buffers for next message */ |
| 184 | read_host_csr(&host); |
| 185 | host.reset = 1; |
| 186 | host.interrupt_generate = 1; |
| 187 | write_host_csr(&host); |
| 188 | |
| 189 | if (mei_wait_for_me_ready() < 0) |
| 190 | return; |
| 191 | |
| 192 | /* Re-init and indicate host is ready */ |
| 193 | read_host_csr(&host); |
| 194 | host.interrupt_generate = 1; |
| 195 | host.ready = 1; |
| 196 | host.reset = 0; |
| 197 | write_host_csr(&host); |
| 198 | } |
| 199 | |
| 200 | static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, |
| 201 | void *req_data) |
| 202 | { |
| 203 | struct mei_csr host; |
| 204 | unsigned ndata, n; |
| 205 | u32 *data; |
| 206 | |
| 207 | /* Number of dwords to write, ignoring MKHI */ |
| 208 | ndata = mei->length >> 2; |
| 209 | |
| 210 | /* Pad non-dword aligned request message length */ |
| 211 | if (mei->length & 3) |
| 212 | ndata++; |
| 213 | if (!ndata) { |
| 214 | printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); |
| 215 | return -1; |
| 216 | } |
| 217 | ndata++; /* Add MEI header */ |
| 218 | |
| 219 | /* |
| 220 | * Make sure there is still room left in the circular buffer. |
| 221 | * Reset the buffer pointers if the requested message will not fit. |
| 222 | */ |
| 223 | read_host_csr(&host); |
| 224 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 225 | printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); |
| 226 | mei_reset(); |
| 227 | read_host_csr(&host); |
| 228 | } |
| 229 | |
| 230 | /* |
| 231 | * This implementation does not handle splitting large messages |
| 232 | * across multiple transactions. Ensure the requested length |
| 233 | * will fit in the available circular buffer depth. |
| 234 | */ |
| 235 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 236 | printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", |
| 237 | ndata + 2, host.buffer_depth); |
| 238 | return -1; |
| 239 | } |
| 240 | |
| 241 | /* Write MEI header */ |
| 242 | mei_write_dword_ptr(mei, MEI_H_CB_WW); |
| 243 | ndata--; |
| 244 | |
| 245 | /* Write MKHI header */ |
| 246 | mei_write_dword_ptr(mkhi, MEI_H_CB_WW); |
| 247 | ndata--; |
| 248 | |
| 249 | /* Write message data */ |
| 250 | data = req_data; |
| 251 | for (n = 0; n < ndata; ++n) |
| 252 | write_cb(*data++); |
| 253 | |
| 254 | /* Generate interrupt to the ME */ |
| 255 | read_host_csr(&host); |
| 256 | host.interrupt_generate = 1; |
| 257 | write_host_csr(&host); |
| 258 | |
| 259 | /* Make sure ME is ready after sending request data */ |
| 260 | return mei_wait_for_me_ready(); |
| 261 | } |
| 262 | |
| 263 | static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, |
| 264 | void *rsp_data, int rsp_bytes) |
| 265 | { |
| 266 | struct mei_header mei_rsp; |
| 267 | struct mkhi_header mkhi_rsp; |
| 268 | struct mei_csr me, host; |
| 269 | unsigned ndata, n; |
| 270 | unsigned expected; |
| 271 | u32 *data; |
| 272 | |
| 273 | /* Total number of dwords to read from circular buffer */ |
| 274 | expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; |
| 275 | if (rsp_bytes & 3) |
| 276 | expected++; |
| 277 | |
| 278 | /* |
| 279 | * The interrupt status bit does not appear to indicate that the |
| 280 | * message has actually been received. Instead we wait until the |
| 281 | * expected number of dwords are present in the circular buffer. |
| 282 | */ |
| 283 | for (n = ME_RETRY; n; --n) { |
| 284 | read_me_csr(&me); |
| 285 | if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) |
| 286 | break; |
| 287 | udelay(ME_DELAY); |
| 288 | } |
| 289 | if (!n) { |
| 290 | printk(BIOS_ERR, "ME: timeout waiting for data: expected " |
| 291 | "%u, available %u\n", expected, |
| 292 | me.buffer_write_ptr - me.buffer_read_ptr); |
| 293 | return -1; |
| 294 | } |
| 295 | |
| 296 | /* Read and verify MEI response header from the ME */ |
| 297 | mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); |
| 298 | if (!mei_rsp.is_complete) { |
| 299 | printk(BIOS_ERR, "ME: response is not complete\n"); |
| 300 | return -1; |
| 301 | } |
| 302 | |
| 303 | /* Handle non-dword responses and expect at least MKHI header */ |
| 304 | ndata = mei_rsp.length >> 2; |
| 305 | if (mei_rsp.length & 3) |
| 306 | ndata++; |
| 307 | if (ndata != (expected - 1)) { |
| 308 | printk(BIOS_ERR, "ME: response is missing data\n"); |
| 309 | return -1; |
| 310 | } |
| 311 | |
| 312 | /* Read and verify MKHI response header from the ME */ |
| 313 | mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); |
| 314 | if (!mkhi_rsp.is_response || |
| 315 | mkhi->group_id != mkhi_rsp.group_id || |
| 316 | mkhi->command != mkhi_rsp.command) { |
| 317 | printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " |
| 318 | "command %u ?= %u, is_response %u\n", mkhi->group_id, |
| 319 | mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, |
| 320 | mkhi_rsp.is_response); |
| 321 | return -1; |
| 322 | } |
| 323 | ndata--; /* MKHI header has been read */ |
| 324 | |
| 325 | /* Make sure caller passed a buffer with enough space */ |
| 326 | if (ndata != (rsp_bytes >> 2)) { |
| 327 | printk(BIOS_ERR, "ME: not enough room in response buffer: " |
| 328 | "%u != %u\n", ndata, rsp_bytes >> 2); |
| 329 | return -1; |
| 330 | } |
| 331 | |
| 332 | /* Read response data from the circular buffer */ |
| 333 | data = rsp_data; |
| 334 | for (n = 0; n < ndata; ++n) |
| 335 | *data++ = read_cb(); |
| 336 | |
| 337 | /* Tell the ME that we have consumed the response */ |
| 338 | read_host_csr(&host); |
| 339 | host.interrupt_status = 1; |
| 340 | host.interrupt_generate = 1; |
| 341 | write_host_csr(&host); |
| 342 | |
| 343 | return mei_wait_for_me_ready(); |
| 344 | } |
| 345 | |
| 346 | static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, |
| 347 | void *req_data, void *rsp_data, int rsp_bytes) |
| 348 | { |
| 349 | if (mei_send_msg(mei, mkhi, req_data) < 0) |
| 350 | return -1; |
| 351 | if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0) |
| 352 | return -1; |
| 353 | return 0; |
| 354 | } |
| 355 | |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 356 | #ifdef __SMM__ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 357 | /* Send END OF POST message to the ME */ |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 358 | static int mkhi_end_of_post(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 359 | { |
| 360 | struct mkhi_header mkhi = { |
| 361 | .group_id = MKHI_GROUP_ID_GEN, |
| 362 | .command = MKHI_END_OF_POST, |
| 363 | }; |
| 364 | struct mei_header mei = { |
| 365 | .is_complete = 1, |
| 366 | .host_address = MEI_HOST_ADDRESS, |
| 367 | .client_address = MEI_ADDRESS_MKHI, |
| 368 | .length = sizeof(mkhi), |
| 369 | }; |
| 370 | |
| 371 | /* Send request and wait for response */ |
| 372 | if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { |
| 373 | printk(BIOS_ERR, "ME: END OF POST message failed\n"); |
| 374 | return -1; |
| 375 | } |
| 376 | |
| 377 | printk(BIOS_INFO, "ME: END OF POST message successful\n"); |
| 378 | return 0; |
| 379 | } |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 380 | #endif |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 381 | |
| 382 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) |
| 383 | /* Get ME firmware version */ |
| 384 | static int mkhi_get_fw_version(void) |
| 385 | { |
| 386 | struct me_fw_version version; |
| 387 | struct mkhi_header mkhi = { |
| 388 | .group_id = MKHI_GROUP_ID_GEN, |
| 389 | .command = MKHI_GET_FW_VERSION, |
| 390 | }; |
| 391 | struct mei_header mei = { |
| 392 | .is_complete = 1, |
| 393 | .host_address = MEI_HOST_ADDRESS, |
| 394 | .client_address = MEI_ADDRESS_MKHI, |
| 395 | .length = sizeof(mkhi), |
| 396 | }; |
| 397 | |
| 398 | /* Send request and wait for response */ |
| 399 | if (mei_sendrecv(&mei, &mkhi, NULL, &version, sizeof(version)) < 0) { |
| 400 | printk(BIOS_ERR, "ME: GET FW VERSION message failed\n"); |
| 401 | return -1; |
| 402 | } |
| 403 | |
| 404 | printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) " |
| 405 | "%u.%u.%u.%u (recovery)\n", |
| 406 | version.code_major, version.code_minor, |
| 407 | version.code_build_number, version.code_hot_fix, |
| 408 | version.recovery_major, version.recovery_minor, |
| 409 | version.recovery_build_number, version.recovery_hot_fix); |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static inline void print_cap(const char *name, int state) |
| 415 | { |
| 416 | printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", |
| 417 | name, state ? "en" : "dis"); |
| 418 | } |
| 419 | |
| 420 | /* Get ME Firmware Capabilities */ |
| 421 | static int mkhi_get_fwcaps(void) |
| 422 | { |
| 423 | u32 rule_id = 0; |
| 424 | struct me_fwcaps cap; |
| 425 | struct mkhi_header mkhi = { |
| 426 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 427 | .command = MKHI_FWCAPS_GET_RULE, |
| 428 | }; |
| 429 | struct mei_header mei = { |
| 430 | .is_complete = 1, |
| 431 | .host_address = MEI_HOST_ADDRESS, |
| 432 | .client_address = MEI_ADDRESS_MKHI, |
| 433 | .length = sizeof(mkhi) + sizeof(rule_id), |
| 434 | }; |
| 435 | |
| 436 | /* Send request and wait for response */ |
| 437 | if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) { |
| 438 | printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); |
| 439 | return -1; |
| 440 | } |
| 441 | |
| 442 | print_cap("Full Network manageability", cap.caps_sku.full_net); |
| 443 | print_cap("Regular Network manageability", cap.caps_sku.std_net); |
| 444 | print_cap("Manageability", cap.caps_sku.manageability); |
| 445 | print_cap("Small business technology", cap.caps_sku.small_business); |
| 446 | print_cap("Level III manageability", cap.caps_sku.l3manageability); |
| 447 | print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); |
| 448 | print_cap("IntelR Capability Licensing Service (CLS)", |
| 449 | cap.caps_sku.intel_cls); |
| 450 | print_cap("IntelR Power Sharing Technology (MPC)", |
| 451 | cap.caps_sku.intel_mpc); |
| 452 | print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); |
| 453 | print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); |
| 454 | print_cap("IPV6", cap.caps_sku.ipv6); |
| 455 | print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); |
| 456 | print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); |
| 457 | print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); |
| 458 | print_cap("TLS", cap.caps_sku.tls); |
| 459 | print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); |
| 460 | |
| 461 | return 0; |
| 462 | } |
| 463 | #endif |
| 464 | |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 465 | #if CONFIG_CHROMEOS && 0 /* DISABLED */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 466 | /* Tell ME to issue a global reset */ |
| 467 | int mkhi_global_reset(void) |
| 468 | { |
| 469 | struct me_global_reset reset = { |
| 470 | .request_origin = GLOBAL_RESET_BIOS_POST, |
| 471 | .reset_type = CBM_RR_GLOBAL_RESET, |
| 472 | }; |
| 473 | struct mkhi_header mkhi = { |
| 474 | .group_id = MKHI_GROUP_ID_CBM, |
| 475 | .command = MKHI_GLOBAL_RESET, |
| 476 | }; |
| 477 | struct mei_header mei = { |
| 478 | .is_complete = 1, |
| 479 | .length = sizeof(mkhi) + sizeof(reset), |
| 480 | .host_address = MEI_HOST_ADDRESS, |
| 481 | .client_address = MEI_ADDRESS_MKHI, |
| 482 | }; |
| 483 | |
| 484 | printk(BIOS_NOTICE, "ME: Requesting global reset\n"); |
| 485 | |
| 486 | /* Send request and wait for response */ |
| 487 | if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { |
| 488 | /* No response means reset will happen shortly... */ |
| 489 | hlt(); |
| 490 | } |
| 491 | |
| 492 | /* If the ME responded it rejected the reset request */ |
| 493 | printk(BIOS_ERR, "ME: Global Reset failed\n"); |
| 494 | return -1; |
| 495 | } |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 496 | #endif |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 497 | |
| 498 | #ifdef __SMM__ |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 499 | static void intel_me7_finalize_smm(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 500 | { |
| 501 | struct me_hfs hfs; |
| 502 | u32 reg32; |
| 503 | |
| 504 | mei_base_address = |
| 505 | pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; |
| 506 | |
| 507 | /* S3 path will have hidden this device already */ |
| 508 | if (!mei_base_address || mei_base_address == 0xfffffff0) |
| 509 | return; |
| 510 | |
| 511 | /* Make sure ME is in a mode that expects EOP */ |
| 512 | reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); |
| 513 | memcpy(&hfs, ®32, sizeof(u32)); |
| 514 | |
| 515 | /* Abort and leave device alone if not normal mode */ |
| 516 | if (hfs.fpt_bad || |
| 517 | hfs.working_state != ME_HFS_CWS_NORMAL || |
| 518 | hfs.operation_mode != ME_HFS_MODE_NORMAL) |
| 519 | return; |
| 520 | |
| 521 | /* Try to send EOP command so ME stops accepting other commands */ |
| 522 | mkhi_end_of_post(); |
| 523 | |
| 524 | /* Make sure IO is disabled */ |
| 525 | reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); |
| 526 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 527 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 528 | pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); |
| 529 | |
| 530 | /* Hide the PCI device */ |
| 531 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 532 | } |
| 533 | |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 534 | void intel_me_finalize_smm(void) |
| 535 | { |
Stefan Reinauer | 9842ad8 | 2012-06-13 16:31:50 -0700 | [diff] [blame] | 536 | u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 537 | switch (did) { |
Duncan Laurie | 708f731 | 2012-07-10 15:15:41 -0700 | [diff] [blame^] | 538 | case 0x1c3a8086: |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 539 | intel_me7_finalize_smm(); |
| 540 | break; |
Duncan Laurie | 708f731 | 2012-07-10 15:15:41 -0700 | [diff] [blame^] | 541 | case 0x1e3a8086: |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame] | 542 | intel_me8_finalize_smm(); |
| 543 | break; |
| 544 | default: |
| 545 | printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); |
| 546 | } |
| 547 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 548 | #else /* !__SMM__ */ |
| 549 | |
| 550 | /* Determine the path that we should take based on ME status */ |
| 551 | static me_bios_path intel_me_path(device_t dev) |
| 552 | { |
| 553 | me_bios_path path = ME_DISABLE_BIOS_PATH; |
| 554 | struct me_hfs hfs; |
| 555 | struct me_gmes gmes; |
| 556 | |
| 557 | #if CONFIG_HAVE_ACPI_RESUME |
| 558 | /* S3 wake skips all MKHI messages */ |
| 559 | if (acpi_slp_type == 3) { |
| 560 | return ME_S3WAKE_BIOS_PATH; |
| 561 | } |
| 562 | #endif |
| 563 | |
| 564 | pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); |
| 565 | pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); |
| 566 | |
| 567 | /* Check and dump status */ |
| 568 | intel_me_status(&hfs, &gmes); |
| 569 | |
| 570 | /* Check for valid firmware */ |
| 571 | if (hfs.fpt_bad) |
| 572 | return ME_ERROR_BIOS_PATH; |
| 573 | |
| 574 | /* Check Current Working State */ |
| 575 | switch (hfs.working_state) { |
| 576 | case ME_HFS_CWS_NORMAL: |
| 577 | path = ME_NORMAL_BIOS_PATH; |
| 578 | break; |
| 579 | case ME_HFS_CWS_REC: |
| 580 | path = ME_RECOVERY_BIOS_PATH; |
| 581 | break; |
| 582 | default: |
| 583 | path = ME_DISABLE_BIOS_PATH; |
| 584 | break; |
| 585 | } |
| 586 | |
| 587 | /* Check Current Operation Mode */ |
| 588 | switch (hfs.operation_mode) { |
| 589 | case ME_HFS_MODE_NORMAL: |
| 590 | break; |
| 591 | case ME_HFS_MODE_DEBUG: |
| 592 | case ME_HFS_MODE_DIS: |
| 593 | case ME_HFS_MODE_OVER_JMPR: |
| 594 | case ME_HFS_MODE_OVER_MEI: |
| 595 | default: |
| 596 | path = ME_DISABLE_BIOS_PATH; |
| 597 | break; |
| 598 | } |
| 599 | |
| 600 | /* Check for any error code */ |
| 601 | if (hfs.error_code) |
| 602 | path = ME_ERROR_BIOS_PATH; |
| 603 | |
| 604 | return path; |
| 605 | } |
| 606 | |
| 607 | /* Prepare ME for MEI messages */ |
| 608 | static int intel_mei_setup(device_t dev) |
| 609 | { |
| 610 | struct resource *res; |
| 611 | struct mei_csr host; |
| 612 | u32 reg32; |
| 613 | |
| 614 | /* Find the MMIO base for the ME interface */ |
| 615 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 616 | if (!res || res->base == 0 || res->size == 0) { |
| 617 | printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); |
| 618 | return -1; |
| 619 | } |
| 620 | mei_base_address = res->base; |
| 621 | |
| 622 | /* Ensure Memory and Bus Master bits are set */ |
| 623 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 624 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 625 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 626 | |
| 627 | /* Clean up status for next message */ |
| 628 | read_host_csr(&host); |
| 629 | host.interrupt_generate = 1; |
| 630 | host.ready = 1; |
| 631 | host.reset = 0; |
| 632 | write_host_csr(&host); |
| 633 | |
| 634 | return 0; |
| 635 | } |
| 636 | |
| 637 | /* Read the Extend register hash of ME firmware */ |
| 638 | static int intel_me_extend_valid(device_t dev) |
| 639 | { |
| 640 | struct me_heres status; |
Stefan Reinauer | 49058c0 | 2012-06-11 14:13:09 -0700 | [diff] [blame] | 641 | u32 extend[8] = {0}; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 642 | int i, count = 0; |
| 643 | |
| 644 | pci_read_dword_ptr(dev, &status, PCI_ME_HERES); |
| 645 | if (!status.extend_feature_present) { |
| 646 | printk(BIOS_ERR, "ME: Extend Feature not present\n"); |
| 647 | return -1; |
| 648 | } |
| 649 | |
| 650 | if (!status.extend_reg_valid) { |
| 651 | printk(BIOS_ERR, "ME: Extend Register not valid\n"); |
| 652 | return -1; |
| 653 | } |
| 654 | |
| 655 | switch (status.extend_reg_algorithm) { |
| 656 | case PCI_ME_EXT_SHA1: |
| 657 | count = 5; |
| 658 | printk(BIOS_DEBUG, "ME: Extend SHA-1: "); |
| 659 | break; |
| 660 | case PCI_ME_EXT_SHA256: |
| 661 | count = 8; |
| 662 | printk(BIOS_DEBUG, "ME: Extend SHA-256: "); |
| 663 | break; |
| 664 | default: |
| 665 | printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", |
| 666 | status.extend_reg_algorithm); |
| 667 | return -1; |
| 668 | } |
| 669 | |
| 670 | for (i = 0; i < count; ++i) { |
| 671 | extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); |
| 672 | printk(BIOS_DEBUG, "%08x", extend[i]); |
| 673 | } |
| 674 | printk(BIOS_DEBUG, "\n"); |
| 675 | |
| 676 | #if CONFIG_CHROMEOS |
| 677 | /* Save hash in NVS for the OS to verify */ |
| 678 | chromeos_set_me_hash(extend, count); |
| 679 | #endif |
| 680 | |
| 681 | return 0; |
| 682 | } |
| 683 | |
| 684 | /* Hide the ME virtual PCI devices */ |
| 685 | static void intel_me_hide(device_t dev) |
| 686 | { |
| 687 | dev->enabled = 0; |
| 688 | pch_enable(dev); |
| 689 | } |
| 690 | |
| 691 | /* Check whether ME is present and do basic init */ |
| 692 | static void intel_me_init(device_t dev) |
| 693 | { |
| 694 | me_bios_path path = intel_me_path(dev); |
| 695 | |
| 696 | /* Do initial setup and determine the BIOS path */ |
| 697 | printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); |
| 698 | |
| 699 | switch (path) { |
| 700 | case ME_S3WAKE_BIOS_PATH: |
| 701 | intel_me_hide(dev); |
| 702 | break; |
| 703 | |
| 704 | case ME_NORMAL_BIOS_PATH: |
| 705 | /* Validate the extend register */ |
| 706 | if (intel_me_extend_valid(dev) < 0) |
| 707 | break; /* TODO: force recovery mode */ |
| 708 | |
| 709 | /* Prepare MEI MMIO interface */ |
| 710 | if (intel_mei_setup(dev) < 0) |
| 711 | break; |
| 712 | |
| 713 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 714 | /* Print ME firmware version */ |
| 715 | mkhi_get_fw_version(); |
| 716 | /* Print ME firmware capabilities */ |
| 717 | mkhi_get_fwcaps(); |
| 718 | #endif |
| 719 | |
| 720 | /* |
| 721 | * Leave the ME unlocked in this path. |
| 722 | * It will be locked via SMI command later. |
| 723 | */ |
| 724 | break; |
| 725 | |
| 726 | case ME_ERROR_BIOS_PATH: |
| 727 | case ME_RECOVERY_BIOS_PATH: |
| 728 | case ME_DISABLE_BIOS_PATH: |
| 729 | case ME_FIRMWARE_UPDATE_BIOS_PATH: |
| 730 | /* |
| 731 | * TODO(dlaurie) Force recovery mode if ME is unhappy? |
| 732 | */ |
| 733 | break; |
| 734 | } |
| 735 | } |
| 736 | |
| 737 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 738 | { |
| 739 | if (!vendor || !device) { |
| 740 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 741 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 742 | } else { |
| 743 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 744 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 745 | } |
| 746 | } |
| 747 | |
| 748 | static struct pci_operations pci_ops = { |
| 749 | .set_subsystem = set_subsystem, |
| 750 | }; |
| 751 | |
| 752 | static struct device_operations device_ops = { |
| 753 | .read_resources = pci_dev_read_resources, |
| 754 | .set_resources = pci_dev_set_resources, |
| 755 | .enable_resources = pci_dev_enable_resources, |
| 756 | .init = intel_me_init, |
| 757 | .scan_bus = scan_static_bus, |
| 758 | .ops_pci = &pci_ops, |
| 759 | }; |
| 760 | |
| 761 | static const struct pci_driver intel_me __pci_driver = { |
| 762 | .ops = &device_ops, |
| 763 | .vendor = PCI_VENDOR_ID_INTEL, |
| 764 | .device = 0x1c3a, |
| 765 | }; |
| 766 | |
| 767 | #endif /* !__SMM__ */ |