Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 3 | * |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2005 Eswar Nallusamy, LANL |
| 6 | * Copyright (C) 2005 Tyan |
| 7 | * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan) |
| 8 | * Copyright (C) 2007 coresystems GmbH |
| 9 | * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH) |
| 10 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 11 | * |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; version 2 of the License. |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 15 | * |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 20 | * |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 24 | */ |
| 25 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 26 | /* We will use 4K bytes only */ |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 27 | /* disable HyperThreading is done by eswar*/ |
| 28 | /* other's is the same as AMD except remove amd specific msr */ |
| 29 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 30 | #define CacheSize CONFIG_DCACHE_RAM_SIZE |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 31 | #define CacheBase (0xd0000 - CacheSize) |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 32 | |
| 33 | #include <cpu/x86/mtrr.h> |
| 34 | |
| 35 | /* Save the BIST result */ |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 36 | movl %eax, %ebp |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 37 | |
| 38 | CacheAsRam: |
| 39 | /* hope we can skip the double set for normal part */ |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 40 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 41 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 42 | // Check whether the processor has HT capability |
| 43 | movl $01, %eax |
| 44 | cpuid |
| 45 | btl $28, %edx |
| 46 | jnc NotHtProcessor |
| 47 | bswapl %ebx |
| 48 | cmpb $01, %bh |
| 49 | jbe NotHtProcessor |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 50 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 51 | // It is a HT processor; Send SIPI to the other logical processor |
| 52 | // within this processor so that the CAR related common system registers |
| 53 | // are programmed accordingly |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 54 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 55 | // Use some register that is common to both logical processors |
| 56 | // as semaphore. Refer Appendix B, Vol.3 |
| 57 | xorl %eax, %eax |
| 58 | xorl %edx, %edx |
| 59 | movl $0x250, %ecx |
| 60 | wrmsr |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 61 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 62 | // Figure out the logical AP's APIC ID; the following logic will work |
| 63 | // only for processors with 2 threads |
| 64 | // Refer to Vol 3. Table 7-1 for details about this logic |
| 65 | movl $0xFEE00020, %esi |
| 66 | movl (%esi), %ebx |
| 67 | andl $0xFF000000, %ebx |
| 68 | bswapl %ebx |
| 69 | btl $0, %ebx |
| 70 | jnc LogicalAP0 |
| 71 | andb $0xFE, %bl |
| 72 | jmp Send_SIPI |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 73 | LogicalAP0: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 74 | orb $0x01, %bl |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 75 | Send_SIPI: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 76 | bswapl %ebx // ebx - logical AP's APIC ID |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 77 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 78 | // Fill up the IPI command registers in the Local APIC mapped to default address |
| 79 | // and issue SIPI to the other logical processor within this processor die. |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 80 | Retry_SIPI: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 81 | movl %ebx, %eax |
| 82 | movl $0xFEE00310, %esi |
| 83 | movl %eax, (%esi) |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 84 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 85 | // SIPI vector - F900:0000 |
| 86 | movl $0x000006F9, %eax |
| 87 | movl $0xFEE00300, %esi |
| 88 | movl %eax, (%esi) |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 89 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 90 | movl $0x30, %ecx |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 91 | SIPI_Delay: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 92 | pause |
| 93 | decl %ecx |
| 94 | jnz SIPI_Delay |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 95 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 96 | movl (%esi), %eax |
| 97 | andl $0x00001000, %eax |
| 98 | jnz Retry_SIPI |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 99 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 100 | // Wait for the Logical AP to complete initialization |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 101 | LogicalAP_SIPINotdone: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 102 | movl $0x250, %ecx |
| 103 | rdmsr |
| 104 | orl %eax, %eax |
| 105 | jz LogicalAP_SIPINotdone |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 106 | |
| 107 | NotHtProcessor: |
| 108 | |
| 109 | #if 1 |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 110 | /* Set the default memory type and enable fixed and variable MTRRs */ |
| 111 | movl $MTRRdefType_MSR, %ecx |
| 112 | xorl %edx, %edx |
| 113 | /* Enable Variable and Fixed MTRRs */ |
| 114 | movl $0x00000c00, %eax |
| 115 | wrmsr |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 116 | #endif |
| 117 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 118 | /* Clear all MTRRs */ |
| 119 | xorl %edx, %edx |
| 120 | movl $fixed_mtrr_msr, %esi |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 121 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 122 | clear_fixed_var_mtrr: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 123 | lodsl (%esi), %eax |
| 124 | testl %eax, %eax |
| 125 | jz clear_fixed_var_mtrr_out |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 126 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 127 | movl %eax, %ecx |
| 128 | xorl %eax, %eax |
| 129 | wrmsr |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 130 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 131 | jmp clear_fixed_var_mtrr |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 132 | clear_fixed_var_mtrr_out: |
| 133 | |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 134 | /* 0x06 is the WB IO type for a given 4k segment. |
| 135 | * segs is the number of 4k segments in the area of the particular |
| 136 | * register we want to use for CAR. |
| 137 | * reg is the register where the IO type should be stored. |
| 138 | */ |
| 139 | .macro extractmask segs, reg |
| 140 | .if \segs <= 0 |
| 141 | /* The xorl here is superfluous because at the point of first execution |
| 142 | * of this macro, %eax and %edx are cleared. Later invocations of this |
| 143 | * macro will have a monotonically increasing segs parameter. |
| 144 | */ |
| 145 | xorl \reg, \reg |
| 146 | .elseif \segs == 1 |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 147 | movl $0x06000000, \reg /* WB IO type */ |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 148 | .elseif \segs == 2 |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 149 | movl $0x06060000, \reg /* WB IO type */ |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 150 | .elseif \segs == 3 |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 151 | movl $0x06060600, \reg /* WB IO type */ |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 152 | .elseif \segs >= 4 |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 153 | movl $0x06060606, \reg /* WB IO type */ |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 154 | .endif |
| 155 | .endm |
| 156 | |
| 157 | /* size is the cache size in bytes we want to use for CAR. |
| 158 | * windowoffset is the 32k-aligned window into CAR size |
| 159 | */ |
| 160 | .macro simplemask carsize, windowoffset |
Carl-Daniel Hailfinger | 4afb7fb | 2008-04-04 15:02:45 +0000 | [diff] [blame] | 161 | .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) |
| 162 | extractmask gas_bug_workaround, %eax |
| 163 | .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) |
| 164 | extractmask gas_bug_workaround, %edx |
| 165 | /* Without the gas bug workaround, the entire macro would consist only of the |
| 166 | * two lines below. |
Carl-Daniel Hailfinger | 188288a | 2008-01-08 19:14:16 +0000 | [diff] [blame] | 167 | extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax |
| 168 | extractmask (((\carsize - \windowoffset) / 0x1000)), %edx |
Carl-Daniel Hailfinger | 4afb7fb | 2008-04-04 15:02:45 +0000 | [diff] [blame] | 169 | */ |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 170 | .endm |
| 171 | |
| 172 | #if CacheSize > 0x10000 |
| 173 | #error Invalid CAR size, must be at most 64k. |
| 174 | #endif |
| 175 | #if CacheSize < 0x1000 |
| 176 | #error Invalid CAR size, must be at least 4k. This is a processor limitation. |
| 177 | #endif |
| 178 | #if (CacheSize & (0x1000 - 1)) |
| 179 | #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. |
| 180 | #endif |
| 181 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 182 | #if CacheSize > 0x8000 |
| 183 | /* enable caching for 32K-64K using fixed mtrr */ |
| 184 | movl $0x268, %ecx /* fix4k_c0000*/ |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 185 | simplemask CacheSize, 0x8000 |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 186 | wrmsr |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 187 | #endif |
| 188 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 189 | /* enable caching for 0-32K using fixed mtrr */ |
| 190 | movl $0x269, %ecx /* fix4k_c8000*/ |
Carl-Daniel Hailfinger | 4d1aa0a | 2008-01-08 17:06:38 +0000 | [diff] [blame] | 191 | simplemask CacheSize, 0 |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 192 | wrmsr |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 193 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 194 | #else |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 195 | /* disable cache */ |
| 196 | movl %cr0, %eax |
| 197 | orl $(0x1 << 30), %eax |
| 198 | movl %eax, %cr0 |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 199 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 200 | #endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/ |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 201 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 202 | #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 203 | /* enable write base caching so we can do execute in place |
| 204 | * on the flash rom. |
| 205 | */ |
| 206 | movl $0x202, %ecx |
| 207 | xorl %edx, %edx |
| 208 | movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax |
| 209 | wrmsr |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 210 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 211 | movl $0x203, %ecx |
| 212 | movl $0x0000000f, %edx |
| 213 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax |
| 214 | wrmsr |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 215 | #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 216 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 217 | /* enable cache */ |
| 218 | movl %cr0, %eax |
| 219 | andl $0x9fffffff, %eax |
| 220 | movl %eax, %cr0 |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 221 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 222 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 223 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 224 | /* Read the range with lodsl*/ |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 225 | movl $CacheBase, %esi |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 226 | cld |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 227 | movl $(CacheSize >> 2), %ecx |
| 228 | rep lodsl |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 229 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 230 | /* Clear the range */ |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 231 | movl $CacheBase, %edi |
| 232 | movl $(CacheSize >> 2), %ecx |
| 233 | xorl %eax, %eax |
| 234 | rep stosl |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 235 | |
| 236 | |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 237 | #if 0 |
| 238 | /* check the cache as ram */ |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 239 | movl $CacheBase, %esi |
| 240 | movl $(CacheSize>>2), %ecx |
| 241 | .xin1: |
| 242 | movl %esi, %eax |
| 243 | movl %eax, (%esi) |
| 244 | decl %ecx |
| 245 | je .xout1 |
| 246 | add $4, %esi |
| 247 | jmp .xin1 |
| 248 | .xout1: |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 249 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 250 | movl $CacheBase, %esi |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 251 | // movl $(CacheSize>>2), %ecx |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 252 | movl $4, %ecx |
| 253 | .xin1x: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 254 | movl %esi, %eax |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 255 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 256 | movl $0x4000, %edx |
| 257 | movb %ah, %al |
| 258 | .testx1: |
| 259 | outb %al, $0x80 |
| 260 | decl %edx |
| 261 | jnz .testx1 |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 262 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 263 | movl (%esi), %eax |
| 264 | cmpb 0xff, %al |
| 265 | je .xin2 /* dont show */ |
| 266 | |
| 267 | movl $0x4000, %edx |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 268 | .testx2: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 269 | outb %al, $0x80 |
| 270 | decl %edx |
| 271 | jnz .testx2 |
| 272 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 273 | .xin2: decl %ecx |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 274 | je .xout1x |
| 275 | add $4, %esi |
| 276 | jmp .xin1x |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 277 | .xout1x: |
| 278 | |
| 279 | #endif |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 280 | #endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 281 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 282 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 283 | movl $(CacheBase + CacheSize - 4), %eax |
| 284 | movl %eax, %esp |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 285 | |
| 286 | /* Load a different set of data segments */ |
| 287 | #if CONFIG_USE_INIT |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 288 | movw $CACHE_RAM_DATA_SEG, %ax |
| 289 | movw %ax, %ds |
| 290 | movw %ax, %es |
| 291 | movw %ax, %ss |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 292 | #endif |
| 293 | |
| 294 | lout: |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 295 | /* Restore the BIST result */ |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 296 | movl %ebp, %eax |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 297 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 298 | /* We need to set ebp ? No need */ |
| 299 | movl %esp, %ebp |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 300 | pushl %eax /* bist */ |
| 301 | call amd64_main |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 302 | /* We will not go back */ |
| 303 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 304 | fixed_mtrr_msr: |
| 305 | .long 0x250, 0x258, 0x259 |
| 306 | .long 0x268, 0x269, 0x26A |
| 307 | .long 0x26B, 0x26C, 0x26D |
| 308 | .long 0x26E, 0x26F |
| 309 | var_mtrr_msr: |
| 310 | .long 0x200, 0x201, 0x202, 0x203 |
| 311 | .long 0x204, 0x205, 0x206, 0x207 |
| 312 | .long 0x208, 0x209, 0x20A, 0x20B |
| 313 | .long 0x20C, 0x20D, 0x20E, 0x20F |
| 314 | .long 0x000 /* NULL, end of table */ |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 315 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 316 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 317 | .align 0x1000 |
| 318 | .code16 |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 319 | .global LogicalAP_SIPI |
| 320 | LogicalAP_SIPI: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 321 | // cr0 register is shared among the logical processors; |
| 322 | // so clear CD & NW bits so that the BSP's cr0 register |
| 323 | // controls the cache behavior |
| 324 | // Note: The cache behavior is determined by "OR" result |
| 325 | // of the cr0 registers of the logical processors |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 326 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 327 | movl %cr0, %eax |
| 328 | andl $0x9FFFFFFF, %eax |
| 329 | movl %eax, %cr0 |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 330 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 331 | finit |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 332 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 333 | // Set the semaphore to indicate the Logical AP is done |
| 334 | // with CAR specific initialization |
| 335 | movl $0x250, %ecx |
| 336 | movl $0x06, %eax |
| 337 | xorl %edx, %edx |
| 338 | wrmsr |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 339 | |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 340 | // Halt this AP |
| 341 | cli |
arch import user (historical) | fb07bf4 | 2005-07-06 18:17:43 +0000 | [diff] [blame] | 342 | Halt_LogicalAP: |
Myles Watson | 707fad0 | 2009-10-23 18:22:27 +0000 | [diff] [blame^] | 343 | hlt |
| 344 | jmp Halt_LogicalAP |
| 345 | .code32 |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 346 | #endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 347 | .CacheAsRam_out: |