Ronald G. Minnich | df46cb2 | 2006-04-18 16:36:58 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## Compute the location and size of where this firmware image |
| 3 | ## (linuxBIOS plus bootloader) will live in the boot rom chip. |
| 4 | ## |
| 5 | if USE_FALLBACK_IMAGE |
| 6 | default ROM_SECTION_SIZE = FALLBACK_SIZE |
| 7 | default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) |
| 8 | else |
| 9 | default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) |
| 10 | default ROM_SECTION_OFFSET = 0 |
| 11 | end |
| 12 | |
| 13 | ## |
| 14 | ## Compute the start location and size size of |
| 15 | ## The linuxBIOS bootloader. |
| 16 | ## |
| 17 | default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) |
| 18 | default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) |
| 19 | |
| 20 | ## |
| 21 | ## Compute where this copy of linuxBIOS will start in the boot rom |
| 22 | ## |
| 23 | default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) |
| 24 | |
| 25 | ## |
| 26 | ## Compute a range of ROM that can cached to speed up linuxBIOS, |
| 27 | ## execution speed. |
| 28 | ## |
| 29 | ## XIP_ROM_SIZE must be a power of 2. |
| 30 | ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE |
| 31 | ## |
| 32 | default XIP_ROM_SIZE=65536 |
| 33 | default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) |
| 34 | |
| 35 | ## |
| 36 | ## Set all of the defaults for an x86 architecture |
| 37 | ## |
| 38 | |
| 39 | arch i386 end |
| 40 | |
| 41 | ## |
| 42 | ## Build the objects we have code for in this directory. |
| 43 | ## |
| 44 | |
| 45 | driver mainboard.o |
| 46 | |
| 47 | if HAVE_PIRQ_TABLE object irq_tables.o end |
| 48 | #object reset.o |
| 49 | |
| 50 | ## |
| 51 | ## Romcc output |
| 52 | ## |
| 53 | makerule ./failover.E |
| 54 | depends "$(MAINBOARD)/failover.c ./romcc" |
| 55 | action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" |
| 56 | end |
| 57 | |
| 58 | makerule ./failover.inc |
| 59 | depends "$(MAINBOARD)/failover.c ./romcc" |
| 60 | action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" |
| 61 | end |
| 62 | |
| 63 | makerule ./auto.E |
| 64 | depends "$(MAINBOARD)/auto.c option_table.h ./romcc" |
| 65 | action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" |
| 66 | end |
| 67 | makerule ./auto.inc |
| 68 | depends "$(MAINBOARD)/auto.c option_table.h ./romcc" |
| 69 | action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" |
| 70 | end |
| 71 | |
| 72 | ## |
| 73 | ## Build our 16 bit and 32 bit linuxBIOS entry code |
| 74 | ## |
| 75 | mainboardinit cpu/x86/16bit/entry16.inc |
| 76 | mainboardinit cpu/x86/32bit/entry32.inc |
| 77 | ldscript /cpu/x86/16bit/entry16.lds |
| 78 | ldscript /cpu/x86/32bit/entry32.lds |
| 79 | |
| 80 | ## |
| 81 | ## Build our reset vector (This is where linuxBIOS is entered) |
| 82 | ## |
| 83 | if USE_FALLBACK_IMAGE |
| 84 | mainboardinit cpu/x86/16bit/reset16.inc |
| 85 | ldscript /cpu/x86/16bit/reset16.lds |
| 86 | else |
| 87 | mainboardinit cpu/x86/32bit/reset32.inc |
| 88 | ldscript /cpu/x86/32bit/reset32.lds |
| 89 | end |
| 90 | |
| 91 | ### Should this be in the northbridge code? |
| 92 | mainboardinit arch/i386/lib/cpu_reset.inc |
| 93 | |
| 94 | ## |
| 95 | ## Include an id string (For safe flashing) |
| 96 | ## |
| 97 | mainboardinit arch/i386/lib/id.inc |
| 98 | ldscript /arch/i386/lib/id.lds |
| 99 | |
| 100 | ### |
| 101 | ### This is the early phase of linuxBIOS startup |
| 102 | ### Things are delicate and we test to see if we should |
| 103 | ### failover to another image. |
| 104 | ### |
| 105 | if USE_FALLBACK_IMAGE |
| 106 | ldscript /arch/i386/lib/failover.lds |
| 107 | mainboardinit ./failover.inc |
| 108 | end |
| 109 | |
| 110 | ### |
| 111 | ### O.k. We aren't just an intermediary anymore! |
| 112 | ### |
| 113 | |
| 114 | ## |
| 115 | ## Setup RAM |
| 116 | ## |
| 117 | mainboardinit cpu/x86/fpu/enable_fpu.inc |
| 118 | mainboardinit ./auto.inc |
| 119 | |
| 120 | ## |
| 121 | ## Include the secondary Configuration files |
| 122 | ## |
| 123 | dir /pc80 |
| 124 | config chip.h |
| 125 | |
| 126 | chip northbridge/amd/gx2 |
Ronald G. Minnich | 2d7bb59 | 2006-06-18 02:28:07 +0000 | [diff] [blame] | 127 | register "irqmap" = "0xaa5b" |
Li-Ta Lo | 05c0869 | 2006-04-20 21:26:01 +0000 | [diff] [blame] | 128 | device apic_cluster 0 on |
| 129 | chip cpu/amd/model_gx2 |
| 130 | device apic 0 on end |
| 131 | end |
| 132 | end |
| 133 | device pci_domain 0 on |
| 134 | device pci 1.0 on end |
| 135 | device pci 1.1 on end |
| 136 | chip southbridge/amd/cs5536 |
Ronald G. Minnich | c01fe5d | 2006-05-03 03:30:23 +0000 | [diff] [blame] | 137 | register "enable_gpio0_inta" = "1" |
Ronald G. Minnich | 88fb1a6 | 2006-06-22 04:37:27 +0000 | [diff] [blame] | 138 | register "enable_ide_nand_flash" = "1" |
| 139 | register "enable_uarta" = "1" |
| 140 | register "audio_irq" = "5" |
| 141 | register "usbf4_irq" = "10" |
Ronald G. Minnich | 707097f | 2006-06-27 02:26:06 +0000 | [diff] [blame^] | 142 | register "usbf5_irq" = "10" |
Ronald G. Minnich | 88fb1a6 | 2006-06-22 04:37:27 +0000 | [diff] [blame] | 143 | register "usbf6_irq" = "0" |
| 144 | register "usbf7_irq" = "0" |
Li-Ta Lo | 05c0869 | 2006-04-20 21:26:01 +0000 | [diff] [blame] | 145 | device pci d.0 on end # Realtek 8139 LAN |
| 146 | device pci f.0 on end # ISA Bridge |
| 147 | device pci f.2 on end # IDE Controller |
| 148 | device pci f.3 on end # Audio |
| 149 | device pci f.4 on end # OHCI |
Ronald G. Minnich | 92e8b80 | 2006-06-24 14:46:26 +0000 | [diff] [blame] | 150 | device pci f.5 on end # UHCI |
Li-Ta Lo | 05c0869 | 2006-04-20 21:26:01 +0000 | [diff] [blame] | 151 | end |
| 152 | end |
Ronald G. Minnich | df46cb2 | 2006-04-18 16:36:58 +0000 | [diff] [blame] | 153 | end |
| 154 | |