Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Memory option API. |
| 6 | * |
| 7 | * Contains structures and values used to control the Memory option code. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: OPTION |
| 12 | * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | e963b38 | 2014-07-06 19:27:14 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _OPTION_MEMORY_H_ |
| 48 | #define _OPTION_MEMORY_H_ |
| 49 | |
| 50 | /* Memory Includes */ |
| 51 | #include "mm.h" |
| 52 | #include "mn.h" |
| 53 | #include "mt.h" |
| 54 | #include "ma.h" |
| 55 | #include "mp.h" |
| 56 | /*---------------------------------------------------------------------------------------- |
| 57 | * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) |
| 58 | *---------------------------------------------------------------------------------------- |
| 59 | */ |
| 60 | |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | #define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported |
| 67 | |
| 68 | /*---------------------------------------------------------------------------------------- |
| 69 | * T Y P E D E F S, S T R U C T U R E S, E N U M S |
| 70 | *---------------------------------------------------------------------------------------- |
| 71 | */ |
| 72 | |
| 73 | /* |
| 74 | * STANDARD MEMORY FEATURE FUNCTION POINTER |
| 75 | */ |
| 76 | |
| 77 | typedef BOOLEAN OPTION_MEM_FEATURE_NB ( |
| 78 | IN OUT MEM_NB_BLOCK *NBPtr |
| 79 | ); |
| 80 | |
| 81 | typedef BOOLEAN MEM_TECH_FEAT ( |
| 82 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 83 | ); |
| 84 | |
| 85 | typedef UINT8 MEM_TABLE_FEAT ( |
| 86 | IN OUT MEM_TABLE_ALIAS **MTPtr |
| 87 | ); |
| 88 | |
| 89 | #define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01 |
| 90 | |
| 91 | /** |
| 92 | * MEMORY FEATURE BLOCK - This structure serves as a vector table for standard |
| 93 | * memory feature implementation functions. It contains vectors for all of the |
| 94 | * features that are supported by the various Northbridge devices supported by |
| 95 | * AGESA. |
| 96 | */ |
| 97 | typedef struct _MEM_FEAT_BLOCK_NB { |
| 98 | UINT16 OptMemFeatVersion; ///< Version of memory feature block. |
| 99 | OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support. |
| 100 | OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support. |
| 101 | OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving. |
| 102 | OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support. |
| 103 | OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support. |
| 104 | OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support. |
| 105 | OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support. |
| 106 | OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support. |
| 107 | OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support. |
| 108 | OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded). |
| 109 | OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support |
| 110 | OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management |
| 111 | MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based). |
| 112 | OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm. |
| 113 | OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support. |
| 114 | OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation. |
| 115 | OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization. |
| 116 | } MEM_FEAT_BLOCK_NB; |
| 117 | |
| 118 | typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL ( |
| 119 | IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr |
| 120 | ); |
| 121 | |
| 122 | typedef BOOLEAN OPTION_MEM_FEATURE_MAIN ( |
| 123 | IN MEM_MAIN_DATA_BLOCK *MMPtr |
| 124 | ); |
| 125 | |
| 126 | typedef BOOLEAN MEM_NB_CONSTRUCTOR ( |
| 127 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 128 | IN OUT MEM_DATA_STRUCT *MemPtr, |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame^] | 129 | CONST IN MEM_FEAT_BLOCK_NB *FeatPtr, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 130 | IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad |
| 131 | IN UINT8 NodeID |
| 132 | ); |
| 133 | |
| 134 | typedef BOOLEAN MEM_TECH_CONSTRUCTOR ( |
| 135 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 136 | IN OUT MEM_NB_BLOCK *NBPtr |
| 137 | ); |
| 138 | |
| 139 | typedef VOID MEM_INITIALIZER ( |
| 140 | IN OUT MEM_DATA_STRUCT *MemPtr |
| 141 | ); |
| 142 | |
| 143 | typedef AGESA_STATUS MEM_PLATFORM_CFG ( |
| 144 | IN struct _MEM_DATA_STRUCT *MemData, |
| 145 | IN UINT8 SocketID, |
| 146 | IN CH_DEF_STRUCT *CurrentChannel |
| 147 | ); |
| 148 | |
| 149 | typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR ( |
| 150 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 151 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 152 | IN UINT8 NodeID |
| 153 | ); |
| 154 | |
| 155 | typedef VOID MEM_TECH_TRAINING_FEAT ( |
| 156 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 157 | IN UINT8 Pass |
| 158 | ); |
| 159 | |
| 160 | typedef BOOLEAN MEM_RESUME_CONSTRUCTOR ( |
| 161 | IN OUT VOID *S3NBPtr, |
| 162 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 163 | IN UINT8 NodeID |
| 164 | ); |
| 165 | |
| 166 | typedef AGESA_STATUS MEM_PLAT_SPEC_CFG ( |
| 167 | IN struct _MEM_DATA_STRUCT *MemData, |
| 168 | IN OUT CH_DEF_STRUCT *CurrentChannel, |
| 169 | IN OUT MEM_PS_BLOCK *PsPtr |
| 170 | ); |
| 171 | |
| 172 | typedef AGESA_STATUS MEM_FLOW_CFG ( |
| 173 | IN OUT MEM_MAIN_DATA_BLOCK *MemData |
| 174 | ); |
| 175 | |
| 176 | #define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01 |
| 177 | |
| 178 | /** |
| 179 | * MAIN FEATURE BLOCK - This structure serves as vector table for memory features |
| 180 | * that shared between all northbridge devices. |
| 181 | */ |
| 182 | typedef struct _MEM_FEAT_BLOCK_MAIN { |
| 183 | UINT16 OptMemFeatVersion; ///< Version of main feature block. |
| 184 | OPTION_MEM_FEATURE_MAIN *Training; ///< Training features. |
| 185 | OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm. |
| 186 | OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare. |
| 187 | OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave. |
| 188 | OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it. |
| 189 | OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear. |
| 190 | OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support. |
| 191 | OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support. |
| 192 | OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation. |
| 193 | OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save |
| 194 | OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore |
| 195 | } MEM_FEAT_BLOCK_MAIN; |
| 196 | |
| 197 | #define MEM_NB_SUPPORT_STRUCT_VERSION 0x01 |
| 198 | #define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01 |
| 199 | #define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01 |
| 200 | #define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01 |
| 201 | /** |
| 202 | * MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard |
| 203 | * memory feature implementation functions. It contains vectors for all of the |
| 204 | * features that are supported by the various Technology features supported by |
| 205 | * AGESA. |
| 206 | */ |
| 207 | typedef struct _MEM_TECH_FEAT_BLOCK { |
| 208 | UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block. |
| 209 | MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training |
| 210 | MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training |
| 211 | MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1 |
| 212 | MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1 |
| 213 | MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2 |
| 214 | MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2 |
| 215 | MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training |
| 216 | MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1 |
| 217 | MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1 |
| 218 | MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training |
| 219 | MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training |
| 220 | MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training |
| 221 | } MEM_TECH_FEAT_BLOCK; |
| 222 | |
| 223 | /** |
| 224 | * MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard |
| 225 | * memory feature implementation functions. It contains vectors for all of the |
| 226 | * features that are supported by the various LRDIMM features supported by |
| 227 | * AGESA. |
| 228 | */ |
| 229 | typedef struct _MEM_TECH_LRDIMM { |
| 230 | UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block. |
| 231 | MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization |
| 232 | } MEM_TECH_LRDIMM; |
| 233 | /** |
| 234 | * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent |
| 235 | * options together in a list to provide a single access point for all code to use |
| 236 | * and to ensure that everything corresponding to the same NB type is grouped together. |
| 237 | * |
| 238 | * The Technology Block pointers are not included in this structure because DRAM technology |
| 239 | * needs to be decoupled from the northbridge type. |
| 240 | * |
| 241 | */ |
| 242 | typedef struct _MEM_NB_SUPPORT { |
| 243 | UINT16 MemNBSupportVersion; ///< Version of northbridge support. |
| 244 | MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor. |
| 245 | MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT. |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame^] | 246 | CONST MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block. |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 247 | MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor. |
| 248 | MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification. |
| 249 | } MEM_NB_SUPPORT; |
| 250 | |
| 251 | /* |
| 252 | * MEMORY Non-Training FEATURES - This structure serves as a vector table for standard |
| 253 | * memory non-training feature implementation functions. It contains vectors for all of the |
| 254 | * features that are supported by the various Technology devices supported by |
| 255 | * AGESA. |
| 256 | */ |
| 257 | |
| 258 | /** |
| 259 | * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features |
| 260 | * that shared between all northbridge devices. |
| 261 | */ |
| 262 | typedef struct _MEM_FEAT_TRAIN_SEQ { |
| 263 | UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block. |
| 264 | OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function. |
| 265 | OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function. |
Arthur Heymans | 704ccaf | 2022-05-16 14:55:46 +0200 | [diff] [blame^] | 266 | CONST MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block. |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 267 | } MEM_FEAT_TRAIN_SEQ; |
| 268 | |
| 269 | /** |
| 270 | * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table |
| 271 | * entries which are used by PSC engine |
| 272 | */ |
| 273 | typedef struct _MEM_PSC_TABLE_BLOCK { |
| 274 | PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq. |
| 275 | PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term. |
| 276 | PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern. |
| 277 | PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC.. |
| 278 | PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR]. |
| 279 | PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL]. |
| 280 | PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT. |
| 281 | PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed]. |
| 282 | PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT |
| 283 | PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks]. |
| 284 | PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks]. |
| 285 | PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map. |
| 286 | } MEM_PSC_TABLE_BLOCK; |
| 287 | |
| 288 | typedef BOOLEAN MEM_PSC_FLOW ( |
| 289 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 290 | IN MEM_PSC_TABLE_BLOCK *EntryOfTables |
| 291 | ); |
| 292 | |
| 293 | /** |
| 294 | * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform |
| 295 | * specific configuration. |
| 296 | */ |
| 297 | typedef struct _MEM_PSC_FLOW_BLOCK { |
| 298 | MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK |
| 299 | MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction. |
| 300 | MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction. |
| 301 | MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction. |
| 302 | MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction. |
| 303 | MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction. |
| 304 | MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction. |
| 305 | MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction. |
| 306 | MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction. |
| 307 | MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction. |
| 308 | MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction. |
| 309 | } MEM_PSC_FLOW_BLOCK; |
| 310 | |
| 311 | /*---------------------------------------------------------------------------------------- |
| 312 | * F U N C T I O N P R O T O T Y P E |
| 313 | *---------------------------------------------------------------------------------------- |
| 314 | */ |
| 315 | /* Feature Default Return */ |
| 316 | BOOLEAN MemFDefRet ( |
| 317 | IN OUT MEM_NB_BLOCK *NBPtr |
| 318 | ); |
| 319 | |
| 320 | BOOLEAN MemMDefRet ( |
| 321 | IN MEM_MAIN_DATA_BLOCK *MMPtr |
| 322 | ); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 323 | |
| 324 | BOOLEAN MemMDefRetFalse ( |
| 325 | IN MEM_MAIN_DATA_BLOCK *MMPtr |
| 326 | ); |
| 327 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 328 | /* Table Feature Default Return */ |
| 329 | UINT8 MemFTableDefRet ( |
| 330 | IN OUT MEM_TABLE_ALIAS **MTPtr |
| 331 | ); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame] | 332 | |
| 333 | BOOLEAN MemNIdentifyDimmConstructorRetDef ( |
| 334 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 335 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 336 | IN UINT8 NodeID |
| 337 | ); |
| 338 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 339 | /* S3 Feature Default Return */ |
| 340 | BOOLEAN MemFS3DefConstructorRet ( |
| 341 | IN OUT VOID *S3NBPtr, |
| 342 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 343 | IN UINT8 NodeID |
| 344 | ); |
| 345 | |
| 346 | BOOLEAN |
| 347 | MemProcessConditionalOverrides ( |
| 348 | IN PSO_TABLE *PlatformMemoryConfiguration, |
| 349 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 350 | IN UINT8 PsoAction, |
| 351 | IN UINT8 Dimm |
| 352 | ); |
| 353 | |
| 354 | #endif // _OPTION_MEMORY_H_ |