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review.coreboot.org / coreboot / 6f9fcc64a170ec4348811dcb1cead2b1bcf2e3a0 / . / src / mainboard / facebook / fbg1701 / ramstage.c
blob: 3903a6474e63fcb2bd97185fcaa95fbc094b24a6 [file] [log] [blame]
Frans Hendriks43b6e2e2019-06-04 13:53:05 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
Frans Hendriks6f9fcc62019-06-21 09:48:48 +0200[diff] [blame^]4 * Copyright (C) 2018-2019 Facebook, Inc
Frans Hendriks43b6e2e2019-06-04 13:53:05 +0200[diff] [blame]5 * Copyright (C) 2018-2019 Eltan B.V.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Frans Hendriks6f9fcc62019-06-21 09:48:48 +0200[diff] [blame^]17#include <arch/io.h>
18#include <console/console.h>
Frans Hendriks43b6e2e2019-06-04 13:53:05 +0200[diff] [blame]19#include <soc/ramstage.h>
Frans Hendriks6f9fcc62019-06-21 09:48:48 +0200[diff] [blame^]20#include <soc/smbus.h>
Frans Hendriks43b6e2e2019-06-04 13:53:05 +0200[diff] [blame]21#include "mainboard.h"
Frans Hendriks6f9fcc62019-06-21 09:48:48 +0200[diff] [blame^]22#include "onboard.h"
23
24struct edp_data {
25 u8 payload_length;
26 u8 address;
27 /* data: reg[15:8],reg[7:0], data bytes starting with data[7:0] */
28 u8 data[6];
29} __packed;
30
31static const struct edp_data tc348860_table[] = {
32 /* set eDP bridge to eDP 1920 */
33 /* IO */
34 { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } },
35 /* Boot */
36 { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } },
37 { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } },
38 { 6, 0x68, { 0x10, 0x08, 0x23, 0x00, 0x87, 0x02 } },
39 { 6, 0x68, { 0x10, 0x0C, 0x19, 0x04, 0x00, 0x23 } },
40 { 6, 0x68, { 0x10, 0x10, 0x06, 0x00, 0x67, 0x00 } },
41 { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } },
42 { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } },
43 /* Internal */
44 { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } },
45 { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } },
46 { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } },
47 { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } },
48 { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } },
49 { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } },
50 { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } },
51 { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } },
52 /* eDP */
53 { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } },
54 { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } },
55 /* DPRX */
56 { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } },
57 { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } },
58 { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } },
59 { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } },
60 { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } },
61 { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } },
62 { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } },
63 { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } },
64 { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } },
65 { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } },
66 { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } },
67 { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } },
68 { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } },
69 { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } },
70 { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } },
71 { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } },
72 { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } },
73 { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } },
74 { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } },
75 { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } },
76 { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } },
77 { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } },
78 { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } },
79 { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } },
80 { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } },
81 { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } },
82 { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } },
83 { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } },
84 { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } },
85 { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } },
86 { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } },
87 { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } },
88 { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } },
89 { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } },
90 { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } },
91 { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } },
92 { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } },
93 { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } },
94 { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } },
95 { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } },
96 { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } },
97 { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } },
98 { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } },
99 { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } },
100 { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } },
101 { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } },
102 { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } },
103 { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } },
104 { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } },
105 { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } },
106 { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } },
107 { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } },
108 { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } },
109 { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } },
110 { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } },
111 { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } },
112 { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } },
113 { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } },
114 { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } },
115 { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } },
116 { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } },
117 { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } },
118 { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } },
119 { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } },
120 /* Video size */
121 { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } },
122 { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } },
123 /* eDP */
124 { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } },
125 { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } },
126 { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } },
127 { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } },
128 { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } },
129 { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } },
130 { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } },
131 { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } },
132 { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } },
133 /* Link Training */
134 { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } },
135 { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } },
136 { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } },
137 { 6, 0x68, { 0x21, 0x58, 0x09, 0x00, 0x28, 0x00 } },
138 { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x0F, 0x00 } },
139 { 6, 0x68, { 0x21, 0x64, 0x28, 0x23, 0x00, 0x00 } },
140 { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } },
141 /* DSI */
142 { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } },
143 { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } },
144 { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } },
145 { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } },
146 /* GPIO */
147 { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } },
148 { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } },
149 { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } },
150 { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } },
151 { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } },
152 /* DSI clock */
153 { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } },
154 /* LCD init */
155 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } },
156 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81 } },
157 { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81 } },
158 { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81 } },
159 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x85, 0x04, 0x81 } },
160 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x86, 0x08, 0x81 } },
161 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } },
162 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } },
163 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81 } },
164 { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81 } },
165 { 6, 0x68, { 0x22, 0xFC, 0x05, 0x11, 0x00, 0x81 } },
166 { 6, 0x68, { 0x22, 0xFC, 0x05, 0x29, 0x00, 0x81 } },
167 { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } },
168 { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } },
169 /* Check Video */
170 { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } },
171 /* End of table */
172 { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } },
173};
174
175static const struct edp_data b101uan08_table[] = {
176 /* set eDP bridge to eDP 1920 */
177 /* IO Voltage Setting */
178 { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } },
179 /* Boot Settings */
180 { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } },
181 { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } },
182 { 6, 0x68, { 0x10, 0x08, 0x22, 0x00, 0xA0, 0x02 } },
183 { 6, 0x68, { 0x10, 0x0C, 0x50, 0x04, 0x00, 0x03 } },
184 { 6, 0x68, { 0x10, 0x10, 0x10, 0x0D, 0x06, 0x01 } },
185 { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } },
186 { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } },
187 /* Internal PCLK settings for Non Present or REFCLK=26MHz */
188 { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } },
189 { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } },
190 { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } },
191 { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } },
192 { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } },
193 { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } },
194 /* DSI Clock setting for Non Preset or REFCLK=26MHz */
195 { 6, 0x68, { 0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00 } },
196 { 6, 0x68, { 0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00 } },
197 { 6, 0x68, { 0x41, 0xC0, 0x30, 0x00, 0x00, 0x00 } },
198 { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } },
199 { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } },
200 /* Additional Settng for eDP */
201 { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } },
202 { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } },
203 /* DPRX CAD Register Setting */
204 { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } },
205 { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } },
206 { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } },
207 { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } },
208 { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } },
209 { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } },
210 { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } },
211 { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } },
212 { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } },
213 { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } },
214 { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } },
215 { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } },
216 { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } },
217 { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } },
218 { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } },
219 { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } },
220 { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } },
221 { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } },
222 { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } },
223 { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } },
224 { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } },
225 { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } },
226 { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } },
227 { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } },
228 { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } },
229 { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } },
230 { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } },
231 { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } },
232 { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } },
233 { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } },
234 { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } },
235 { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } },
236 { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } },
237 { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } },
238 { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } },
239 { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } },
240 { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } },
241 { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } },
242 { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } },
243 { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } },
244 { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } },
245 { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } },
246 { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } },
247 { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } },
248 { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } },
249 { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } },
250 { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } },
251 { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } },
252 { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } },
253 { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } },
254 { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } },
255 { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } },
256 { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } },
257 { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } },
258 { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } },
259 { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } },
260 { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } },
261 { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } },
262 { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } },
263 { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } },
264 { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } },
265 { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } },
266 { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } },
267 { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } },
268 /* Video size Related Settings for Non Present */
269 { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } },
270 { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } },
271 /* eDP Settings for Link Training*/
272 { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } },
273 { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } },
274 { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } },
275 { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } },
276 { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } },
277 { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } },
278 { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } },
279 { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } },
280 { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } },
281 /* Link Training */
282 { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } },
283 { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } },
284 { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } },
285 /* DSI Transition Time Setting for Non Preset */
286 { 6, 0x68, { 0x21, 0x54, 0x0D, 0x00, 0x00, 0x00 } },
287 { 6, 0x68, { 0x21, 0x58, 0x06, 0x00, 0x2A, 0x00 } },
288 { 6, 0x68, { 0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00 } },
289 { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x10, 0x00 } },
290 { 6, 0x68, { 0x21, 0x64, 0x10, 0x27, 0x00, 0x00 } },
291 { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } },
292 { 6, 0x68, { 0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00 } },
293 { 6, 0x68, { 0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00 } },
294 /* DSI Start */
295 { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } },
296 { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } },
297 { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } },
298 { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } },
299 /* GPIO for LCD control*/
300 { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } },
301 { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } },
302 { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } },
303 { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } },
304 { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } },
305 /* DSI Hs Clock Mode */
306 { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } },
307 /* LCD Initialization */
308 { 6, 0x68, { 0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81 } },
309 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } },
310 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81 } },
311 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } },
312 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } },
313 { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81 } },
314 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0x00, 0x81 } },
315 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x00, 0x81 } },
316 { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81 } },
317 { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } },
318 { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } },
319 /* Check if eDP video is coming */
320 { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } },
321 /* End of table */
322 { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } },
323};
324
325static void mainboard_configure_edp_bridge(void)
326{
327 u8 cpld_version;
328 const struct edp_data *edptable;
329 unsigned int loops;
330 int status;
331
332 cpld_version = (inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >>
333 CPLD_PCB_VERSION_BIT;
334 printk(BIOS_DEBUG, "CPLD version: %x\n", cpld_version);
335 if (cpld_version < 7)
336 edptable = tc348860_table;
337 else
338 edptable = b101uan08_table;
339
340 /* reset bridge */
341 outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT);
342 outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT);
343
344 /* set eDP bridge to eDP 1920 */
345 while (edptable->payload_length) {
346 loops = 5;
347 do {
348 status = smbus_i2c_block_write(edptable->address,
349 edptable->payload_length,
350 (u8 *)&edptable->data[0]);
351 } while (--loops && (status < 0));
352
353 if (loops == 0) {
354 printk(BIOS_ERR, "Writing eDP bridge failed!\n");
355 return;
356 }
357 edptable++;
358 };
359}
Frans Hendriks43b6e2e2019-06-04 13:53:05 +0200[diff] [blame]360
361void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
362{
Frans Hendriks6f9fcc62019-06-21 09:48:48 +0200[diff] [blame^]363 /* Configure the eDP bridge to eDP 1920 */
364 mainboard_configure_edp_bridge();
365
Frans Hendriks43b6e2e2019-06-04 13:53:05 +0200[diff] [blame]366 if (CONFIG(FSP1_1_DISPLAY_LOGO)) {
367 size_t logo_len;
368 void *logo = NULL;
369
370 logo = load_logo(&logo_len);
371
372 if (logo) {
373 params->PcdLogoPtr = (u32)logo;
374 params->PcdLogoSize = logo_len;
375 }
376 }
377}