Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 4 | * Copyright (C) 2016-2017 Intel Corp. |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 16 | #include <arch/early_variables.h> |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 17 | #include <console/console.h> |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 18 | #include <cbfs.h> |
| 19 | #include <cbmem.h> |
| 20 | #include "../chip.h" |
| 21 | #include <cpu/x86/cache.h> |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 22 | #include <fsp/util.h> |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/pm.h> |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 25 | #include <soc/romstage.h> |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 26 | #include <soc/reg_access.h> |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 27 | |
| 28 | asmlinkage void *car_stage_c_entry(void) |
| 29 | { |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 30 | struct postcar_frame pcf; |
| 31 | bool s3wake; |
| 32 | uintptr_t top_of_ram; |
| 33 | uintptr_t top_of_low_usable_memory; |
| 34 | |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 35 | post_code(0x20); |
| 36 | console_init(); |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 37 | |
| 38 | /* Initialize DRAM */ |
| 39 | s3wake = fill_power_state() == ACPI_S3; |
| 40 | fsp_memory_init(s3wake); |
| 41 | |
| 42 | /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ |
| 43 | disable_rom_shadow(); |
| 44 | |
| 45 | /* Initialize the PCIe bridges */ |
| 46 | pcie_init(); |
| 47 | |
| 48 | if (postcar_frame_init(&pcf, 1*KiB)) |
| 49 | die("Unable to initialize postcar frame.\n"); |
| 50 | |
| 51 | /* Locate the top of RAM */ |
| 52 | top_of_low_usable_memory = (uintptr_t) cbmem_top(); |
| 53 | top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); |
| 54 | |
| 55 | /* Cache postcar and ramstage */ |
| 56 | postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB, |
| 57 | MTRR_TYPE_WRBACK); |
| 58 | |
| 59 | /* Cache RMU area */ |
| 60 | postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory, |
| 61 | 0x10000, MTRR_TYPE_WRTHROUGH); |
| 62 | |
| 63 | /* Cache ESRAM */ |
| 64 | postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); |
| 65 | |
| 66 | /* Cache SPI flash - Write protect not supported */ |
| 67 | postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE), |
| 68 | CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH); |
| 69 | |
| 70 | run_postcar_phase(&pcf); |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 71 | return NULL; |
| 72 | } |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 73 | |
| 74 | static struct chipset_power_state power_state CAR_GLOBAL; |
| 75 | |
| 76 | struct chipset_power_state *get_power_state(void) |
| 77 | { |
| 78 | return (struct chipset_power_state *)car_get_var_ptr(&power_state); |
| 79 | } |
| 80 | |
| 81 | int fill_power_state(void) |
| 82 | { |
| 83 | struct chipset_power_state *ps = get_power_state(); |
| 84 | |
| 85 | ps->prev_sleep_state = 0; |
| 86 | printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 87 | return ps->prev_sleep_state; |
| 88 | } |
| 89 | |
Andrey Petrov | f796c6e | 2016-11-18 14:57:51 -0800 | [diff] [blame] | 90 | void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 91 | { |
Lee Leahy | 44ec92a | 2016-09-28 17:16:44 -0700 | [diff] [blame] | 92 | FSPM_ARCH_UPD *aupd; |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 93 | const struct device *dev; |
| 94 | const struct soc_intel_quark_config *config; |
| 95 | char *rmu_file; |
| 96 | size_t rmu_file_len; |
Lee Leahy | 44ec92a | 2016-09-28 17:16:44 -0700 | [diff] [blame] | 97 | FSP_M_CONFIG *upd; |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 98 | |
| 99 | /* Clear SMI and wake events */ |
| 100 | clear_smi_and_wake_events(); |
| 101 | |
| 102 | /* Locate the RMU data file in flash */ |
| 103 | rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, |
| 104 | &rmu_file_len); |
| 105 | if (!rmu_file) |
| 106 | die("Microcode file (rmu.bin) not found."); |
| 107 | |
| 108 | /* Locate the configuration data from devicetree.cb */ |
| 109 | dev = dev_find_slot(0, LPC_DEV_FUNC); |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 110 | if (!dev) |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 111 | die("ERROR - LPC device not found!"); |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 112 | config = dev->chip_info; |
| 113 | |
| 114 | /* Update the architectural UPD values. */ |
| 115 | aupd = &fspm_upd->FspmArchUpd; |
| 116 | aupd->BootLoaderTolumSize = cbmem_overhead_size(); |
| 117 | aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); |
| 118 | aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; |
| 119 | |
| 120 | /* Display the ESRAM layout */ |
| 121 | if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { |
| 122 | printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); |
| 123 | printk(BIOS_SPEW, |
| 124 | "+-------------------+ 0x80080000 - ESRAM end\n"); |
| 125 | printk(BIOS_SPEW, "| FSP binary |\n"); |
| 126 | printk(BIOS_SPEW, |
| 127 | "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", |
| 128 | CONFIG_FSP_ESRAM_LOC); |
| 129 | printk(BIOS_SPEW, "| FSP stack |\n"); |
| 130 | printk(BIOS_SPEW, "+-------------------+ 0x%p\n", |
| 131 | aupd->StackBase); |
| 132 | printk(BIOS_SPEW, "| |\n"); |
| 133 | printk(BIOS_SPEW, "+-------------------+ 0x%p\n", |
| 134 | _car_relocatable_data_end); |
| 135 | printk(BIOS_SPEW, "| coreboot data |\n"); |
| 136 | printk(BIOS_SPEW, "+-------------------+ 0x%p\n", |
| 137 | _car_stack_end); |
| 138 | printk(BIOS_SPEW, "| coreboot stack |\n"); |
| 139 | printk(BIOS_SPEW, |
| 140 | "+-------------------+ 0x80000000 - ESRAM start\n\n"); |
| 141 | } |
| 142 | |
| 143 | /* Update the UPD data for MemoryInit */ |
| 144 | upd = &fspm_upd->FspmConfig; |
| 145 | upd->AddrMode = config->AddrMode; |
| 146 | upd->ChanMask = config->ChanMask; |
| 147 | upd->ChanWidth = config->ChanWidth; |
| 148 | upd->DramDensity = config->DramDensity; |
| 149 | upd->DramRonVal = config->DramRonVal; |
| 150 | upd->DramRttNomVal = config->DramRttNomVal; |
| 151 | upd->DramRttWrVal = config->DramRttWrVal; |
| 152 | upd->DramSpeed = config->DramSpeed; |
| 153 | upd->DramType = config->DramType; |
| 154 | upd->DramWidth = config->DramWidth; |
| 155 | upd->EccScrubBlkSize = config->EccScrubBlkSize; |
| 156 | upd->EccScrubInterval = config->EccScrubInterval; |
| 157 | upd->Flags = config->Flags; |
| 158 | upd->FspReservedMemoryLength = config->FspReservedMemoryLength; |
| 159 | upd->RankMask = config->RankMask; |
| 160 | upd->RmuBaseAddress = (uintptr_t)rmu_file; |
| 161 | upd->RmuLength = rmu_file_len; |
Lee Leahy | 5e07a7e | 2016-08-06 09:51:35 -0700 | [diff] [blame] | 162 | upd->SerialPortWriteChar = console_log_level(BIOS_SPEW) |
| 163 | ? (uintptr_t)fsp_write_line : 0; |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 164 | upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? |
| 165 | config->SmmTsegSize : 0; |
| 166 | upd->SocRdOdtVal = config->SocRdOdtVal; |
| 167 | upd->SocWrRonVal = config->SocWrRonVal; |
| 168 | upd->SocWrSlewRate = config->SocWrSlewRate; |
| 169 | upd->SrInt = config->SrInt; |
| 170 | upd->SrTemp = config->SrTemp; |
| 171 | upd->tCL = config->tCL; |
| 172 | upd->tFAW = config->tFAW; |
| 173 | upd->tRAS = config->tRAS; |
| 174 | upd->tRRD = config->tRRD; |
| 175 | upd->tWTR = config->tWTR; |
| 176 | } |