Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
| 7 | # FSP configuration |
| 8 | |
| 9 | register "SataMode" = "0" # AHCI |
| 10 | register "SataSalpSupport" = "0" |
| 11 | register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1 |
| 12 | |
| 13 | register "SataPortsEnable[0]" = "1" |
| 14 | register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1 |
| 15 | register "SataPortsEnable[2]" = "0" # Not used for SATA |
| 16 | register "SataPortsEnable[3]" = "0" # Not used for SATA |
| 17 | register "SataPortsEnable[4]" = "1" |
| 18 | register "SataPortsEnable[5]" = "1" |
| 19 | register "SataPortsEnable[6]" = "1" |
| 20 | register "SataPortsEnable[7]" = "1" |
| 21 | |
Jonas Loeffelholz | 72afe02 | 2020-06-25 15:00:33 +0200 | [diff] [blame] | 22 | register "SataPortsHotPlug[0]" = "1" |
| 23 | register "SataPortsHotPlug[1]" = "1" |
| 24 | register "SataPortsHotPlug[2]" = "0" |
| 25 | register "SataPortsHotPlug[3]" = "0" |
| 26 | register "SataPortsHotPlug[4]" = "1" |
| 27 | register "SataPortsHotPlug[5]" = "1" |
| 28 | register "SataPortsHotPlug[6]" = "1" |
| 29 | register "SataPortsHotPlug[7]" = "1" |
| 30 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 31 | register "PchHdaDspEnable" = "0" |
| 32 | register "PchHdaAudioLinkHda" = "1" |
| 33 | |
| 34 | # Enumeration starts at 0 for PCIE1 |
| 35 | # Ports are not hotplugable |
| 36 | register "PcieRpEnable[0]" = "1" # Slot3 x4 |
Elyes HAOUAS | bda27cd | 2020-06-27 07:17:16 +0200 | [diff] [blame] | 37 | # Set MaxPayload to 256 bytes |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 38 | register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" |
| 39 | # Enable Latency Tolerance Reporting Mechanism |
| 40 | register "PcieRpLtrEnable[0]" = "1" |
| 41 | # Enable Advanced Error Reporting |
| 42 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 43 | # Disable Aspm |
| 44 | register "PcieRpAspm[0]" = "AspmDisabled" |
| 45 | |
| 46 | |
| 47 | register "PcieRpEnable[4]" = "1" # PHY ETH3 |
| 48 | register "PcieRpEnable[5]" = "1" # PHY ETH4 |
| 49 | register "PcieRpEnable[6]" = "1" # PHY ETH2 |
| 50 | register "PcieRpEnable[7]" = "1" # PHY ETH1 |
| 51 | register "PcieRpEnable[8]" = "1" # M2 Slot M x4, depends on SATAXPCIE1 |
| 52 | register "PcieRpEnable[13]" = "1" # PHY ETH0 |
| 53 | register "PcieRpEnable[14]" = "1" # BMC |
| 54 | register "PcieRpEnable[15]" = "1" # M2 Slot E x1 |
| 55 | register "PcieRpEnable[20]" = "1" # Slot 1 x4 |
| 56 | # Set MaxPayload to 256 bytes |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame] | 57 | register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" |
| 58 | # Enable Latency Tolerance Reporting Mechanism |
| 59 | register "PcieRpLtrEnable[20]" = "1" |
| 60 | # Enable Advanced Error Reporting |
| 61 | register "PcieRpAdvancedErrorReporting[20]" = "1" |
| 62 | # Disable Aspm |
| 63 | register "PcieRpAspm[20]" = "AspmDisabled" |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 64 | |
| 65 | # Controls the CLKREQ, not the output directly. |
| 66 | # Depends on the CLKREQ to CLK gen mapping below |
| 67 | register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # BMC, PCIe Slot1, Slot2, Slot4, Slot6 |
| 68 | register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PHY3 |
| 69 | register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" |
| 70 | register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" |
| 71 | register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4 |
| 72 | register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1 |
| 73 | register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" |
| 74 | register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" |
| 75 | register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED" |
| 76 | register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED" |
| 77 | register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED" |
| 78 | register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED" |
| 79 | register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED" |
| 80 | register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PHY 0, PHY 1, PHY 2, PHY 4 |
| 81 | register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE" # PB |
| 82 | register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE" # PCIe Slot3 |
| 83 | |
| 84 | # Only map M2 CLKREQ to CLK gen |
| 85 | register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n |
| 86 | register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n |
| 87 | |
| 88 | # USB Config 2.0/3.0 |
| 89 | # Enumeration starts at 0 |
| 90 | # USB 3.0 |
| 91 | # USB OC0: RP1 |
| 92 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" |
| 93 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" |
| 94 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" |
| 95 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" |
| 96 | |
| 97 | # USB OC1: RP2 |
| 98 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" |
| 99 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" |
| 100 | register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" |
| 101 | register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC1)" |
| 102 | |
| 103 | # USB OC2: Internal Header CN_USB3_HDR |
| 104 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" |
| 105 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" |
| 106 | register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC2)" |
| 107 | register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC2)" |
| 108 | |
| 109 | # USB 2.0 |
| 110 | # USB OC3: Internal Header USB2_HDR1 |
| 111 | register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" |
| 112 | register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" |
| 113 | |
| 114 | # USB OC4: Internal Header USB2_HDR2 |
| 115 | register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" |
| 116 | register "usb2_ports[9]" = "USB2_PORT_MID(OC4)" |
| 117 | |
| 118 | # USB OC5-7: not connected |
| 119 | # BMC |
| 120 | register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 121 | # piggy-back |
| 122 | register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" |
| 123 | # M2 key E |
| 124 | register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" |
| 125 | |
| 126 | # Thermal |
Patrick Rudolph | b5f580e | 2020-10-29 12:25:44 +0100 | [diff] [blame] | 127 | register "tcc_offset" = "1" # TCC of 99C |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 128 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 129 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 130 | # Disable S0ix |
| 131 | register "s0ix_enable" = "0" |
| 132 | |
Christian Walter | 23cdcb8 | 2020-06-24 18:32:21 +0200 | [diff] [blame] | 133 | # Enable Turbo |
| 134 | register "eist_enable" = "1" |
| 135 | |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 136 | register "common_soc_config" = "{ |
| 137 | .gspi[0] = { |
| 138 | .speed_mhz = 1, |
| 139 | .early_init = 1, |
| 140 | }, |
| 141 | }" |
| 142 | |
| 143 | # VR Power Delivery Design |
| 144 | register "VrPowerDeliveryDesign" = "0x12" |
| 145 | |
| 146 | register "SerialIoDevMode" = "{ |
| 147 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 148 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 149 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 150 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 151 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 152 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 153 | [PchSerialIoIndexSPI0] = PchSerialIoPci, |
| 154 | [PchSerialIoIndexSPI1] = PchSerialIoDisabled, |
| 155 | [PchSerialIoIndexUART0] = PchSerialIoPci, |
| 156 | [PchSerialIoIndexUART1] = PchSerialIoPci, |
| 157 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 158 | }" |
| 159 | |
| 160 | register "DisableHeciRetry" = "1" |
| 161 | |
| 162 | |
| 163 | device domain 0 on |
Patrick Rudolph | 6e98292 | 2020-11-03 19:23:34 +0100 | [diff] [blame^] | 164 | device pci 02.0 on end # Integrated Graphics Device |
Furquan Shaikh | edac4ef | 2020-10-09 08:50:14 -0700 | [diff] [blame] | 165 | device pci 14.3 on |
| 166 | chip drivers/wifi/generic |
| 167 | register "wake" = "PME_B0_EN_BIT" |
| 168 | device generic 0 on end |
| 169 | end |
| 170 | end # CNVi wifi |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 171 | |
Christian Walter | 2276ffa | 2020-07-15 13:04:40 +0200 | [diff] [blame] | 172 | # This device does not have any function on CNP-H, but it needs |
| 173 | # to be here so that the resource allocator is aware of UART 2. |
| 174 | device pci 19.0 hidden end |
Patrick Rudolph | 7bcef3a | 2020-08-12 07:38:01 +0200 | [diff] [blame] | 175 | chip soc/intel/common/block/uart |
| 176 | device pci 19.2 hidden |
| 177 | register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" |
| 178 | end # UART #2, in ACPI mode |
| 179 | end |
Felix Singer | 2b9035e | 2020-08-18 23:12:55 +0200 | [diff] [blame] | 180 | device pci 1b.4 on # PCIe root port 21 (Slot 1) |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 181 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 182 | register "PcieRpSlotImplemented[20]" = "1" |
Felix Singer | 2b9035e | 2020-08-18 23:12:55 +0200 | [diff] [blame] | 183 | end |
| 184 | device pci 1c.0 on # PCIe root port 1 (Slot 3) |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 185 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 186 | register "PcieRpSlotImplemented[0]" = "1" |
Felix Singer | 2b9035e | 2020-08-18 23:12:55 +0200 | [diff] [blame] | 187 | end |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 188 | device pci 1c.4 on # PCIe root port 5 (PHY 3) |
| 189 | register "PcieRpSlotImplemented[4]" = "1" |
| 190 | end |
| 191 | device pci 1c.5 on # PCIe root port 6 (PHY 4) |
| 192 | register "PcieRpSlotImplemented[5]" = "1" |
| 193 | end |
| 194 | device pci 1c.6 on # PCIe root port 7 (PHY 2) |
| 195 | register "PcieRpSlotImplemented[6]" = "1" |
| 196 | end |
| 197 | device pci 1c.7 on # PCIe root port 8 (PHY 1) |
| 198 | register "PcieRpSlotImplemented[7]" = "1" |
| 199 | end |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 200 | |
Felix Singer | 2b9035e | 2020-08-18 23:12:55 +0200 | [diff] [blame] | 201 | device pci 1d.0 on # PCIe root port 9 (M2 M) |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 202 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 203 | register "PcieRpSlotImplemented[8]" = "1" |
Felix Singer | 2b9035e | 2020-08-18 23:12:55 +0200 | [diff] [blame] | 204 | end |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 205 | device pci 1d.5 on # PCIe root port 14 (PHY 0) |
| 206 | register "PcieRpSlotImplemented[13]" = "1" |
| 207 | end |
| 208 | device pci 1d.6 on # PCIe root port 15 (BMC) |
| 209 | register "PcieRpSlotImplemented[14]" = "1" |
| 210 | end |
Christian Walter | b646e28 | 2020-01-09 15:42:42 +0100 | [diff] [blame] | 211 | |
| 212 | device pci 1e.0 on end # UART #0 |
| 213 | device pci 1e.1 on end # UART #1 |
| 214 | device pci 1e.2 off end # GSPI #0 |
| 215 | device pci 1e.3 off end # GSPI #1 |
| 216 | |
| 217 | end |
| 218 | end |