Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 2 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 3 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
| 5 | #include <acpi/acpigen.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 6 | #include <arch/cpu.h> |
| 7 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 8 | #include <cpu/intel/speedstep.h> |
| 9 | #include <cpu/intel/turbo.h> |
| 10 | #include <device/device.h> |
Elyes HAOUAS | 7cf1f20 | 2020-07-22 07:53:53 +0200 | [diff] [blame] | 11 | #include <stdint.h> |
| 12 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 13 | #include "model_206ax.h" |
| 14 | #include "chip.h" |
| 15 | |
Angel Pons | 85790d0 | 2021-01-21 21:12:27 +0100 | [diff] [blame] | 16 | /* |
| 17 | * List of supported C-states in this processor |
| 18 | * |
| 19 | * Latencies are typical worst-case package exit time in uS |
| 20 | * taken from the SandyBridge BIOS specification. |
| 21 | */ |
| 22 | static const acpi_cstate_t cstate_map[] = { |
| 23 | { /* 0: C0 */ |
| 24 | }, { /* 1: C1 */ |
| 25 | .latency = 1, |
| 26 | .power = 1000, |
| 27 | .resource = { |
| 28 | .addrl = 0x00, /* MWAIT State 0 */ |
| 29 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 30 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 31 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 32 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 33 | } |
| 34 | }, |
| 35 | { /* 2: C1E */ |
| 36 | .latency = 1, |
| 37 | .power = 1000, |
| 38 | .resource = { |
| 39 | .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ |
| 40 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 41 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 42 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 43 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 44 | } |
| 45 | }, |
| 46 | { /* 3: C3 */ |
| 47 | .latency = 63, |
| 48 | .power = 500, |
| 49 | .resource = { |
| 50 | .addrl = 0x10, /* MWAIT State 1 */ |
| 51 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 52 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 53 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 54 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 55 | } |
| 56 | }, |
| 57 | { /* 4: C6 */ |
| 58 | .latency = 87, |
| 59 | .power = 350, |
| 60 | .resource = { |
| 61 | .addrl = 0x20, /* MWAIT State 2 */ |
| 62 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 63 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 64 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 65 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 66 | } |
| 67 | }, |
| 68 | { /* 5: C7 */ |
| 69 | .latency = 90, |
| 70 | .power = 200, |
| 71 | .resource = { |
| 72 | .addrl = 0x30, /* MWAIT State 3 */ |
| 73 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 74 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 75 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 76 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 77 | } |
| 78 | }, |
| 79 | { /* 6: C7S */ |
| 80 | .latency = 90, |
| 81 | .power = 200, |
| 82 | .resource = { |
| 83 | .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ |
| 84 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 85 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 86 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 87 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 88 | } |
| 89 | }, |
| 90 | }; |
| 91 | |
Evgeny Zinoviev | 920d2b7 | 2020-06-16 08:23:09 +0300 | [diff] [blame] | 92 | static int get_logical_cores_per_package(void) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 93 | { |
Evgeny Zinoviev | 920d2b7 | 2020-06-16 08:23:09 +0300 | [diff] [blame] | 94 | msr_t msr = rdmsr(MSR_CORE_THREAD_COUNT); |
| 95 | return msr.lo & 0xffff; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 96 | } |
| 97 | |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 98 | static void generate_C_state_entries(void) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 99 | { |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 100 | struct device *lapic; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 101 | struct cpu_intel_model_206ax_config *conf = NULL; |
| 102 | |
| 103 | /* Find the SpeedStep CPU in the device tree using magic APIC ID */ |
| 104 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 105 | if (!lapic) |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 106 | return; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 107 | conf = lapic->chip_info; |
| 108 | if (!conf) |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 109 | return; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 110 | |
Angel Pons | d8b9e56 | 2021-01-04 17:37:46 +0100 | [diff] [blame] | 111 | const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; |
| 112 | |
| 113 | acpi_cstate_t acpi_cstate_map[ARRAY_SIZE(acpi_cstates)] = { 0 }; |
| 114 | |
| 115 | /* Count number of active C-states */ |
| 116 | int count = 0; |
| 117 | |
| 118 | for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) { |
Angel Pons | 85790d0 | 2021-01-21 21:12:27 +0100 | [diff] [blame] | 119 | if (acpi_cstates[i] > 0 && acpi_cstates[i] < ARRAY_SIZE(cstate_map)) { |
| 120 | acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; |
Angel Pons | d8b9e56 | 2021-01-04 17:37:46 +0100 | [diff] [blame] | 121 | acpi_cstate_map[count].ctype = i + 1; |
| 122 | count++; |
| 123 | } |
| 124 | } |
| 125 | acpigen_write_CST_package(acpi_cstate_map, count); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | static acpi_tstate_t tss_table_fine[] = { |
| 129 | { 100, 1000, 0, 0x00, 0 }, |
| 130 | { 94, 940, 0, 0x1f, 0 }, |
| 131 | { 88, 880, 0, 0x1e, 0 }, |
| 132 | { 82, 820, 0, 0x1d, 0 }, |
| 133 | { 75, 760, 0, 0x1c, 0 }, |
| 134 | { 69, 700, 0, 0x1b, 0 }, |
| 135 | { 63, 640, 0, 0x1a, 0 }, |
| 136 | { 57, 580, 0, 0x19, 0 }, |
| 137 | { 50, 520, 0, 0x18, 0 }, |
| 138 | { 44, 460, 0, 0x17, 0 }, |
| 139 | { 38, 400, 0, 0x16, 0 }, |
| 140 | { 32, 340, 0, 0x15, 0 }, |
| 141 | { 25, 280, 0, 0x14, 0 }, |
| 142 | { 19, 220, 0, 0x13, 0 }, |
| 143 | { 13, 160, 0, 0x12, 0 }, |
| 144 | }; |
| 145 | |
| 146 | static acpi_tstate_t tss_table_coarse[] = { |
| 147 | { 100, 1000, 0, 0x00, 0 }, |
| 148 | { 88, 875, 0, 0x1f, 0 }, |
| 149 | { 75, 750, 0, 0x1e, 0 }, |
| 150 | { 63, 625, 0, 0x1d, 0 }, |
| 151 | { 50, 500, 0, 0x1c, 0 }, |
| 152 | { 38, 375, 0, 0x1b, 0 }, |
| 153 | { 25, 250, 0, 0x1a, 0 }, |
| 154 | { 13, 125, 0, 0x19, 0 }, |
| 155 | }; |
| 156 | |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 157 | static void generate_T_state_entries(int core, int cores_per_package) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 158 | { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 159 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 160 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 161 | |
| 162 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 163 | acpigen_write_empty_PTC(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 164 | |
| 165 | /* Set a T-state limit that can be modified in NVS */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 166 | acpigen_write_TPC("\\TLVL"); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 167 | |
| 168 | /* |
| 169 | * CPUID.(EAX=6):EAX[5] indicates support |
| 170 | * for extended throttle levels. |
| 171 | */ |
| 172 | if (cpuid_eax(6) & (1 << 5)) |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 173 | acpigen_write_TSS_package( |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 174 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 175 | else |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 176 | acpigen_write_TSS_package( |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 177 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 181 | { |
| 182 | u32 m; |
| 183 | u32 power; |
| 184 | |
| 185 | /* |
| 186 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 187 | * |
| 188 | * Power = (ratio / p1_ratio) * m * tdp |
| 189 | */ |
| 190 | |
| 191 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 192 | m = (m * m) / 1000; |
| 193 | |
| 194 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 195 | power *= (m / 100) * (tdp / 1000); |
| 196 | power /= 1000; |
| 197 | |
| 198 | return (int)power; |
| 199 | } |
| 200 | |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 201 | static void generate_P_state_entries(int core, int cores_per_package) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 202 | { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 203 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 204 | int coord_type, power_max, power_unit, num_entries; |
| 205 | int ratio, power, clock, clock_max; |
| 206 | msr_t msr; |
| 207 | |
| 208 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 209 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 210 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 211 | coord_type = SW_ANY; |
| 212 | else |
| 213 | coord_type = HW_ALL; |
| 214 | |
| 215 | /* Get bus ratio limits and calculate clock speeds */ |
| 216 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 217 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 218 | |
| 219 | /* Determine if this CPU has configurable TDP */ |
| 220 | if (cpu_config_tdp_levels()) { |
| 221 | /* Set max ratio to nominal TDP ratio */ |
| 222 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 223 | ratio_max = msr.lo & 0xff; |
| 224 | } else { |
| 225 | /* Max Non-Turbo Ratio */ |
| 226 | ratio_max = (msr.lo >> 8) & 0xff; |
| 227 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 228 | clock_max = ratio_max * SANDYBRIDGE_BCLK; |
| 229 | |
| 230 | /* Calculate CPU TDP in mW */ |
| 231 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 232 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 233 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 234 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 235 | |
| 236 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 237 | acpigen_write_empty_PCT(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 238 | |
| 239 | /* Write _PPC with no limit on supported P-state */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 240 | acpigen_write_PPC_NVS(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 241 | |
| 242 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 243 | acpigen_write_PSD_package(core, cores_per_package, coord_type); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 244 | |
| 245 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 246 | acpigen_write_name("_PSS"); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 247 | |
| 248 | /* Determine ratio points */ |
| 249 | ratio_step = PSS_RATIO_STEP; |
| 250 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 251 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 252 | ratio_step <<= 1; |
| 253 | num_entries >>= 1; |
| 254 | } |
| 255 | |
| 256 | /* P[T] is Turbo state if enabled */ |
| 257 | if (get_turbo_state() == TURBO_ENABLED) { |
| 258 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 259 | acpigen_write_package(num_entries + 2); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 260 | |
| 261 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 262 | ratio_turbo = msr.lo & 0xff; |
| 263 | |
| 264 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 265 | acpigen_write_PSS_package( |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 266 | clock_max + 1, /*MHz*/ |
| 267 | power_max, /*mW*/ |
| 268 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 269 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 270 | ratio_turbo << 8, /*control*/ |
| 271 | ratio_turbo << 8); /*status*/ |
| 272 | } else { |
| 273 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 274 | acpigen_write_package(num_entries + 1); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | /* First regular entry is max non-turbo ratio */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 278 | acpigen_write_PSS_package( |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 279 | clock_max, /*MHz*/ |
| 280 | power_max, /*mW*/ |
| 281 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 282 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 283 | ratio_max << 8, /*control*/ |
| 284 | ratio_max << 8); /*status*/ |
| 285 | |
| 286 | /* Generate the remaining entries */ |
| 287 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 288 | ratio >= ratio_min; ratio -= ratio_step) { |
| 289 | |
| 290 | /* Calculate power at this ratio */ |
| 291 | power = calculate_power(power_max, ratio_max, ratio); |
| 292 | clock = ratio * SANDYBRIDGE_BCLK; |
| 293 | |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 294 | acpigen_write_PSS_package( |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 295 | clock, /*MHz*/ |
| 296 | power, /*mW*/ |
| 297 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 298 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 299 | ratio << 8, /*control*/ |
| 300 | ratio << 8); /*status*/ |
| 301 | } |
| 302 | |
| 303 | /* Fix package length */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 304 | acpigen_pop_len(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 305 | } |
| 306 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 307 | void generate_cpu_entries(const struct device *device) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 308 | { |
Angel Pons | 6e7f9d6 | 2021-06-04 12:13:40 +0200 | [diff] [blame^] | 309 | int coreID, cpuID; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 310 | int totalcores = dev_count_cpu(); |
Evgeny Zinoviev | 920d2b7 | 2020-06-16 08:23:09 +0300 | [diff] [blame] | 311 | int cores_per_package = get_logical_cores_per_package(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 312 | int numcpus = totalcores/cores_per_package; |
| 313 | |
| 314 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 315 | numcpus, cores_per_package); |
| 316 | |
Martin Roth | 9944b28 | 2014-08-11 11:24:55 -0600 | [diff] [blame] | 317 | for (cpuID = 1; cpuID <= numcpus; cpuID++) { |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 318 | for (coreID = 1; coreID <= cores_per_package; coreID++) { |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 319 | /* Generate processor \_SB.CPUx */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 320 | acpigen_write_processor( |
Angel Pons | 6e7f9d6 | 2021-06-04 12:13:40 +0200 | [diff] [blame^] | 321 | (cpuID-1)*cores_per_package+coreID-1, 0, 0); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 322 | |
| 323 | /* Generate P-state tables */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 324 | generate_P_state_entries( |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 325 | cpuID-1, cores_per_package); |
| 326 | |
| 327 | /* Generate C-state tables */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 328 | generate_C_state_entries(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 329 | |
| 330 | /* Generate T-state tables */ |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 331 | generate_T_state_entries( |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 332 | cpuID-1, cores_per_package); |
| 333 | |
Vladimir Serbinenko | 226d784 | 2014-11-04 21:09:23 +0100 | [diff] [blame] | 334 | acpigen_pop_len(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 335 | } |
| 336 | } |
Arthur Heymans | 04008a9 | 2018-11-28 12:13:54 +0100 | [diff] [blame] | 337 | |
| 338 | /* PPKG is usually used for thermal management |
| 339 | of the first and only package. */ |
| 340 | acpigen_write_processor_package("PPKG", 0, cores_per_package); |
| 341 | |
| 342 | /* Add a method to notify processor nodes */ |
| 343 | acpigen_write_processor_cnot(cores_per_package); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | struct chip_operations cpu_intel_model_206ax_ops = { |
Stefan Reinauer | 0b7b7b6 | 2012-07-10 17:13:04 -0700 | [diff] [blame] | 347 | CHIP_NAME("Intel SandyBridge/IvyBridge CPU") |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 348 | }; |