blob: 33fece5c4dce739184a5012aa6b0a5aaaef5461d [file] [log] [blame]
Jonathan Zhangeacd74f2022-10-24 17:08:47 -07001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3#ifndef OCP_VPD_H
4#define OCP_VPD_H
5
6/* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */
7#define FRB2_TIMER "frb2_timer_enable"
8#define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */
9
10/* VPD variable for setting FRB2 timer countdown value (unit: 100ms). */
11#define FRB2_COUNTDOWN "frb2_countdown"
12/* Default countdown is 15 minutes when the VPD variable is not found */
13#define FRB2_COUNTDOWN_DEFAULT 9000
14
15/* VPD variable for setting FRB2 timer action.
16 0: No action, 1: hard reset, 2: power down, 3: power cycle */
17#define FRB2_ACTION "frb2_action"
18#define FRB2_ACTION_DEFAULT 0 /* Default no action when the VPD variable is not found */
19
20/* coreboot log level */
21#define COREBOOT_LOG_LEVEL "coreboot_log_level"
22#define COREBOOT_LOG_LEVEL_DEFAULT 4
23
24/* Define the VPD keys for UPD variables that can be overwritten */
25#define FSP_LOG "fsp_log_enable" /* 1 or 0: enable or disable FSP SOL log */
26#define FSP_LOG_DEFAULT 1 /* Default value when the VPD variable is not found */
27
28/* Select Memory Serial Debug Message Level.
29 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto */
30#define FSP_MEM_LOG_LEVEL "fsp_mem_log_lvl"
31#define FSP_MEM_LOG_LEVEL_DEFAULT 1
32
33/* VPD variable for enabling/disabling MRC promote warning in FSP.
34 System may upgrade memory training warning to fatal error when enabled.
35 0: Disable, 1: Enable */
36#define MRC_PROMOTE_WARNING "mrc_promote_warning"
37#define MRC_PROMOTE_WARNING_DEFAULT 1
38
39/* SMM log level */
40#define SMM_LOG_LEVEL "smm_log_level"
41#define SMM_LOG_LEVEL_DEFAULT 0 /* By default 0 would disable SMM log completely */
42
43/* FSP Dfx PMIC secure mode.
44 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode */
45#define FSP_PMIC_SECURE_MODE "fsp_pmic_mode"
46#define FSP_PMIC_SECURE_MODE_DEFAULT 2
47
48enum cxl_memory_mode {
49 CXL_DISABLED = 0,
50 CXL_SYSTEM_MEMORY = 1,
51 CXL_SPM = 2,
52 CXL_MODE_MAX,
53};
54
55/* CXL mode. 0: Disable CXL, 1: configured as system memory, 2: configured as SPM. */
56#define CXL_MODE "cxl_mode"
57#define CXL_MODE_DEFAULT CXL_SYSTEM_MEMORY /* By default configured as system memory */
58
59/* Skip TXT lockdown */
60#define SKIP_INTEL_TXT_LOCKDOWN "skip_intel_txt_lockdown"
61#define SKIP_INTEL_TXT_LOCKDOWN_DEFAULT 0
62
63/* Disable boot drive PCIe root port for testing */
64#define DISABLE_BOOTDRIVE "disable_bootdrive"
65#define DISABLE_BOOTDRIVE_DEFAULT 0 /* By default don't disable */
66
67/* Skip Global reset so that information in Previous Boot Error Hob won't be cleared */
68#define SKIP_GLOBAL_RESET "skip_global_reset"
69#define SKIP_GLOBAL_RESET_DEFAULT 1
70
71/* Disable memory poison */
72#define DISABLE_MEM_POISON "disable_mem_poison"
73#define DISABLE_MEM_POISON_DEFAULT 0
74
75/* Socket 0 core disable bitmask, set 1 to disable core */
76#define CORE_DIS_BITMSK0 "core_disable_bitmask0"
77/* Socket 1 core disable bitmask */
78#define CORE_DIS_BITMSK1 "core_disable_bitmask1"
79
80/* Get VPD key with provided fallback value and min/max ranges */
81int get_int_from_vpd_range(const char *const key, const int fallback, const int min,
82 const int max);
83bool get_bool_from_vpd(const char *const key, const bool fallback);
Johnny Lin651e3e02022-12-19 21:36:00 +080084int get_cxl_mode_from_vpd(void);
Johnny Lin6e7645e2023-01-16 17:21:01 +080085int get_loglevel_from_vpd(const char *const key, const int fallback);
Jonathan Zhangeacd74f2022-10-24 17:08:47 -070086#endif