Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <console/usb.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 6 | #include <delay.h> |
| 7 | #include "raminit_native.h" |
| 8 | #include "raminit_common.h" |
| 9 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 10 | /* Frequency multiplier */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 11 | static u32 get_FRQ(u32 tCK) |
| 12 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 13 | const u32 FRQ = 256000 / (tCK * BASEFREQ); |
| 14 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 15 | if (FRQ > 8) |
| 16 | return 8; |
| 17 | if (FRQ < 3) |
| 18 | return 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 19 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 20 | return FRQ; |
| 21 | } |
| 22 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 23 | /* Get REFI based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 24 | static u32 get_REFI(u32 tCK) |
| 25 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 26 | static const u32 frq_refi_map[] = { |
| 27 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 28 | 3120, 4160, 5200, 6240, 7280, 8320, |
| 29 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 30 | return frq_refi_map[get_FRQ(tCK) - 3]; |
| 31 | } |
| 32 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 33 | /* Get XSOffset based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 34 | static u8 get_XSOffset(u32 tCK) |
| 35 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 36 | static const u8 frq_xs_map[] = { |
| 37 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 38 | 4, 6, 7, 8, 10, 11, |
| 39 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 40 | return frq_xs_map[get_FRQ(tCK) - 3]; |
| 41 | } |
| 42 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 43 | /* Get MOD based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 44 | static u8 get_MOD(u32 tCK) |
| 45 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 46 | static const u8 frq_mod_map[] = { |
| 47 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 48 | 12, 12, 12, 12, 15, 16, |
| 49 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 50 | return frq_mod_map[get_FRQ(tCK) - 3]; |
| 51 | } |
| 52 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 53 | /* Get Write Leveling Output delay based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 54 | static u8 get_WLO(u32 tCK) |
| 55 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 56 | static const u8 frq_wlo_map[] = { |
| 57 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 58 | 4, 5, 6, 6, 8, 8, |
| 59 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 60 | return frq_wlo_map[get_FRQ(tCK) - 3]; |
| 61 | } |
| 62 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 63 | /* Get CKE based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 64 | static u8 get_CKE(u32 tCK) |
| 65 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 66 | static const u8 frq_cke_map[] = { |
| 67 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 68 | 3, 3, 4, 4, 5, 6, |
| 69 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 70 | return frq_cke_map[get_FRQ(tCK) - 3]; |
| 71 | } |
| 72 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 73 | /* Get XPDLL based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 74 | static u8 get_XPDLL(u32 tCK) |
| 75 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 76 | static const u8 frq_xpdll_map[] = { |
| 77 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 78 | 10, 13, 16, 20, 23, 26, |
| 79 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 80 | return frq_xpdll_map[get_FRQ(tCK) - 3]; |
| 81 | } |
| 82 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 83 | /* Get XP based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 84 | static u8 get_XP(u32 tCK) |
| 85 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 86 | static const u8 frq_xp_map[] = { |
| 87 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 88 | 3, 4, 4, 5, 6, 7, |
| 89 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 90 | return frq_xp_map[get_FRQ(tCK) - 3]; |
| 91 | } |
| 92 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 93 | /* Get AONPD based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 94 | static u8 get_AONPD(u32 tCK) |
| 95 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 96 | static const u8 frq_aonpd_map[] = { |
| 97 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 98 | 4, 5, 6, 8, 8, 10, |
| 99 | }; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 100 | return frq_aonpd_map[get_FRQ(tCK) - 3]; |
| 101 | } |
| 102 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 103 | /* Get COMP2 based on MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 104 | static u32 get_COMP2(u32 tCK) |
| 105 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 106 | static const u32 frq_comp2_map[] = { |
| 107 | /* FRQ: 3, 4, 5, 6, 7, 8, */ |
| 108 | 0x0D6BEDCC, 0x0CE7C34C, 0x0CA57A4C, 0x0C6369CC, 0x0C42514C, 0x0C21410C, |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 109 | }; |
| 110 | return frq_comp2_map[get_FRQ(tCK) - 3]; |
| 111 | } |
| 112 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 113 | static void snb_normalize_tclk(u32 *tclk) |
| 114 | { |
| 115 | if (*tclk <= TCK_1066MHZ) { |
| 116 | *tclk = TCK_1066MHZ; |
| 117 | } else if (*tclk <= TCK_933MHZ) { |
| 118 | *tclk = TCK_933MHZ; |
| 119 | } else if (*tclk <= TCK_800MHZ) { |
| 120 | *tclk = TCK_800MHZ; |
| 121 | } else if (*tclk <= TCK_666MHZ) { |
| 122 | *tclk = TCK_666MHZ; |
| 123 | } else if (*tclk <= TCK_533MHZ) { |
| 124 | *tclk = TCK_533MHZ; |
| 125 | } else if (*tclk <= TCK_400MHZ) { |
| 126 | *tclk = TCK_400MHZ; |
| 127 | } else { |
| 128 | *tclk = 0; |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | static void find_cas_tck(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 133 | { |
| 134 | u8 val; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 135 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 136 | /* Find CAS latency */ |
| 137 | while (1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 138 | /* |
| 139 | * Normalising tCK before computing clock could potentially |
| 140 | * result in a lower selected CAS, which is desired. |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 141 | */ |
| 142 | snb_normalize_tclk(&(ctrl->tCK)); |
| 143 | if (!(ctrl->tCK)) |
| 144 | die("Couldn't find compatible clock / CAS settings\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 145 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 146 | val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); |
| 147 | printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); |
| 148 | for (; val <= MAX_CAS; val++) |
| 149 | if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) |
| 150 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 151 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 152 | if (val == (MAX_CAS + 1)) { |
| 153 | ctrl->tCK++; |
| 154 | continue; |
| 155 | } else { |
| 156 | printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n"); |
| 157 | break; |
| 158 | } |
| 159 | } |
| 160 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 161 | printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 162 | printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); |
| 163 | ctrl->CAS = val; |
| 164 | } |
| 165 | |
| 166 | static void dram_timing(ramctr_timing *ctrl) |
| 167 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 168 | /* |
| 169 | * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). |
| 170 | * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. |
| 171 | */ |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 172 | if (ctrl->tCK == TCK_1066MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 173 | ctrl->edge_offset[0] = 16; |
| 174 | ctrl->edge_offset[1] = 7; |
| 175 | ctrl->edge_offset[2] = 7; |
| 176 | ctrl->timC_offset[0] = 18; |
| 177 | ctrl->timC_offset[1] = 7; |
| 178 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 179 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 180 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 181 | } else if (ctrl->tCK == TCK_933MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 182 | ctrl->edge_offset[0] = 14; |
| 183 | ctrl->edge_offset[1] = 6; |
| 184 | ctrl->edge_offset[2] = 6; |
| 185 | ctrl->timC_offset[0] = 15; |
| 186 | ctrl->timC_offset[1] = 6; |
| 187 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 188 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 189 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 190 | } else if (ctrl->tCK == TCK_800MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 191 | ctrl->edge_offset[0] = 13; |
| 192 | ctrl->edge_offset[1] = 5; |
| 193 | ctrl->edge_offset[2] = 5; |
| 194 | ctrl->timC_offset[0] = 14; |
| 195 | ctrl->timC_offset[1] = 5; |
| 196 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 197 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 198 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 199 | } else if (ctrl->tCK == TCK_666MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 200 | ctrl->edge_offset[0] = 10; |
| 201 | ctrl->edge_offset[1] = 4; |
| 202 | ctrl->edge_offset[2] = 4; |
| 203 | ctrl->timC_offset[0] = 11; |
| 204 | ctrl->timC_offset[1] = 4; |
| 205 | ctrl->timC_offset[2] = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 206 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 207 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 208 | } else if (ctrl->tCK == TCK_533MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 209 | ctrl->edge_offset[0] = 8; |
| 210 | ctrl->edge_offset[1] = 3; |
| 211 | ctrl->edge_offset[2] = 3; |
| 212 | ctrl->timC_offset[0] = 9; |
| 213 | ctrl->timC_offset[1] = 3; |
| 214 | ctrl->timC_offset[2] = 3; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 215 | ctrl->pi_coding_threshold = 17; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 216 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 217 | } else { |
| 218 | ctrl->tCK = TCK_400MHZ; |
| 219 | ctrl->edge_offset[0] = 6; |
| 220 | ctrl->edge_offset[1] = 2; |
| 221 | ctrl->edge_offset[2] = 2; |
| 222 | ctrl->timC_offset[0] = 6; |
| 223 | ctrl->timC_offset[1] = 2; |
| 224 | ctrl->timC_offset[2] = 2; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 225 | ctrl->pi_coding_threshold = 17; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | /* Initial phase between CLK/CMD pins */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 229 | ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 230 | |
| 231 | /* DLL_CONFIG_MDLL_W_TIMER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 232 | ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 233 | |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 234 | if (ctrl->tCWL) |
| 235 | ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); |
| 236 | else |
| 237 | ctrl->CWL = get_CWL(ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 238 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 239 | printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); |
| 240 | |
| 241 | /* Find tRCD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 242 | ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 243 | printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); |
| 244 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 245 | ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 246 | printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); |
| 247 | |
| 248 | /* Find tRAS */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 249 | ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 250 | printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); |
| 251 | |
| 252 | /* Find tWR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 253 | ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 254 | printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); |
| 255 | |
| 256 | /* Find tFAW */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 257 | ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 258 | printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); |
| 259 | |
| 260 | /* Find tRRD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 261 | ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 262 | printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); |
| 263 | |
| 264 | /* Find tRTP */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 265 | ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 266 | printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); |
| 267 | |
| 268 | /* Find tWTR */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 269 | ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 270 | printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); |
| 271 | |
| 272 | /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ |
Angel Pons | 143309f | 2020-03-21 21:38:16 +0100 | [diff] [blame] | 273 | ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 274 | printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); |
| 275 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 276 | ctrl->tREFI = get_REFI(ctrl->tCK); |
| 277 | ctrl->tMOD = get_MOD(ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 278 | ctrl->tXSOffset = get_XSOffset(ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 279 | ctrl->tWLO = get_WLO(ctrl->tCK); |
| 280 | ctrl->tCKE = get_CKE(ctrl->tCK); |
| 281 | ctrl->tXPDLL = get_XPDLL(ctrl->tCK); |
| 282 | ctrl->tXP = get_XP(ctrl->tCK); |
| 283 | ctrl->tAONPD = get_AONPD(ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 284 | } |
| 285 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 286 | static void dram_freq(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 287 | { |
| 288 | if (ctrl->tCK > TCK_400MHZ) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 289 | printk(BIOS_ERR, |
| 290 | "DRAM frequency is under lowest supported frequency (400 MHz). " |
| 291 | "Increasing to 400 MHz as last resort"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 292 | ctrl->tCK = TCK_400MHZ; |
| 293 | } |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 294 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 295 | while (1) { |
| 296 | u8 val2; |
| 297 | u32 reg1 = 0; |
| 298 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 299 | /* Step 1 - Set target PCU frequency */ |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 300 | find_cas_tck(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 301 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 302 | /* Frequency multiplier */ |
| 303 | const u32 FRQ = get_FRQ(ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 304 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 305 | /* |
| 306 | * The PLL will never lock if the required frequency is already set. |
| 307 | * Exit early to prevent a system hang. |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 308 | */ |
| 309 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 310 | val2 = (u8) reg1; |
| 311 | if (val2) |
| 312 | return; |
| 313 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 314 | /* Step 1 - Select frequency in the MCU */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 315 | reg1 = FRQ; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 316 | reg1 |= 0x80000000; /* set running bit */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 317 | MCHBAR32(MC_BIOS_REQ) = reg1; |
| 318 | int i=0; |
| 319 | printk(BIOS_DEBUG, "PLL busy... "); |
| 320 | while (reg1 & 0x80000000) { |
| 321 | udelay(10); |
| 322 | i++; |
| 323 | reg1 = MCHBAR32(MC_BIOS_REQ); |
| 324 | } |
| 325 | printk(BIOS_DEBUG, "done in %d us\n", i * 10); |
| 326 | |
Arthur Heymans | dcd3cef | 2017-05-16 17:58:25 +0200 | [diff] [blame] | 327 | /* Step 2 - Verify lock frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 328 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 329 | val2 = (u8) reg1; |
| 330 | if (val2 >= FRQ) { |
| 331 | printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", |
| 332 | (1000 << 8) / ctrl->tCK); |
| 333 | return; |
| 334 | } |
| 335 | printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); |
| 336 | ctrl->tCK++; |
| 337 | } |
| 338 | } |
| 339 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 340 | static void dram_ioregs(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 341 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 342 | u32 reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 343 | |
| 344 | int channel; |
| 345 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 346 | /* IO clock */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 347 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 348 | MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 349 | } |
| 350 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 351 | /* IO command */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 352 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 353 | MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 354 | } |
| 355 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 356 | /* IO control */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 357 | FOR_ALL_POPULATED_CHANNELS { |
| 358 | program_timings(ctrl, channel); |
| 359 | } |
| 360 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 361 | /* Perform RCOMP */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 362 | printram("RCOMP..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 363 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 364 | ; |
| 365 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 366 | printram("done\n"); |
| 367 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 368 | /* Set COMP2 */ |
| 369 | MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 370 | printram("COMP2 done\n"); |
| 371 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 372 | /* Set COMP1 */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 373 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 374 | reg = MCHBAR32(CRCOMPOFST1_ch(channel)); |
| 375 | reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ |
| 376 | reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ |
| 377 | reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 378 | MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 379 | } |
| 380 | printram("COMP1 done\n"); |
| 381 | |
| 382 | printram("FORCE RCOMP and wait 20us..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 383 | MCHBAR32(M_COMP) |= (1 << 8); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 384 | udelay(20); |
| 385 | printram("done\n"); |
| 386 | } |
| 387 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 388 | int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 389 | { |
| 390 | int err; |
| 391 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 392 | printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", fast_boot); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 393 | |
| 394 | if (!fast_boot) { |
| 395 | /* Find fastest common supported parameters */ |
| 396 | dram_find_common_params(ctrl); |
| 397 | |
| 398 | dram_dimm_mapping(ctrl); |
| 399 | } |
| 400 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 401 | /* Set MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 402 | dram_freq(ctrl); |
| 403 | |
| 404 | if (!fast_boot) { |
| 405 | /* Calculate timings */ |
| 406 | dram_timing(ctrl); |
| 407 | } |
| 408 | |
| 409 | /* Set version register */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 410 | MCHBAR32(MRC_REVISION) = 0xc04eb002; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 411 | |
| 412 | /* Enable crossover */ |
| 413 | dram_xover(ctrl); |
| 414 | |
| 415 | /* Set timing and refresh registers */ |
| 416 | dram_timing_regs(ctrl); |
| 417 | |
| 418 | /* Power mode preset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 419 | MCHBAR32(PM_THML_STAT) = 0x5500; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 420 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 421 | /* Set scheduler chicken bits */ |
| 422 | MCHBAR32(SCHED_CBIT) = 0x10100005; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 423 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 424 | /* Set up watermarks and starvation counter */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 425 | set_wmm_behavior(ctrl->cpu); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 426 | |
| 427 | /* Clear IO reset bit */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 428 | MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 429 | |
| 430 | /* Set MAD-DIMM registers */ |
| 431 | dram_dimm_set_mapping(ctrl); |
| 432 | printk(BIOS_DEBUG, "Done dimm mapping\n"); |
| 433 | |
| 434 | /* Zone config */ |
| 435 | dram_zones(ctrl, 1); |
| 436 | |
| 437 | /* Set memory map */ |
| 438 | dram_memorymap(ctrl, me_uma_size); |
| 439 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 440 | |
| 441 | /* Set IO registers */ |
| 442 | dram_ioregs(ctrl); |
| 443 | printk(BIOS_DEBUG, "Done io registers\n"); |
| 444 | |
| 445 | udelay(1); |
| 446 | |
| 447 | if (fast_boot) { |
| 448 | restore_timings(ctrl); |
| 449 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 450 | /* Do JEDEC DDR3 reset sequence */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 451 | dram_jedecreset(ctrl); |
| 452 | printk(BIOS_DEBUG, "Done jedec reset\n"); |
| 453 | |
| 454 | /* MRS commands */ |
| 455 | dram_mrscommands(ctrl); |
| 456 | printk(BIOS_DEBUG, "Done MRS commands\n"); |
| 457 | |
| 458 | /* Prepare for memory training */ |
| 459 | prepare_training(ctrl); |
| 460 | |
| 461 | err = read_training(ctrl); |
| 462 | if (err) |
| 463 | return err; |
| 464 | |
| 465 | err = write_training(ctrl); |
| 466 | if (err) |
| 467 | return err; |
| 468 | |
| 469 | printram("CP5a\n"); |
| 470 | |
| 471 | err = discover_edges(ctrl); |
| 472 | if (err) |
| 473 | return err; |
| 474 | |
| 475 | printram("CP5b\n"); |
| 476 | |
| 477 | err = command_training(ctrl); |
| 478 | if (err) |
| 479 | return err; |
| 480 | |
| 481 | printram("CP5c\n"); |
| 482 | |
| 483 | err = discover_edges_write(ctrl); |
| 484 | if (err) |
| 485 | return err; |
| 486 | |
| 487 | err = discover_timC_write(ctrl); |
| 488 | if (err) |
| 489 | return err; |
| 490 | |
| 491 | normalize_training(ctrl); |
| 492 | } |
| 493 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 494 | set_read_write_timings(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 495 | |
| 496 | write_controller_mr(ctrl); |
| 497 | |
| 498 | if (!s3_resume) { |
| 499 | err = channel_test(ctrl); |
| 500 | if (err) |
| 501 | return err; |
| 502 | } |
| 503 | |
| 504 | return 0; |
| 505 | } |