Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; version 2 of |
| 8 | * the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | |
| 17 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 18 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 19 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 20 | Name(_BBN, 0) |
| 21 | |
| 22 | Device (MCHC) |
| 23 | { |
| 24 | Name(_ADR, 0x00000000) // 0:0.0 |
| 25 | |
| 26 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 27 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 28 | { |
| 29 | Offset (0x40), // EPBAR |
| 30 | EPEN, 1, // Enable |
| 31 | , 11, // |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 32 | EPBR, 27, // EPBAR |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 33 | |
| 34 | Offset (0x48), // MCHBAR |
| 35 | MHEN, 1, // Enable |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 36 | , 14, // |
| 37 | MHBR, 24, // MCHBAR |
Patrick Rudolph | 0b643d2 | 2017-07-05 20:07:06 +0200 | [diff] [blame] | 38 | Offset (0x54), |
| 39 | DVEN, 32, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 40 | Offset (0x60), // PCIe BAR |
| 41 | PXEN, 1, // Enable |
| 42 | PXSZ, 2, // BAR size |
| 43 | , 23, // |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 44 | PXBR, 13, // PCIe BAR |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | |
| 46 | Offset (0x68), // DMIBAR |
| 47 | DMEN, 1, // Enable |
| 48 | , 11, // |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 49 | DMBR, 27, // DMIBAR |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 50 | |
| 51 | Offset (0x70), // ME Base Address |
| 52 | MEBA, 64, |
| 53 | |
| 54 | // ... |
| 55 | |
| 56 | Offset (0x80), // PAM0 |
| 57 | , 4, |
| 58 | PM0H, 2, |
| 59 | , 2, |
| 60 | Offset (0x81), // PAM1 |
| 61 | PM1L, 2, |
| 62 | , 2, |
| 63 | PM1H, 2, |
| 64 | , 2, |
| 65 | Offset (0x82), // PAM2 |
| 66 | PM2L, 2, |
| 67 | , 2, |
| 68 | PM2H, 2, |
| 69 | , 2, |
| 70 | Offset (0x83), // PAM3 |
| 71 | PM3L, 2, |
| 72 | , 2, |
| 73 | PM3H, 2, |
| 74 | , 2, |
| 75 | Offset (0x84), // PAM4 |
| 76 | PM4L, 2, |
| 77 | , 2, |
| 78 | PM4H, 2, |
| 79 | , 2, |
| 80 | Offset (0x85), // PAM5 |
| 81 | PM5L, 2, |
| 82 | , 2, |
| 83 | PM5H, 2, |
| 84 | , 2, |
| 85 | Offset (0x86), // PAM6 |
| 86 | PM6L, 2, |
| 87 | , 2, |
| 88 | PM6H, 2, |
| 89 | , 2, |
| 90 | |
| 91 | Offset (0xa0), // Top of Used Memory |
| 92 | TOM, 64, |
| 93 | |
| 94 | Offset (0xbc), // Top of Low Used Memory |
| 95 | TLUD, 32, |
| 96 | } |
| 97 | |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 98 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 99 | Name (CTCC, 0) /* CTDP Current Selection */ |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 100 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 101 | Name (CTCD, 1) /* CTDP Down Select */ |
| 102 | Name (CTCU, 2) /* CTDP Up Select */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 103 | |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 104 | OperationRegion (MCHB, SystemMemory, \_SB.PCI0.MCHC.MHBR << 15, 0x8000) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 105 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 106 | { |
| 107 | Offset (0x5930), |
| 108 | CTDN, 15, /* CTDP Nominal PL1 */ |
| 109 | Offset (0x59a0), |
| 110 | PL1V, 15, /* Power Limit 1 Value */ |
| 111 | PL1E, 1, /* Power Limit 1 Enable */ |
| 112 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 113 | PL1T, 7, /* Power Limit 1 Time */ |
| 114 | Offset (0x59a4), |
| 115 | PL2V, 15, /* Power Limit 2 Value */ |
| 116 | PL2E, 1, /* Power Limit 2 Enable */ |
| 117 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 118 | PL2T, 7, /* Power Limit 2 Time */ |
| 119 | Offset (0x5f3c), |
| 120 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
| 121 | Offset (0x5f40), |
| 122 | CTDD, 15, /* CTDP Down PL1 */ |
| 123 | , 1, |
| 124 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
| 125 | Offset (0x5f48), |
| 126 | CTDU, 15, /* CTDP Up PL1 */ |
| 127 | , 1, |
| 128 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
| 129 | Offset (0x5f50), |
| 130 | CTCS, 2, /* CTDP Select */ |
| 131 | Offset (0x5f54), |
| 132 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 133 | } |
| 134 | |
| 135 | /* |
| 136 | * Search CPU0 _PSS looking for control=arg0 and then |
| 137 | * return previous P-state entry number for new _PPC |
| 138 | * |
| 139 | * Format of _PSS: |
| 140 | * Name (_PSS, Package () { |
| 141 | * Package (6) { freq, power, tlat, blat, control, status } |
| 142 | * } |
| 143 | */ |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 144 | External (\_SB.CP00._PSS) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 145 | Method (PSSS, 1, NotSerialized) |
| 146 | { |
| 147 | Store (One, Local0) /* Start at P1 */ |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 148 | Store (SizeOf (\_SB.CP00._PSS), Local1) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 149 | |
| 150 | While (LLess (Local0, Local1)) { |
| 151 | /* Store _PSS entry Control value to Local2 */ |
| 152 | ShiftRight (DeRefOf (Index (DeRefOf (Index |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 153 | (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 154 | If (LEqual (Local2, Arg0)) { |
| 155 | Return (Subtract (Local0, 1)) |
| 156 | } |
| 157 | Increment (Local0) |
| 158 | } |
| 159 | |
| 160 | Return (0) |
| 161 | } |
| 162 | |
| 163 | /* Set TDP Down */ |
| 164 | Method (STND, 0, Serialized) |
| 165 | { |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 166 | If (Acquire (CTCM, 100)) { |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 167 | Return (0) |
| 168 | } |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 169 | If (LEqual (CTCD, CTCC)) { |
| 170 | Release (CTCM) |
| 171 | Return (0) |
| 172 | } |
| 173 | |
| 174 | Store ("Set TDP Down", Debug) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 175 | |
| 176 | /* Set CTC */ |
| 177 | Store (CTCD, CTCS) |
| 178 | |
| 179 | /* Set TAR */ |
| 180 | Store (TARD, TARS) |
| 181 | |
| 182 | /* Set PPC limit and notify OS */ |
| 183 | Store (PSSS (TARD), PPCM) |
| 184 | PPCN () |
| 185 | |
| 186 | /* Set PL2 to 1.25 * PL1 */ |
Martin Roth | 35272fd | 2015-12-10 08:28:53 -0700 | [diff] [blame] | 187 | Divide (Multiply (CTDD, 125), 100, , PL2V) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 188 | |
| 189 | /* Set PL1 */ |
| 190 | Store (CTDD, PL1V) |
| 191 | |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 192 | /* Store the new TDP Down setting */ |
| 193 | Store (CTCD, CTCC) |
| 194 | |
| 195 | Release (CTCM) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 196 | Return (1) |
| 197 | } |
| 198 | |
| 199 | /* Set TDP Nominal from Down */ |
| 200 | Method (STDN, 0, Serialized) |
| 201 | { |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 202 | If (Acquire (CTCM, 100)) { |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 203 | Return (0) |
| 204 | } |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 205 | If (LEqual (CTCN, CTCC)) { |
| 206 | Release (CTCM) |
| 207 | Return (0) |
| 208 | } |
| 209 | |
| 210 | Store ("Set TDP Nominal", Debug) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 211 | |
| 212 | /* Set PL1 */ |
| 213 | Store (CTDN, PL1V) |
| 214 | |
| 215 | /* Set PL2 to 1.25 * PL1 */ |
Martin Roth | 35272fd | 2015-12-10 08:28:53 -0700 | [diff] [blame] | 216 | Divide (Multiply (CTDN, 125), 100, , PL2V) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 217 | |
| 218 | /* Set PPC limit and notify OS */ |
| 219 | Store (PSSS (TARN), PPCM) |
| 220 | PPCN () |
| 221 | |
| 222 | /* Set TAR */ |
| 223 | Store (TARN, TARS) |
| 224 | |
| 225 | /* Set CTC */ |
| 226 | Store (CTCN, CTCS) |
| 227 | |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 228 | /* Store the new TDP Nominal setting */ |
| 229 | Store (CTCN, CTCC) |
| 230 | |
| 231 | Release (CTCM) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 232 | Return (1) |
| 233 | } |
| 234 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 235 | |
| 236 | // Current Resource Settings |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 237 | Name (MCRS, ResourceTemplate() |
| 238 | { |
| 239 | // Bus Numbers |
| 240 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 241 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 242 | |
| 243 | // IO Region 0 |
| 244 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 245 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 246 | |
| 247 | // PCI Config Space |
| 248 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 249 | |
| 250 | // IO Region 1 |
| 251 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 252 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 253 | |
| 254 | // VGA memory (0xa0000-0xbffff) |
| 255 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 256 | Cacheable, ReadWrite, |
| 257 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 258 | 0x00020000,,, ASEG) |
| 259 | |
| 260 | // OPROM reserved (0xc0000-0xc3fff) |
| 261 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 262 | Cacheable, ReadWrite, |
| 263 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 264 | 0x00004000,,, OPR0) |
| 265 | |
| 266 | // OPROM reserved (0xc4000-0xc7fff) |
| 267 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 268 | Cacheable, ReadWrite, |
| 269 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 270 | 0x00004000,,, OPR1) |
| 271 | |
| 272 | // OPROM reserved (0xc8000-0xcbfff) |
| 273 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 274 | Cacheable, ReadWrite, |
| 275 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 276 | 0x00004000,,, OPR2) |
| 277 | |
| 278 | // OPROM reserved (0xcc000-0xcffff) |
| 279 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 280 | Cacheable, ReadWrite, |
| 281 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 282 | 0x00004000,,, OPR3) |
| 283 | |
| 284 | // OPROM reserved (0xd0000-0xd3fff) |
| 285 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 286 | Cacheable, ReadWrite, |
| 287 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 288 | 0x00004000,,, OPR4) |
| 289 | |
| 290 | // OPROM reserved (0xd4000-0xd7fff) |
| 291 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 292 | Cacheable, ReadWrite, |
| 293 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 294 | 0x00004000,,, OPR5) |
| 295 | |
| 296 | // OPROM reserved (0xd8000-0xdbfff) |
| 297 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 298 | Cacheable, ReadWrite, |
| 299 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 300 | 0x00004000,,, OPR6) |
| 301 | |
| 302 | // OPROM reserved (0xdc000-0xdffff) |
| 303 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 304 | Cacheable, ReadWrite, |
| 305 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 306 | 0x00004000,,, OPR7) |
| 307 | |
| 308 | // BIOS Extension (0xe0000-0xe3fff) |
| 309 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 310 | Cacheable, ReadWrite, |
| 311 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 312 | 0x00004000,,, ESG0) |
| 313 | |
| 314 | // BIOS Extension (0xe4000-0xe7fff) |
| 315 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 316 | Cacheable, ReadWrite, |
| 317 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 318 | 0x00004000,,, ESG1) |
| 319 | |
| 320 | // BIOS Extension (0xe8000-0xebfff) |
| 321 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 322 | Cacheable, ReadWrite, |
| 323 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 324 | 0x00004000,,, ESG2) |
| 325 | |
| 326 | // BIOS Extension (0xec000-0xeffff) |
| 327 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 328 | Cacheable, ReadWrite, |
| 329 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 330 | 0x00004000,,, ESG3) |
| 331 | |
| 332 | // System BIOS (0xf0000-0xfffff) |
| 333 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 334 | Cacheable, ReadWrite, |
| 335 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 336 | 0x00010000,,, FSEG) |
| 337 | |
| 338 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 339 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 340 | Cacheable, ReadWrite, |
| 341 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 342 | 0x00000000,,, PM01) |
| 343 | |
| 344 | // TPM Area (0xfed40000-0xfed44fff) |
| 345 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 346 | Cacheable, ReadWrite, |
| 347 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 348 | 0x00005000,,, TPMR) |
| 349 | }) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 350 | |
| 351 | Method (_CRS, 0, Serialized) |
| 352 | { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 353 | // Find PCI resource area in MCRS |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 354 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 355 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 356 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 357 | |
| 358 | // Fix up PCI memory region |
| 359 | // Start with Top of Lower Usable DRAM |
| 360 | Store (^MCHC.TLUD, Local0) |
| 361 | Store (^MCHC.MEBA, Local1) |
| 362 | |
| 363 | // Check if ME base is equal |
| 364 | If (LEqual (Local0, Local1)) { |
| 365 | // Use Top Of Memory instead |
| 366 | Store (^MCHC.TOM, Local0) |
| 367 | } |
| 368 | |
| 369 | Store (Local0, PMIN) |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 370 | Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 371 | Add(Subtract(PMAX, PMIN), 1, PLEN) |
| 372 | |
| 373 | Return (MCRS) |
| 374 | } |