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review.coreboot.org / coreboot / 55864eff9218259335a776a139424c4d178cf14e / . / src / northbridge / intel / sandybridge / acpi / hostbridge.asl
blob: 8dd1de6ff63474b95e0a98d1a237acc04b08c467 [file] [log] [blame]
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
22
23Name(_HID,EISAID("PNP0A08")) // PCIe
24Name(_CID,EISAID("PNP0A03")) // PCI
25
26Name(_ADR, 0)
27Name(_BBN, 0)
28
29Device (MCHC)
30{
31 Name(_ADR, 0x00000000) // 0:0.0
32
33 OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
34 Field (MCHP, DWordAcc, NoLock, Preserve)
35 {
36 Offset (0x40), // EPBAR
37 EPEN, 1, // Enable
38 , 11, //
39 EPBR, 24, // EPBAR
40
41 Offset (0x48), // MCHBAR
42 MHEN, 1, // Enable
43 , 13, //
44 MHBR, 22, // MCHBAR
45
46 Offset (0x60), // PCIe BAR
47 PXEN, 1, // Enable
48 PXSZ, 2, // BAR size
49 , 23, //
50 PXBR, 10, // PCIe BAR
51
52 Offset (0x68), // DMIBAR
53 DMEN, 1, // Enable
54 , 11, //
55 DMBR, 24, // DMIBAR
56
57 Offset (0x70), // ME Base Address
58 MEBA, 64,
59
60 // ...
61
62 Offset (0x80), // PAM0
63 , 4,
64 PM0H, 2,
65 , 2,
66 Offset (0x81), // PAM1
67 PM1L, 2,
68 , 2,
69 PM1H, 2,
70 , 2,
71 Offset (0x82), // PAM2
72 PM2L, 2,
73 , 2,
74 PM2H, 2,
75 , 2,
76 Offset (0x83), // PAM3
77 PM3L, 2,
78 , 2,
79 PM3H, 2,
80 , 2,
81 Offset (0x84), // PAM4
82 PM4L, 2,
83 , 2,
84 PM4H, 2,
85 , 2,
86 Offset (0x85), // PAM5
87 PM5L, 2,
88 , 2,
89 PM5H, 2,
90 , 2,
91 Offset (0x86), // PAM6
92 PM6L, 2,
93 , 2,
94 PM6H, 2,
95 , 2,
96
97 Offset (0xa0), // Top of Used Memory
98 TOM, 64,
99
100 Offset (0xbc), // Top of Low Used Memory
101 TLUD, 32,
102 }
103
Duncan Laurie55864ef2012-07-16 12:27:42 -0700[diff] [blame^]104 Name (CTCN, 0) /* CTDP Nominal Select */
105 Name (CTCD, 1) /* CTDP Down Select */
106 Name (CTCU, 2) /* CTDP Up Select */
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]107
Duncan Laurie55864ef2012-07-16 12:27:42 -0700[diff] [blame^]108 OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
109 Field (MCHB, DWordAcc, Lock, Preserve)
110 {
111 Offset (0x5930),
112 CTDN, 15, /* CTDP Nominal PL1 */
113 Offset (0x59a0),
114 PL1V, 15, /* Power Limit 1 Value */
115 PL1E, 1, /* Power Limit 1 Enable */
116 PL1C, 1, /* Power Limit 1 Clamp */
117 PL1T, 7, /* Power Limit 1 Time */
118 Offset (0x59a4),
119 PL2V, 15, /* Power Limit 2 Value */
120 PL2E, 1, /* Power Limit 2 Enable */
121 PL2C, 1, /* Power Limit 2 Clamp */
122 PL2T, 7, /* Power Limit 2 Time */
123 Offset (0x5f3c),
124 TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
125 Offset (0x5f40),
126 CTDD, 15, /* CTDP Down PL1 */
127 , 1,
128 TARD, 8, /* CTDP Down Turbo Activation Ratio */
129 Offset (0x5f48),
130 CTDU, 15, /* CTDP Up PL1 */
131 , 1,
132 TARU, 8, /* CTDP Up Turbo Activation Ratio */
133 Offset (0x5f50),
134 CTCS, 2, /* CTDP Select */
135 Offset (0x5f54),
136 TARS, 8, /* Turbo Activation Ratio Select */
137 }
138
139 /*
140 * Search CPU0 _PSS looking for control=arg0 and then
141 * return previous P-state entry number for new _PPC
142 *
143 * Format of _PSS:
144 * Name (_PSS, Package () {
145 * Package (6) { freq, power, tlat, blat, control, status }
146 * }
147 */
148 External (\_PR.CPU0._PSS)
149 Method (PSSS, 1, NotSerialized)
150 {
151 Store (One, Local0) /* Start at P1 */
152 Store (SizeOf (\_PR.CPU0._PSS), Local1)
153
154 While (LLess (Local0, Local1)) {
155 /* Store _PSS entry Control value to Local2 */
156 ShiftRight (DeRefOf (Index (DeRefOf (Index
157 (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2)
158 If (LEqual (Local2, Arg0)) {
159 Return (Subtract (Local0, 1))
160 }
161 Increment (Local0)
162 }
163
164 Return (0)
165 }
166
167 /* Set TDP Down */
168 Method (STND, 0, Serialized)
169 {
170 Store ("Set TDP Down", Debug)
171
172 If (LEqual (CTCD, CTCS)) {
173 Return (0)
174 }
175
176 /* Set CTC */
177 Store (CTCD, CTCS)
178
179 /* Set TAR */
180 Store (TARD, TARS)
181
182 /* Set PPC limit and notify OS */
183 Store (PSSS (TARD), PPCM)
184 PPCN ()
185
186 /* Set PL2 to 1.25 * PL1 */
187 Divide (Multiply (CTDD, 125), 100, Local0, PL2V)
188
189 /* Set PL1 */
190 Store (CTDD, PL1V)
191
192 Return (1)
193 }
194
195 /* Set TDP Nominal from Down */
196 Method (STDN, 0, Serialized)
197 {
198 Store ("Set TDP Nominal", Debug)
199
200 If (LEqual (CTCN, CTCS)) {
201 Return (0)
202 }
203
204 /* Set PL1 */
205 Store (CTDN, PL1V)
206
207 /* Set PL2 to 1.25 * PL1 */
208 Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
209
210 /* Set PPC limit and notify OS */
211 Store (PSSS (TARN), PPCM)
212 PPCN ()
213
214 /* Set TAR */
215 Store (TARN, TARS)
216
217 /* Set CTC */
218 Store (CTCN, CTCS)
219
220 Return (1)
221 }
222}
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]223
224// Current Resource Settings
225
226Method (_CRS, 0, Serialized)
227{
228 Name (MCRS, ResourceTemplate()
229 {
230 // Bus Numbers
231 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
232 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
233
234 // IO Region 0
235 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
236 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
237
238 // PCI Config Space
239 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
240
241 // IO Region 1
242 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
243 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
244
245 // VGA memory (0xa0000-0xbffff)
246 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
247 Cacheable, ReadWrite,
248 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
249 0x00020000,,, ASEG)
250
251 // OPROM reserved (0xc0000-0xc3fff)
252 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
253 Cacheable, ReadWrite,
254 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
255 0x00004000,,, OPR0)
256
257 // OPROM reserved (0xc4000-0xc7fff)
258 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
259 Cacheable, ReadWrite,
260 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
261 0x00004000,,, OPR1)
262
263 // OPROM reserved (0xc8000-0xcbfff)
264 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
265 Cacheable, ReadWrite,
266 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
267 0x00004000,,, OPR2)
268
269 // OPROM reserved (0xcc000-0xcffff)
270 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
271 Cacheable, ReadWrite,
272 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
273 0x00004000,,, OPR3)
274
275 // OPROM reserved (0xd0000-0xd3fff)
276 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
277 Cacheable, ReadWrite,
278 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
279 0x00004000,,, OPR4)
280
281 // OPROM reserved (0xd4000-0xd7fff)
282 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
283 Cacheable, ReadWrite,
284 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
285 0x00004000,,, OPR5)
286
287 // OPROM reserved (0xd8000-0xdbfff)
288 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
289 Cacheable, ReadWrite,
290 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
291 0x00004000,,, OPR6)
292
293 // OPROM reserved (0xdc000-0xdffff)
294 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
295 Cacheable, ReadWrite,
296 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
297 0x00004000,,, OPR7)
298
299 // BIOS Extension (0xe0000-0xe3fff)
300 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
301 Cacheable, ReadWrite,
302 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
303 0x00004000,,, ESG0)
304
305 // BIOS Extension (0xe4000-0xe7fff)
306 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
307 Cacheable, ReadWrite,
308 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
309 0x00004000,,, ESG1)
310
311 // BIOS Extension (0xe8000-0xebfff)
312 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
313 Cacheable, ReadWrite,
314 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
315 0x00004000,,, ESG2)
316
317 // BIOS Extension (0xec000-0xeffff)
318 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
319 Cacheable, ReadWrite,
320 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
321 0x00004000,,, ESG3)
322
323 // System BIOS (0xf0000-0xfffff)
324 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
325 Cacheable, ReadWrite,
326 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
327 0x00010000,,, FSEG)
328
329 // PCI Memory Region (Top of memory-0xfebfffff)
330 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
331 Cacheable, ReadWrite,
332 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
333 0xfec00000,,, PM01)
334
335 // TPM Area (0xfed40000-0xfed44fff)
336 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
337 Cacheable, ReadWrite,
338 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
339 0x00005000,,, TPMR)
340 })
341
342 // Find PCI resource area in MCRS
343 CreateDwordField(MCRS, PM01._MIN, PMIN)
344 CreateDwordField(MCRS, PM01._MAX, PMAX)
345 CreateDwordField(MCRS, PM01._LEN, PLEN)
346
347 // Fix up PCI memory region
348 // Start with Top of Lower Usable DRAM
349 Store (^MCHC.TLUD, Local0)
350 Store (^MCHC.MEBA, Local1)
351
352 // Check if ME base is equal
353 If (LEqual (Local0, Local1)) {
354 // Use Top Of Memory instead
355 Store (^MCHC.TOM, Local0)
356 }
357
358 Store (Local0, PMIN)
359 Add(Subtract(PMAX, PMIN), 1, PLEN)
360
361 Return (MCRS)
362}
363
364/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
365#include "acpi/sandybridge_pci_irqs.asl"
366
367