Sven Schnelle | 1767086 | 2012-02-01 22:06:45 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Sven Schnelle | 1767086 | 2012-02-01 22:06:45 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef NORTHBRIDGE_I5000_RAMINIT_H |
| 18 | #define NORTHBRIDGE_I5000_RAMINIT_H |
| 19 | |
| 20 | #include <types.h> |
| 21 | #include <arch/io.h> |
Sven Schnelle | 1767086 | 2012-02-01 22:06:45 +0100 | [diff] [blame] | 22 | |
| 23 | #define I5000_MAX_BRANCH 2 |
| 24 | #define I5000_MAX_CHANNEL 2 |
| 25 | #define I5000_MAX_DIMM_PER_CHANNEL 4 |
| 26 | #define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL) |
| 27 | |
| 28 | #define I5000_FBDRST 0x53 |
| 29 | |
| 30 | #define I5000_SPD_BUSY (1 << 12) |
| 31 | #define I5000_SPD_SBE (1 << 13) |
| 32 | #define I5000_SPD_WOD (1 << 14) |
| 33 | #define I5000_SPD_RDO (1 << 15) |
| 34 | |
| 35 | #define I5000_SPD0 0x74 |
| 36 | #define I5000_SPD1 0x76 |
| 37 | |
| 38 | #define I5000_SPDCMD0 0x78 |
| 39 | #define I5000_SPDCMD1 0x7c |
| 40 | |
| 41 | #define I5000_FBDHPC 0x4f |
| 42 | #define I5000_FBDST 0x4b |
| 43 | |
| 44 | #define I5000_FBDHPC_STATE_RESET 0x00 |
| 45 | #define I5000_FBDHPC_STATE_INIT 0x10 |
| 46 | #define I5000_FBDHPC_STATE_READY 0x20 |
| 47 | #define I5000_FBDHPC_STATE_ACTIVE 0x30 |
| 48 | |
| 49 | #define I5000_FBDISTS0 0x58 |
| 50 | #define I5000_FBDISTS1 0x5a |
| 51 | |
| 52 | #define I5000_FBDLVL0 0x44 |
| 53 | #define I5000_FBDLVL1 0x45 |
| 54 | |
| 55 | #define I5000_FBDICMD0 0x46 |
| 56 | #define I5000_FBDICMD1 0x47 |
| 57 | |
| 58 | #define I5000_FBDICMD_IDLE 0x00 |
| 59 | #define I5000_FBDICMD_TS0 0x80 |
| 60 | #define I5000_FBDICMD_TS1 0x90 |
| 61 | #define I5000_FBDICMD_TS2 0xa0 |
| 62 | #define I5000_FBDICMD_TS3 0xb0 |
| 63 | #define I5000_FBDICMD_TS2_MERGE 0xd0 |
| 64 | #define I5000_FBDICMD_TS2_NOMERGE 0xe0 |
| 65 | #define I5000_FBDICMD_ALL_ONES 0xf0 |
| 66 | |
| 67 | #define I5000_AMBPRESENT0 0x64 |
| 68 | #define I5000_AMBPRESENT1 0x66 |
| 69 | |
| 70 | #define I5000_FBDSBTXCFG0 0xc0 |
| 71 | #define I5000_FBDSBTXCFG1 0xc1 |
| 72 | |
| 73 | #define I5000_PROCENABLE 0xf0 |
| 74 | #define I5000_FBD0IBPORTCTL 0x180 |
| 75 | #define I5000_FBD0IBTXPAT2EN 0x1a8 |
| 76 | #define I5000_FBD0IBRXPAT2EN 0x1ac |
| 77 | |
| 78 | #define I5000_FBD0IBTXMSK 0x18c |
| 79 | #define I5000_FBD0IBRXMSK 0x190 |
| 80 | |
| 81 | #define I5000_FBDPLLCTRL 0x1c0 |
| 82 | |
| 83 | /* dev 16, function 1 registers */ |
| 84 | #define I5000_MC 0x40 |
| 85 | #define I5000_DRTA 0x48 |
| 86 | #define I5000_DRTB 0x4c |
| 87 | #define I5000_ERRPERR 0x50 |
| 88 | #define I5000_MCA 0x58 |
| 89 | #define I5000_TOLM 0x6c |
| 90 | #define I5000_MIR0 0x80 |
| 91 | #define I5000_MIR1 0x84 |
| 92 | #define I5000_MIR2 0x88 |
| 93 | #define I5000_AMIR0 0x8c |
| 94 | #define I5000_AMIR1 0x90 |
| 95 | #define I5000_AMIR2 0x94 |
| 96 | |
| 97 | #define I5000_FERR_FAT_FBD 0x98 |
| 98 | #define I5000_NERR_FAT_FBD 0x9c |
| 99 | #define I5000_FERR_NF_FBD 0xa0 |
| 100 | #define I5000_NERR_NF_FBD 0xa4 |
| 101 | #define I5000_EMASK_FBD 0xa8 |
| 102 | #define I5000_ERR0_FBD 0xac |
| 103 | #define I5000_ERR1_FBD 0xb0 |
| 104 | #define I5000_ERR2_FBD 0xb4 |
| 105 | #define I5000_MCERR_FBD 0xb8 |
| 106 | #define I5000_NRECMEMA 0xbe |
| 107 | #define I5000_NRECMEMB 0xc0 |
| 108 | #define I5000_NRECFGLOG 0xc4 |
| 109 | #define I5000_NRECMEMA 0xbe |
| 110 | #define I5000_NRECFBDA 0xc8 |
| 111 | #define I5000_NRECFBDB 0xcc |
| 112 | #define I5000_NRECFBDC 0xd0 |
| 113 | #define I5000_NRECFBDD 0xd4 |
| 114 | #define I5000_NRECFBDE 0xd8 |
| 115 | |
| 116 | #define I5000_REDMEMB 0x7c |
| 117 | #define I5000_RECMEMA 0xe2 |
| 118 | #define I5000_RECMEMB 0xe4 |
| 119 | #define I5000_RECFGLOG 0xe8 |
| 120 | #define I5000_RECFBDA 0xec |
| 121 | #define I5000_RECFBDB 0xf0 |
| 122 | #define I5000_RECFBDC 0xf4 |
| 123 | #define I5000_RECFBDD 0xf8 |
| 124 | #define I5000_RECFBDE 0xfc |
| 125 | |
| 126 | #define I5000_FBDTOHOSTGRCFG0 0x160 |
| 127 | #define I5000_FBDTOHOSTGRCFG1 0x164 |
| 128 | #define I5000_HOSTTOFBDGRCFG 0x168 |
| 129 | #define I5000_GRFBDLVLDCFG 0x16c |
| 130 | #define I5000_GRHOSTFULLCFG 0x16d |
| 131 | #define I5000_GRBUBBLECFG 0x16e |
| 132 | #define I5000_GRFBDTOHOSTDBLCFG 0x16f |
| 133 | |
| 134 | /* dev 16, function 2 registers */ |
| 135 | #define I5000_FERR_GLOBAL 0x40 |
| 136 | #define I5000_NERR_GLOBAL 0x44 |
| 137 | |
| 138 | /* dev 21, function 0 registers */ |
| 139 | #define I5000_MTR0 0x80 |
| 140 | #define I5000_MTR1 0x84 |
| 141 | #define I5000_MTR2 0x88 |
| 142 | #define I5000_MTR3 0x8c |
| 143 | #define I5000_DMIR0 0x90 |
| 144 | #define I5000_DMIR1 0x94 |
| 145 | #define I5000_DMIR2 0x98 |
| 146 | #define I5000_DMIR3 0x9c |
| 147 | #define I5000_DMIR4 0xa0 |
| 148 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 149 | #define DEFAULT_AMBASE ((u8 *)0xfe000000) |
Sven Schnelle | 1767086 | 2012-02-01 22:06:45 +0100 | [diff] [blame] | 150 | |
| 151 | /* AMB function 1 registers */ |
| 152 | #define AMB_FBDSBCFGNXT 0x54 |
| 153 | #define AMB_FBDLOCKTO 0x68 |
| 154 | #define AMB_EMASK 0x8c |
| 155 | #define AMB_FERR 0x90 |
| 156 | #define AMB_NERR 0x94 |
| 157 | #define AMB_CMD2DATANXT 0xe8 |
| 158 | |
| 159 | /* AMB function 3 registers */ |
| 160 | #define AMB_DAREFTC 0x70 |
| 161 | #define AMB_DSREFTC 0x74 |
| 162 | #define AMB_DRT 0x78 |
| 163 | #define AMB_DRC 0x7c |
| 164 | |
| 165 | #define AMB_MBCSR 0x40 |
| 166 | #define AMB_MBADDR 0x44 |
| 167 | #define AMB_MBLFSRSED 0xa4 |
| 168 | |
| 169 | /* AMB function 4 registers */ |
| 170 | #define AMB_DCALCSR 0x40 |
| 171 | #define AMB_DCALADDR 0x44 |
| 172 | #define AMB_DCALCSR_START (1 << 31) |
| 173 | |
| 174 | #define AMB_DCALCSR_OPCODE_NOP 0x00 |
| 175 | #define AMB_DCALCSR_OPCODE_REFRESH 0x01 |
| 176 | #define AMB_DCALCSR_OPCODE_PRECHARGE 0x02 |
| 177 | #define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03 |
| 178 | #define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05 |
| 179 | #define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c |
| 180 | #define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d |
| 181 | |
| 182 | #define AMB_DDR2ODTC 0xfc |
| 183 | |
| 184 | #define FBDIMM_SPD_SDRAM_ADDRESSING 0x04 |
| 185 | #define FBDIMM_SPD_MODULE_ORGANIZATION 0x07 |
| 186 | #define FBDIMM_SPD_FTB 0x08 |
| 187 | #define FBDIMM_SPD_MTB_DIVIDEND 0x09 |
| 188 | #define FBDIMM_SPD_MTB_DIVISOR 0x0a |
| 189 | #define FBDIMM_SPD_MIN_TCK 0x0b |
| 190 | #define FBDIMM_SPD_CAS_LATENCIES 0x0d |
| 191 | #define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e |
| 192 | #define FBDIMM_SPD_T_WR 0x10 |
| 193 | #define FBDIMM_SPD_T_RCD 0x13 |
| 194 | #define FBDIMM_SPD_T_RRD 0x14 |
| 195 | #define FBDIMM_SPD_T_RP 0x15 |
| 196 | #define FBDIMM_SPD_T_RAS_RC_MSB 0x16 |
| 197 | #define FBDIMM_SPD_T_RAS 0x17 |
| 198 | #define FBDIMM_SPD_T_RC 0x18 |
| 199 | #define FBDIMM_SPD_T_RFC 0x19 |
| 200 | #define FBDIMM_SPD_T_WTR 0x1b |
| 201 | #define FBDIMM_SPD_T_RTP 0x1c |
| 202 | #define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d |
| 203 | #define FBDIMM_SPD_ODT 0x4f |
| 204 | #define FBDIMM_SPD_T_REFI 0x20 |
| 205 | #define FBDIMM_SPD_T_BB 0x83 |
| 206 | #define FBDIMM_SPD_CMD2DATA_800 0x54 |
| 207 | #define FBDIMM_SPD_CMD2DATA_667 0x55 |
| 208 | #define FBDIMM_SPD_CMD2DATA_533 0x56 |
| 209 | |
| 210 | void i5000_fbdimm_init(void); |
| 211 | |
| 212 | #define I5000_BURST4 0x01 |
| 213 | #define I5000_BURST8 0x02 |
| 214 | #define I5000_BURST_CHOP 0x80 |
| 215 | |
| 216 | #define I5000_ODT_50 4 |
| 217 | #define I5000_ODT_75 2 |
| 218 | #define I5000_ODT_150 1 |
| 219 | |
| 220 | enum ddr_speeds { |
| 221 | DDR_533MHZ, |
| 222 | DDR_667MHZ, |
| 223 | DDR_MAX, |
| 224 | }; |
| 225 | |
| 226 | struct i5000_fbdimm { |
| 227 | struct i5000_fbd_branch *branch; |
| 228 | struct i5000_fbd_channel *channel; |
| 229 | struct i5000_fbd_setup *setup; |
| 230 | enum ddr_speeds speed; |
| 231 | int num; |
| 232 | int present:1; |
| 233 | u32 ambase; |
| 234 | |
| 235 | /* SPD data */ |
| 236 | u8 amb_personality_bytes[14]; |
| 237 | u8 banks; |
| 238 | u8 rows; |
| 239 | u8 columns; |
| 240 | u8 ranks; |
| 241 | u8 odt; |
| 242 | u8 sdram_width; |
| 243 | u8 mtb_divisor; |
| 244 | u8 mtb_dividend; |
| 245 | u8 t_ck_min; |
| 246 | u8 min_cas_latency; |
| 247 | u8 t_rrd; |
| 248 | u16 t_rfc; |
| 249 | u8 t_wtr; |
| 250 | u8 t_refi; |
| 251 | u8 cmd2datanxt[DDR_MAX]; |
| 252 | |
| 253 | u16 vendor; |
| 254 | u16 device; |
| 255 | |
| 256 | /* memory rank size in MB */ |
| 257 | int ranksize; |
| 258 | }; |
| 259 | |
| 260 | struct i5000_fbd_channel { |
| 261 | struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL]; |
| 262 | struct i5000_fbd_branch *branch; |
| 263 | struct i5000_fbd_setup *setup; |
| 264 | int num; |
| 265 | int used; |
| 266 | int highest_amb; |
| 267 | int columns; |
| 268 | int rows; |
| 269 | int ranks; |
| 270 | int banks; |
| 271 | int width; |
| 272 | /* memory size in MB on this channel */ |
| 273 | int totalmem; |
| 274 | }; |
| 275 | |
| 276 | struct i5000_fbd_branch { |
| 277 | struct i5000_fbd_channel channel[I5000_MAX_CHANNEL]; |
| 278 | struct i5000_fbd_setup *setup; |
Antonello Dettori | 1004710 | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 279 | pci_devfn_t branchdev; |
Sven Schnelle | 1767086 | 2012-02-01 22:06:45 +0100 | [diff] [blame] | 280 | int num; |
| 281 | int used; |
| 282 | /* memory size in MB on this branch */ |
| 283 | int totalmem; |
| 284 | }; |
| 285 | |
| 286 | enum odt { |
| 287 | ODT_150OHM=1, |
| 288 | ODT_50OHM=4, |
| 289 | ODT_75OHM=2, |
| 290 | }; |
| 291 | |
| 292 | enum bl { |
| 293 | BL_BL4=1, |
| 294 | BL_BL8=2, |
| 295 | }; |
| 296 | |
| 297 | struct i5000_fbd_setup { |
| 298 | struct i5000_fbd_branch branch[I5000_MAX_BRANCH]; |
| 299 | struct i5000_fbdimm *dimms[I5000_MAX_DIMMS]; |
| 300 | enum bl bl; |
| 301 | enum ddr_speeds ddr_speed; |
| 302 | |
| 303 | int single_channel:1; |
| 304 | u32 tolm; |
| 305 | |
| 306 | /* global SDRAM timing parameters */ |
| 307 | u8 t_al; |
| 308 | u8 t_cl; |
| 309 | u8 t_ras; |
| 310 | u8 t_wrc; |
| 311 | u8 t_rc; |
| 312 | u8 t_rfc; |
| 313 | u8 t_rrd; |
| 314 | u8 t_ref; |
| 315 | u8 t_w2rdr; |
| 316 | u8 t_r2w; |
| 317 | u8 t_w2r; |
| 318 | u8 t_r2r; |
| 319 | u8 t_w2w; |
| 320 | u8 t_wtr; |
| 321 | u8 t_rcd; |
| 322 | u8 t_rp; |
| 323 | u8 t_wr; |
| 324 | u8 t_rtp; |
| 325 | /* memory size in MB */ |
| 326 | int totalmem; |
| 327 | }; |
| 328 | |
| 329 | int mainboard_set_fbd_clock(int); |
| 330 | #define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff))) |
| 331 | #endif |