Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 23 | #include <delay.h> |
| 24 | |
| 25 | #include <stdint.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/romcc_io.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <device/pnp_def.h> |
| 30 | #include <cpu/x86/lapic.h> |
| 31 | |
| 32 | #include "option_table.h" |
| 33 | #include "pc80/mc146818rtc_early.c" |
| 34 | |
| 35 | #include "pc80/serial.c" |
Stefan Reinauer | 5a1f597 | 2010-03-31 14:34:40 +0000 | [diff] [blame] | 36 | #include "console/console.c" |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 37 | #include <cpu/x86/bist.h> |
| 38 | |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 39 | #include "lib/ramtest.c" |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 40 | #include "southbridge/intel/i3100/i3100_early_smbus.c" |
| 41 | #include "southbridge/intel/i3100/i3100_early_lpc.c" |
| 42 | #include "reset.c" |
| 43 | #include "superio/intel/i3100/i3100_early_serial.c" |
| 44 | #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" |
| 45 | |
| 46 | /* Data */ |
| 47 | #define UART_RBR 0x00 |
| 48 | #define UART_TBR 0x00 |
| 49 | |
| 50 | /* Control */ |
| 51 | #define UART_IER 0x01 |
| 52 | #define UART_IIR 0x02 |
| 53 | #define UART_FCR 0x02 |
| 54 | #define UART_LCR 0x03 |
| 55 | #define UART_MCR 0x04 |
| 56 | #define UART_DLL 0x00 |
| 57 | #define UART_DLM 0x01 |
| 58 | |
| 59 | /* Status */ |
| 60 | #define UART_LSR 0x05 |
| 61 | #define UART_MSR 0x06 |
| 62 | #define UART_SCR 0x07 |
| 63 | |
| 64 | #define SIO_GPIO_BASE 0x680 |
| 65 | #define SIO_XBUS_BASE 0x4880 |
| 66 | |
| 67 | #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) |
| 68 | #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) |
| 69 | |
| 70 | #define IA32_PERF_STS 0x198 |
| 71 | #define IA32_PERF_CTL 0x199 |
| 72 | #define MSR_THERM2_CTL 0x19D |
| 73 | #define IA32_MISC_ENABLES 0x1A0 |
| 74 | |
| 75 | /* SATA */ |
| 76 | #define SATA_MAP 0x90 |
| 77 | |
| 78 | #define SATA_MODE_IDE 0x00 |
| 79 | #define SATA_MODE_AHCI 0x01 |
| 80 | |
| 81 | /* RCBA registers */ |
| 82 | #define RCBA 0xF0 |
| 83 | #define DEFAULT_RCBA 0xFEA00000 |
| 84 | |
| 85 | #define RCBA_RPC 0x0224 /* 32 bit */ |
| 86 | |
| 87 | #define RCBA_TCTL 0x3000 /* 8 bit */ |
| 88 | |
| 89 | #define RCBA_D31IP 0x3100 /* 32 bit */ |
| 90 | #define RCBA_D30IP 0x3104 /* 32 bit */ |
| 91 | #define RCBA_D29IP 0x3108 /* 32 bit */ |
| 92 | #define RCBA_D28IP 0x310C /* 32 bit */ |
| 93 | #define RCBA_D31IR 0x3140 /* 16 bit */ |
| 94 | #define RCBA_D30IR 0x3142 /* 16 bit */ |
| 95 | #define RCBA_D29IR 0x3144 /* 16 bit */ |
| 96 | #define RCBA_D28IR 0x3146 /* 16 bit */ |
| 97 | |
| 98 | #define RCBA_RTC 0x3400 /* 32 bit */ |
| 99 | #define RCBA_HPTC 0x3404 /* 32 bit */ |
| 100 | #define RCBA_GCS 0x3410 /* 32 bit */ |
| 101 | #define RCBA_BUC 0x3414 /* 8 bit */ |
| 102 | #define RCBA_FD 0x3418 /* 32 bit */ |
| 103 | #define RCBA_PRC 0x341C /* 32 bit */ |
| 104 | |
| 105 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 106 | { |
| 107 | /* nothing to do */ |
| 108 | } |
| 109 | static inline int spd_read_byte(u16 device, u8 address) |
| 110 | { |
| 111 | return smbus_read_byte(device, address); |
| 112 | } |
| 113 | |
| 114 | #include "northbridge/intel/i3100/raminit.h" |
| 115 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 116 | #include "northbridge/intel/i3100/memory_initialized.c" |
| 117 | #include "northbridge/intel/i3100/raminit.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 118 | #include "lib/generic_sdram.c" |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 119 | #include "northbridge/intel/i3100/reset_test.c" |
| 120 | #include "debug.c" |
| 121 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 122 | void early_config(void) { |
| 123 | device_t dev; |
| 124 | u32 gcs, rpc, fd; |
| 125 | |
| 126 | /* Enable RCBA */ |
| 127 | pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); |
| 128 | |
| 129 | /* Disable watchdog */ |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 130 | gcs = read32(DEFAULT_RCBA + RCBA_GCS); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 131 | gcs |= (1 << 5); /* No reset */ |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 132 | write32(DEFAULT_RCBA + RCBA_GCS, gcs); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 133 | |
| 134 | /* Configure PCIe port B as 4x */ |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 135 | rpc = read32(DEFAULT_RCBA + RCBA_RPC); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 136 | rpc |= (3 << 0); |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 137 | write32(DEFAULT_RCBA + RCBA_RPC, rpc); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 138 | |
| 139 | /* Disable Modem, Audio, PCIe ports 2/3/4 */ |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 140 | fd = read32(DEFAULT_RCBA + RCBA_FD); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 141 | fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 142 | write32(DEFAULT_RCBA + RCBA_FD, fd); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 143 | |
| 144 | /* Enable HPET */ |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 145 | write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 146 | |
| 147 | /* Improve interrupt routing |
| 148 | * D31:F2 SATA INTB# -> PIRQD |
| 149 | * D31:F3 SMBUS INTB# -> PIRQD |
| 150 | * D31:F4 CHAP INTD# -> PIRQA |
| 151 | * D29:F0 USB1#1 INTA# -> PIRQH |
| 152 | * D29:F1 USB1#2 INTB# -> PIRQD |
| 153 | * D29:F7 USB2 INTA# -> PIRQH |
| 154 | * D28:F0 PCIe Port 1 INTA# -> PIRQE |
| 155 | */ |
| 156 | |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 157 | write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230); |
| 158 | write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210); |
| 159 | write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237); |
| 160 | write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 161 | |
| 162 | /* Setup sata mode */ |
| 163 | pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); |
| 164 | } |
| 165 | |
Stefan Reinauer | 6d1b0d8 | 2010-04-13 00:02:20 +0000 | [diff] [blame^] | 166 | void main(unsigned long bist) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 167 | { |
| 168 | /* int boot_mode = 0; */ |
| 169 | |
| 170 | static const struct mem_controller mch[] = { |
| 171 | { |
| 172 | .node_id = 0, |
| 173 | .f0 = PCI_DEV(0, 0x00, 0), |
| 174 | .f1 = PCI_DEV(0, 0x00, 1), |
| 175 | .f2 = PCI_DEV(0, 0x00, 2), |
| 176 | .f3 = PCI_DEV(0, 0x00, 3), |
| 177 | .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 }, |
| 178 | .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 }, |
| 179 | } |
| 180 | }; |
| 181 | |
| 182 | if (bist == 0) { |
| 183 | enable_lapic(); |
| 184 | } |
| 185 | |
| 186 | /* Setup the console */ |
| 187 | i3100_enable_superio(); |
| 188 | i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE); |
| 189 | uart_init(); |
| 190 | console_init(); |
| 191 | |
| 192 | /* Halt if there was a built in self test failure */ |
| 193 | report_bist_failure(bist); |
| 194 | |
| 195 | /* Perform early board specific init */ |
| 196 | early_config(); |
| 197 | |
| 198 | /* Prevent the TCO timer from rebooting us */ |
| 199 | i3100_halt_tco_timer(); |
| 200 | |
| 201 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 202 | enable_smbus(); |
| 203 | |
| 204 | /* Enable SpeedStep and automatic thermal throttling */ |
| 205 | { |
| 206 | msr_t msr; |
| 207 | u16 perf; |
| 208 | |
| 209 | msr = rdmsr(IA32_MISC_ENABLES); |
| 210 | msr.lo |= (1 << 3) | (1 << 16); |
| 211 | wrmsr(IA32_MISC_ENABLES, msr); |
| 212 | |
| 213 | /* Set CPU frequency/voltage to maximum */ |
| 214 | |
| 215 | /* Read performance status register and keep |
| 216 | * bits 47:32, where BUS_RATIO_MAX and VID_MAX |
| 217 | * are encoded |
| 218 | */ |
| 219 | msr = rdmsr(IA32_PERF_STS); |
| 220 | perf = msr.hi & 0x0000ffff; |
| 221 | |
| 222 | /* Write VID_MAX & BUS_RATIO_MAX to |
| 223 | * performance control register |
| 224 | */ |
| 225 | msr = rdmsr(IA32_PERF_CTL); |
| 226 | msr.lo &= 0xffff0000; |
| 227 | msr.lo |= perf; |
| 228 | wrmsr(IA32_PERF_CTL, msr); |
| 229 | } |
| 230 | |
| 231 | /* Initialize memory */ |
| 232 | sdram_initialize(ARRAY_SIZE(mch), mch); |
| 233 | } |
| 234 | |