Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Hal Martin | de7f8d3 | 2017-10-28 10:58:08 +0000 | [diff] [blame] | 2 | |
Nico Huber | b0b25c8 | 2020-03-21 20:35:12 +0100 | [diff] [blame] | 3 | chip northbridge/intel/sandybridge # FIXME: check gfx |
| 4 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
Hal Martin | de7f8d3 | 2017-10-28 10:58:08 +0000 | [diff] [blame] | 5 | register "gpu_dp_b_hotplug" = "4" |
| 6 | register "gpu_dp_c_hotplug" = "4" |
| 7 | register "gpu_dp_d_hotplug" = "4" |
Angel Pons | 0d4c593 | 2020-01-01 19:53:17 +0100 | [diff] [blame] | 8 | |
Angel Pons | d2489ee | 2021-05-17 11:05:29 +0200 | [diff] [blame] | 9 | device cpu_cluster 0 on |
Hal Martin | de7f8d3 | 2017-10-28 10:58:08 +0000 | [diff] [blame] | 10 | chip cpu/intel/model_206ax # FIXME: check all registers |
Angel Pons | 6f56a23 | 2021-01-04 17:02:23 +0100 | [diff] [blame] | 11 | register "acpi_c1" = "1" |
| 12 | register "acpi_c2" = "3" |
| 13 | register "acpi_c3" = "5" |
Angel Pons | c56c723 | 2021-05-17 11:03:55 +0200 | [diff] [blame] | 14 | device lapic 0 on end |
Arthur Heymans | b3f2323 | 2019-01-21 17:48:55 +0100 | [diff] [blame] | 15 | device lapic 0xacac off end |
Hal Martin | de7f8d3 | 2017-10-28 10:58:08 +0000 | [diff] [blame] | 16 | end |
| 17 | end |
Angel Pons | bceea67 | 2021-05-17 10:58:36 +0200 | [diff] [blame] | 18 | device domain 0 on |
Angel Pons | 0d4c593 | 2020-01-01 19:53:17 +0100 | [diff] [blame] | 19 | device pci 00.0 on # Host bridge |
| 20 | subsystemid 0x8086 0x2010 |
| 21 | end |
| 22 | device pci 01.0 on # PCIe Bridge for discrete graphics |
| 23 | subsystemid 0x8086 0x2010 |
| 24 | end |
| 25 | device pci 01.1 on # PCIe Bridge for discrete graphics |
| 26 | subsystemid 0x8086 0x2010 |
| 27 | end |
| 28 | device pci 02.0 on # Internal graphics VGA controller |
| 29 | subsystemid 0x8086 0x2211 |
| 30 | end |
| 31 | |
| 32 | subsystemid 0x8086 0x7270 inherit |
| 33 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
Hal Martin | de7f8d3 | 2017-10-28 10:58:08 +0000 | [diff] [blame] | 34 | register "docking_supported" = "1" |
| 35 | register "gen1_dec" = "0x0000164d" |
| 36 | register "gen2_dec" = "0x000c0681" |
| 37 | register "gen3_dec" = "0x000406f1" |
| 38 | register "gen4_dec" = "0x000c06a1" |
| 39 | register "gpi7_routing" = "2" |
Angel Pons | af4bd56 | 2021-12-28 13:05:56 +0100 | [diff] [blame] | 40 | register "pcie_port_coalesce" = "true" |
Hal Martin | de7f8d3 | 2017-10-28 10:58:08 +0000 | [diff] [blame] | 41 | register "sata_interface_speed_support" = "0x3" |
| 42 | # Intense PC SATA portmap: |
| 43 | # Port 0: internal 2.5" bay |
| 44 | # Port 1: optional FACE module |
| 45 | # Port 2: rear eSATA |
| 46 | # Port 3: rear eSATA |
| 47 | # Port 4: mSATA |
| 48 | # Port 5: optional FACE module |
| 49 | # enable ALL ports (FACE module REQUIRED for ports 1&5) |
| 50 | register "sata_port_map" = "0x3f" |
| 51 | # enable ONLY ports present on stock MintBox/Intense PC |
| 52 | #register "sata_port_map" = "0x1d" |
| 53 | register "superspeed_capable_ports" = "0x0000000f" |
| 54 | register "xhci_overcurrent_mapping" = "0x00000c03" |
| 55 | register "xhci_switchable_ports" = "0x0000000f" |
| 56 | register "spi_uvscc" = "0x2005" |
| 57 | register "spi_lvscc" = "0x2005" |
| 58 | |
Angel Pons | 0d4c593 | 2020-01-01 19:53:17 +0100 | [diff] [blame] | 59 | device pci 14.0 on end # USB 3.0 Controller |
| 60 | device pci 16.0 off end # Management Engine Interface 1 |
| 61 | device pci 16.1 off end # Management Engine Interface 2 |
| 62 | device pci 16.2 off end # Management Engine IDE-R |
| 63 | device pci 16.3 off end # Management Engine KT |
| 64 | device pci 19.0 on end # Intel Gigabit Ethernet |
| 65 | device pci 1a.0 on end # USB2 EHCI #2 |
| 66 | device pci 1b.0 on end # High Definition Audio |
| 67 | device pci 1c.0 on end # PCIe Port #1 |
| 68 | device pci 1c.1 on end # PCIe Port #2 |
| 69 | device pci 1c.2 on end # PCIe Port #3 |
| 70 | device pci 1c.3 off end # PCIe Port #4 |
| 71 | device pci 1c.4 on end # PCIe Port #5 |
| 72 | device pci 1c.5 off end # PCIe Port #6 |
| 73 | device pci 1c.6 off end # PCIe Port #7 |
| 74 | device pci 1c.7 off end # PCIe Port #8 |
| 75 | device pci 1d.0 on end # USB2 EHCI #1 |
| 76 | device pci 1e.0 off end # PCI bridge |
| 77 | device pci 1f.0 on end # LPC bridge |
| 78 | device pci 1f.2 on end # SATA Controller 1 |
| 79 | device pci 1f.3 on end # SMBus |
| 80 | device pci 1f.5 off end # SATA Controller 2 |
| 81 | device pci 1f.6 on end # Thermal |
Hal Martin | de7f8d3 | 2017-10-28 10:58:08 +0000 | [diff] [blame] | 82 | end |
| 83 | end |
| 84 | end |