Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 3 | |
| 4 | #include <stdint.h> |
Elyes HAOUAS | 10b65dc | 2018-06-16 18:39:26 +0200 | [diff] [blame] | 5 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 6 | #include "pch.h" |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 7 | |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame^] | 8 | void southbridge_configure_default_intmap(void) |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 9 | { |
| 10 | /* |
Nico Huber | 16a41cc | 2019-02-14 17:52:25 +0100 | [diff] [blame] | 11 | * For the PCH internal PCI functions, provide a reasonable |
| 12 | * default IRQ mapping that utilizes only PIRQ A to D. Higher |
| 13 | * PIRQs are sometimes used for other on-board chips that |
| 14 | * require an edge triggered interrupt which is not shareable. |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
Nico Huber | 16a41cc | 2019-02-14 17:52:25 +0100 | [diff] [blame] | 17 | /* |
| 18 | * We use a linear mapping for the pin numbers. They are not |
| 19 | * physical pins, and thus, have no relation between the dif- |
| 20 | * ferent devices. Only rule we must obey is that a single- |
| 21 | * function device has to use pin A. |
| 22 | */ |
| 23 | RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 24 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 25 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
Nico Huber | 16a41cc | 2019-02-14 17:52:25 +0100 | [diff] [blame] | 26 | RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) | |
| 27 | (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) | |
| 28 | (INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) | |
| 29 | (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP); |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 30 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 31 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
Nico Huber | 16a41cc | 2019-02-14 17:52:25 +0100 | [diff] [blame] | 32 | RCBA32(D25IP) = (INTA << D25IP_LIP); |
| 33 | RCBA32(D22IP) = (INTA << D22IP_MEI1IP); |
| 34 | RCBA32(D20IP) = (INTA << D20IP_XHCIIP); |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 35 | |
Nico Huber | 16a41cc | 2019-02-14 17:52:25 +0100 | [diff] [blame] | 36 | /* |
| 37 | * For the PIRQ allocation the following was taken into |
| 38 | * account: |
| 39 | * o Interrupts of the PCIe root ports are only about |
| 40 | * events at the ports, not downstream devices. So we |
| 41 | * don't expect many interrupts there and ignore them. |
| 42 | * o We don't expect to talk constantly to the ME either |
| 43 | * so ignore that, too. Same for SMBus and the thermal |
| 44 | * device. |
| 45 | * o Second SATA interface is only used in non-AHCI mode |
| 46 | * so unlikely to coexist with modern interfaces (e.g. |
| 47 | * xHCI). |
| 48 | * o An OS that knows USB3 will likely also know how to |
| 49 | * use MSI. |
| 50 | * |
| 51 | * The functions that might matter first: |
| 52 | * |
| 53 | * D31IP_SIP SATA 1 -> PIRQ A (MSI capable in AHCI mode) |
| 54 | * D31IP_SIP2 SATA 2 -> PIRQ B |
| 55 | * D29IP_E1P EHCI 1 -> PIRQ C |
| 56 | * D27IP_ZIP HDA -> PIRQ D (MSI capable) |
| 57 | * D26IP_E2P EHCI 2 -> PIRQ D |
| 58 | * D25IP_LIP GbE -> PIRQ B (MSI capable) |
| 59 | * D20IP_XHCIIP xHCI -> PIRQ B (MSI capable) |
| 60 | * |
| 61 | * D31IP_TTIP Thermal -> PIRQ B |
| 62 | * D31IP_SMIP SMBUS -> PIRQ A |
| 63 | * D28IP_* PCIe RP -> PIRQ A-D (MSI capable) |
| 64 | * D22IP_MEI1IP ME -> PIRQ A (MSI capable) |
| 65 | * |
| 66 | * Note, CPU-integrated functions seem to always use PIRQ A. |
| 67 | */ |
| 68 | #define _none 0 |
| 69 | DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB); |
| 70 | DIR_ROUTE(D29IR, PIRQC, _none, _none, _none); |
| 71 | DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 72 | DIR_ROUTE(D27IR, PIRQD, _none, _none, _none); |
| 73 | DIR_ROUTE(D26IR, PIRQD, _none, _none, _none); |
| 74 | DIR_ROUTE(D25IR, PIRQB, _none, _none, _none); |
| 75 | DIR_ROUTE(D22IR, PIRQA, _none, _none, _none); |
| 76 | DIR_ROUTE(D20IR, PIRQB, _none, _none, _none); |
| 77 | #undef _none |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 78 | |
| 79 | /* Enable IOAPIC (generic) */ |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 80 | RCBA16(OIC) = 0x0100; |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 81 | /* PCH BWG says to read back the IOAPIC enable register */ |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 82 | (void) RCBA16(OIC); |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 83 | } |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 84 | |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame^] | 85 | void southbridge_rcba_config(void) |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 86 | { |
| 87 | RCBA32(FD) = PCH_DISABLE_ALWAYS; |
| 88 | } |